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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : Intra_pred_pipeline.v
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// Generated : Aug 4, 2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Intra16x16,Intra4x4 prediction pipeline
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module Intra_pred_pipeline (clk,reset_n,mb_type_general,blk4x4_rec_counter,
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trigger_blk4x4_intra_pred,mb_num_v,mb_num_h,blk4x4_sum_counter,NextMB_IsSkip,
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Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
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Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
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Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
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Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
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Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
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Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
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Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
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Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
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Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
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Intra_mbAddrD_window,
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Intra4x4_predmode,blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,
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blk4x4_intra_calculate_counter,end_of_one_blk4x4_intra,
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blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,mbAddrC_availability,
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main_seed,plane_b_reg,plane_c_reg,
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Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_rd_addr
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);
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input clk,reset_n;
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input [3:0] mb_type_general;
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input [4:0] blk4x4_rec_counter;
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input trigger_blk4x4_intra_pred;
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input [3:0] mb_num_v,mb_num_h;
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input [2:0] blk4x4_sum_counter;
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input NextMB_IsSkip;
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input [1:0] Intra16x16_predmode;
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input [63:0] Intra4x4_predmode_CurrMb;
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input [1:0] Intra_chroma_predmode;
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input [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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input [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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input [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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input [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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input [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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input [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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input [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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input [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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input [7:0] Intra_mbAddrD_window;
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output [3:0] Intra4x4_predmode;
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output [2:0] blk4x4_intra_preload_counter;
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output [3:0] blk4x4_intra_precompute_counter;
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output [2:0] blk4x4_intra_calculate_counter;
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output end_of_one_blk4x4_intra;
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output blkAddrA_availability,blkAddrB_availability;
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output mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
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output [15:0] main_seed;
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output [11:0] plane_b_reg,plane_c_reg;
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output Intra_mbAddrB_RAM_rd;
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output [6:0] Intra_mbAddrB_RAM_rd_addr;
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reg [3:0] Intra4x4_predmode;
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reg [2:0] blk4x4_intra_preload_counter;
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reg [3:0] blk4x4_intra_precompute_counter;
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reg [2:0] blk4x4_intra_calculate_counter;
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reg [11:0] plane_b_reg,plane_c_reg;
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wire Intra_mbAddrB_RAM_rd;
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wire [6:0] Intra_mbAddrB_RAM_rd_addr;
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wire end_of_one_blk4x4_intra;
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wire blkAddrA_availability,blkAddrB_availability;
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wire mbAddrA_availability,mbAddrB_availability;
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//----------------------------------------------------------------------------------------
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//Intra4x4 prediction mode for current 4x4 block
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//----------------------------------------------------------------------------------------
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always @ (Intra4x4_predmode_CurrMb or blk4x4_rec_counter or mb_type_general)
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if (mb_type_general == `MB_Intra4x4)
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case (blk4x4_rec_counter)
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1 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[7:4];
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2 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[11:8];
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3 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[15:12];
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4 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[19:16];
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5 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[23:20];
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6 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[27:24];
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7 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[31:28];
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8 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[35:32];
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9 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[39:36];
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10:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[43:40];
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11:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[47:44];
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12:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[51:48];
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13:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[55:52];
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14:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[59:56];
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15:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[63:60];
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default:Intra4x4_predmode <= 4'b1111;
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endcase
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else
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Intra4x4_predmode <= 4'b1111;
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//availability for intra4x4 predmode = Intra4x4_DC only
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assign blkAddrA_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC &&
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blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8 ||
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blk4x4_rec_counter == 10) && mb_num_h == 0))? 1'b0:1'b1;
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assign blkAddrB_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC &&
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blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 ||
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blk4x4_rec_counter == 5) && mb_num_v == 0))? 1'b0:1'b1;
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//availability for whole intra predicted MB (both intra16x16 & intra4x4)
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//assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
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//assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
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assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0;
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assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0;
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assign mbAddrC_availability = (mb_type_general[3] && mb_num_v != 0 && mb_num_h != 10)? 1'b1:1'b0;
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//----------------------------------------------------------------------------------------
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//Intra prediction step control counter
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//----------------------------------------------------------------------------------------
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//1.Preload upper pels counter
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always @ (posedge clk)
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if (reset_n == 1'b0)
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blk4x4_intra_preload_counter <= 0;
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else if (trigger_blk4x4_intra_pred)
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begin
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//Chroma
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if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
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case (Intra_chroma_predmode)
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`Intra_chroma_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b011:3'b000;
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`Intra_chroma_Horizontal:blk4x4_intra_preload_counter <= 3'b000;
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`Intra_chroma_Vertical :blk4x4_intra_preload_counter <= 3'b011;
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`Intra_chroma_Plane :blk4x4_intra_preload_counter <= 3'b011;
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endcase
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//Luma
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// Intra16x16
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else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter == 0)
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case (Intra16x16_predmode)
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`Intra16x16_Vertical :blk4x4_intra_preload_counter <= 3'b101;
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`Intra16x16_Horizontal:blk4x4_intra_preload_counter <= 3'b000;
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`Intra16x16_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b101:3'b000;
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`Intra16x16_Plane :blk4x4_intra_preload_counter <= 3'b101;
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endcase
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// Intra4x4
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else if (mb_type_general[3:2] == 2'b11 && (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1
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|| blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5))
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case (Intra4x4_predmode)
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`Intra4x4_Vertical :blk4x4_intra_preload_counter <= 3'b010;
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`Intra4x4_Horizontal :blk4x4_intra_preload_counter <= 3'b000;
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`Intra4x4_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b010:3'b000;
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`Intra4x4_Diagonal_Down_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC
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`Intra4x4_Diagonal_Down_Right:blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
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`Intra4x4_Vertical_Right :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
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`Intra4x4_Horizontal_Down :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD
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`Intra4x4_Vertical_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC
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`Intra4x4_Horizontal_Up :blk4x4_intra_preload_counter <= 3'b000;
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endcase
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end
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else if (blk4x4_intra_preload_counter != 0)
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blk4x4_intra_preload_counter <= blk4x4_intra_preload_counter - 1;
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//2.Precomputation for plane mode counter
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always @ (posedge clk)
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if (reset_n == 1'b0)
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blk4x4_intra_precompute_counter <= 0;
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//Intra16x16 plane mode: 10 cycle + 1 cycle (seed)
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else if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_preload_counter == 3'b001)
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blk4x4_intra_precompute_counter <= 4'b1011;
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//Chroma8x8 plane mode: 6 cycle + 1 cycle (seed)
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else if ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_preload_counter == 3'b001)
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blk4x4_intra_precompute_counter <= 4'b0111;
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else if (blk4x4_intra_precompute_counter != 0)
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blk4x4_intra_precompute_counter <= blk4x4_intra_precompute_counter - 1;
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//3.Intra prediction calculation counter
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always @ (posedge clk)
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if (reset_n == 1'b0)
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blk4x4_intra_calculate_counter <= 0;
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//Intra16x16 Luma
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else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
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begin
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if (blk4x4_rec_counter == 0)
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case (Intra16x16_predmode)
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`Intra16x16_Vertical:
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if (blk4x4_intra_preload_counter == 3'b001)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
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`Intra16x16_Horizontal:
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if (trigger_blk4x4_intra_pred)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
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`Intra16x16_DC:
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if (mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (!mbAddrB_availability && trigger_blk4x4_intra_pred)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
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`Intra16x16_Plane:
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if (blk4x4_intra_precompute_counter == 4'b0001)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
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endcase
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else
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begin
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if (trigger_blk4x4_intra_pred)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
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end
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end
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//Intra4x4 Luma
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else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
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begin
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if (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 ||
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blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5)
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case (Intra4x4_predmode)
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`Intra4x4_Horizontal,`Intra4x4_Horizontal_Up://Intra4x4 prediction modes do NOT need preload
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if (trigger_blk4x4_intra_pred)
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blk4x4_intra_calculate_counter <= 3'b100;
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else if (blk4x4_intra_calculate_counter != 0)
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|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 236 |
|
|
`Intra4x4_DC: //Intra4x4 prediction modes may or may NOT need preload
|
| 237 |
|
|
if (mbAddrB_availability == 1'b1) //need reload
|
| 238 |
|
|
begin
|
| 239 |
|
|
if (blk4x4_intra_preload_counter == 3'b001)
|
| 240 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 241 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 242 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 243 |
|
|
end
|
| 244 |
|
|
else //do not need reload
|
| 245 |
|
|
begin
|
| 246 |
|
|
if (trigger_blk4x4_intra_pred)
|
| 247 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 248 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 249 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 250 |
|
|
end
|
| 251 |
|
|
default: //other Intra4x4 prediction modes that needs preload
|
| 252 |
|
|
if (blk4x4_intra_preload_counter == 3'b001)
|
| 253 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 254 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 255 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 256 |
|
|
endcase
|
| 257 |
|
|
else if (trigger_blk4x4_intra_pred)
|
| 258 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 259 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 260 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 261 |
|
|
end
|
| 262 |
|
|
//Chroma
|
| 263 |
|
|
else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
|
| 264 |
|
|
case (Intra_chroma_predmode)
|
| 265 |
|
|
`Intra_chroma_DC:
|
| 266 |
|
|
if ((mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) || (!mbAddrB_availability && trigger_blk4x4_intra_pred))
|
| 267 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 268 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 269 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 270 |
|
|
`Intra_chroma_Horizontal:
|
| 271 |
|
|
if (trigger_blk4x4_intra_pred)
|
| 272 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 273 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 274 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 275 |
|
|
`Intra_chroma_Vertical:
|
| 276 |
|
|
if (blk4x4_intra_preload_counter == 3'b001)
|
| 277 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 278 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 279 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 280 |
|
|
`Intra_chroma_Plane: //plane
|
| 281 |
|
|
if (blk4x4_intra_precompute_counter == 4'b0001)
|
| 282 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 283 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 284 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 285 |
|
|
endcase
|
| 286 |
|
|
else
|
| 287 |
|
|
begin
|
| 288 |
|
|
if (trigger_blk4x4_intra_pred)
|
| 289 |
|
|
blk4x4_intra_calculate_counter <= 3'b100;
|
| 290 |
|
|
else if (blk4x4_intra_calculate_counter != 0)
|
| 291 |
|
|
blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1;
|
| 292 |
|
|
end
|
| 293 |
|
|
|
| 294 |
|
|
assign end_of_one_blk4x4_intra = (blk4x4_intra_calculate_counter == 3'd1)? 1'b1:1'b0;
|
| 295 |
|
|
//----------------------------------------------------------------------------------------
|
| 296 |
|
|
//1.Preload
|
| 297 |
|
|
// For intra4x4,preload_counter == 3'b010 means preload mbAddrC or mbAddrD
|
| 298 |
|
|
// preload_counter == 3'b001 means preload mbAddrB
|
| 299 |
|
|
//----------------------------------------------------------------------------------------
|
| 300 |
|
|
wire [6:0] Intra_mbAddrB_RAM_addr_bp;
|
| 301 |
|
|
reg [5:0] Intra_mbAddrB_RAM_addr_sp;
|
| 302 |
|
|
reg [1:0] Intra_mbAddrB_RAM_addr_ip;
|
| 303 |
|
|
|
| 304 |
|
|
wire Intra_mbAddrB_RAM_rd_for_mbAddrD;
|
| 305 |
|
|
assign Intra_mbAddrB_RAM_rd_for_mbAddrD = (blk4x4_sum_counter == 3'b0 &&
|
| 306 |
|
|
(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23) &&
|
| 307 |
|
|
mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip)? 1'b1:1'b0;
|
| 308 |
|
|
|
| 309 |
|
|
assign Intra_mbAddrB_RAM_rd = ((blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) || Intra_mbAddrB_RAM_rd_for_mbAddrD)? 1'b1:1'b0;
|
| 310 |
|
|
|
| 311 |
|
|
// base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr
|
| 312 |
|
|
assign Intra_mbAddrB_RAM_addr_bp = (Intra_mbAddrB_RAM_rd)? ((blk4x4_rec_counter > 15)? ((blk4x4_rec_counter > 19)? 7'd66:7'd44):0):0;
|
| 313 |
|
|
|
| 314 |
|
|
// shift pointer,x2 for chroma,x4 for luma
|
| 315 |
|
|
always @ (Intra_mbAddrB_RAM_rd_for_mbAddrD or Intra_mbAddrB_RAM_rd or mb_num_h or
|
| 316 |
|
|
blk4x4_rec_counter or Intra4x4_predmode or blk4x4_intra_preload_counter)
|
| 317 |
|
|
if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
| 318 |
|
|
Intra_mbAddrB_RAM_addr_sp <= (blk4x4_rec_counter < 16)? {mb_num_h,2'b0}:{1'b0,mb_num_h,1'b0};
|
| 319 |
|
|
else if (Intra_mbAddrB_RAM_rd)
|
| 320 |
|
|
begin
|
| 321 |
|
|
if (blk4x4_rec_counter < 16)
|
| 322 |
|
|
Intra_mbAddrB_RAM_addr_sp <= ((Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left
|
| 323 |
|
|
|| Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter == 5
|
| 324 |
|
|
&& blk4x4_intra_preload_counter == 3'b011)? //read for mbAddrC
|
| 325 |
|
|
{(mb_num_h + 1),2'b0}:{mb_num_h,2'b0};
|
| 326 |
|
|
else
|
| 327 |
|
|
Intra_mbAddrB_RAM_addr_sp <= {1'b0,mb_num_h,1'b0};
|
| 328 |
|
|
end
|
| 329 |
|
|
else
|
| 330 |
|
|
Intra_mbAddrB_RAM_addr_sp <= 0;
|
| 331 |
|
|
|
| 332 |
|
|
// pointer for relative address of each 4x4 block inside a MB
|
| 333 |
|
|
always @ (Intra_mbAddrB_RAM_rd or blk4x4_rec_counter or blk4x4_intra_preload_counter or
|
| 334 |
|
|
mb_type_general[3:2] or Intra4x4_predmode or Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
| 335 |
|
|
if (blk4x4_rec_counter < 16 && Intra_mbAddrB_RAM_rd) //luma
|
| 336 |
|
|
begin
|
| 337 |
|
|
if (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)
|
| 338 |
|
|
begin
|
| 339 |
|
|
if (mb_type_general[3:2] == 2'b10) //Intra16x16
|
| 340 |
|
|
case (blk4x4_intra_preload_counter)
|
| 341 |
|
|
3'b101:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 342 |
|
|
3'b100:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
| 343 |
|
|
3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
| 344 |
|
|
3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
| 345 |
|
|
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 346 |
|
|
endcase
|
| 347 |
|
|
else //Intra4x4
|
| 348 |
|
|
begin
|
| 349 |
|
|
if (blk4x4_intra_preload_counter == 3'b010) //For mbAddrB
|
| 350 |
|
|
case (blk4x4_rec_counter)
|
| 351 |
|
|
0:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 352 |
|
|
1:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
| 353 |
|
|
4:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
| 354 |
|
|
5:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
| 355 |
|
|
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 356 |
|
|
endcase
|
| 357 |
|
|
else if (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left
|
| 358 |
|
|
|| Intra4x4_predmode == `Intra4x4_Vertical_Left) //For mbAddrC
|
| 359 |
|
|
case (blk4x4_rec_counter)
|
| 360 |
|
|
0:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
| 361 |
|
|
1:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
| 362 |
|
|
4:Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
| 363 |
|
|
5:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
|
| 364 |
|
|
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 365 |
|
|
endcase
|
| 366 |
|
|
else //For mbAddrD
|
| 367 |
|
|
case (blk4x4_rec_counter)
|
| 368 |
|
|
1:Intra_mbAddrB_RAM_addr_ip <= 2'b00;
|
| 369 |
|
|
4:Intra_mbAddrB_RAM_addr_ip <= 2'b01;
|
| 370 |
|
|
5:Intra_mbAddrB_RAM_addr_ip <= 2'b10;
|
| 371 |
|
|
default:Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 372 |
|
|
endcase
|
| 373 |
|
|
end
|
| 374 |
|
|
end
|
| 375 |
|
|
else if (Intra_mbAddrB_RAM_rd_for_mbAddrD)
|
| 376 |
|
|
Intra_mbAddrB_RAM_addr_ip <= 2'b11;
|
| 377 |
|
|
else
|
| 378 |
|
|
Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 379 |
|
|
end
|
| 380 |
|
|
else if (Intra_mbAddrB_RAM_rd) //chroma
|
| 381 |
|
|
Intra_mbAddrB_RAM_addr_ip <= (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)? {1'b0,~blk4x4_intra_preload_counter[0]}:2'b01;
|
| 382 |
|
|
else
|
| 383 |
|
|
Intra_mbAddrB_RAM_addr_ip <= 0;
|
| 384 |
|
|
|
| 385 |
|
|
// pointer for each 4x4 block
|
| 386 |
|
|
assign Intra_mbAddrB_RAM_rd_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip;
|
| 387 |
|
|
|
| 388 |
|
|
//----------------------------------------------------------------------------------------
|
| 389 |
|
|
//2.Precomputation
|
| 390 |
|
|
// For Intra16x16 Luma Plane
|
| 391 |
|
|
// cycle11: x1 + x3 |
|
| 392 |
|
|
// cycle10: x2 + x5 |
|
| 393 |
|
|
// cycle9 : x4 + x6 |
|
| 394 |
|
|
// cycle8 : x8 + x7 | Vertical,V For Intra Chroma Plane
|
| 395 |
|
|
// cycle7 : calculate c cycle7: x1 + x3 |
|
| 396 |
|
|
// cycle6 : x1 + x3 | cycle6: x2 + x4 | Vertical,V
|
| 397 |
|
|
// cycle5 : x2 + x5 | cycle5: calculate c
|
| 398 |
|
|
// cycle4 : x4 + x6 | cycle4: x1 + x3 |
|
| 399 |
|
|
// cycle3 : x8 + x7 | Horizontal,H cycle3: x2 + x4 | Horizontal,H
|
| 400 |
|
|
// cycle2 : calculate a & b cycle2 : calculate a & b
|
| 401 |
|
|
// cycle1 : seed cycle1 : seed
|
| 402 |
|
|
//----------------------------------------------------------------------------------------
|
| 403 |
|
|
// 2.1 precomputation for HV:
|
| 404 |
|
|
reg [14:0] plane_HV_prev_in;
|
| 405 |
|
|
reg [7:0] plane_HV_A1,plane_HV_A2,plane_HV_B1,plane_HV_B2;
|
| 406 |
|
|
reg [1:0] plane_HV_shifter1_len,plane_HV_shifter2_len;
|
| 407 |
|
|
reg plane_HV_mux1_sel,plane_HV_mux2_sel;
|
| 408 |
|
|
reg plane_HV_Is7;
|
| 409 |
|
|
wire [14:0] plane_HV_out;
|
| 410 |
|
|
reg [14:0] plane_HV_out_reg;
|
| 411 |
|
|
|
| 412 |
|
|
plane_HV_precomputation plane_HV_precomputation (
|
| 413 |
|
|
.prev_in(plane_HV_prev_in),
|
| 414 |
|
|
.A1(plane_HV_A1),
|
| 415 |
|
|
.A2(plane_HV_A2),
|
| 416 |
|
|
.B1(plane_HV_B1),
|
| 417 |
|
|
.B2(plane_HV_B2),
|
| 418 |
|
|
.shifter1_len(plane_HV_shifter1_len),
|
| 419 |
|
|
.shifter2_len(plane_HV_shifter2_len),
|
| 420 |
|
|
.mux1_sel(plane_HV_mux1_sel),
|
| 421 |
|
|
.mux2_sel(plane_HV_mux2_sel),
|
| 422 |
|
|
.Is7(plane_HV_Is7),
|
| 423 |
|
|
.HV_out(plane_HV_out)
|
| 424 |
|
|
);
|
| 425 |
|
|
always @ (blk4x4_intra_precompute_counter or mb_type_general[2] or blk4x4_rec_counter or plane_HV_out_reg
|
| 426 |
|
|
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
| 427 |
|
|
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
| 428 |
|
|
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
| 429 |
|
|
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
| 430 |
|
|
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3
|
| 431 |
|
|
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
| 432 |
|
|
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
| 433 |
|
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
| 434 |
|
|
or Intra_mbAddrD_window)
|
| 435 |
|
|
//Intra16x16 plane
|
| 436 |
|
|
if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0)
|
| 437 |
|
|
case (blk4x4_intra_precompute_counter)
|
| 438 |
|
|
11,6: // x1,x3
|
| 439 |
|
|
begin
|
| 440 |
|
|
plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0;
|
| 441 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg8 :Intra_mbAddrB_reg8;
|
| 442 |
|
|
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg6 :Intra_mbAddrB_reg6;
|
| 443 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg10:Intra_mbAddrB_reg10;
|
| 444 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg4 :Intra_mbAddrB_reg4;
|
| 445 |
|
|
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01;
|
| 446 |
|
|
plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0;
|
| 447 |
|
|
end
|
| 448 |
|
|
10,5 : // x2,x5
|
| 449 |
|
|
begin
|
| 450 |
|
|
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
| 451 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg9 :Intra_mbAddrB_reg9;
|
| 452 |
|
|
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg5 :Intra_mbAddrB_reg5;
|
| 453 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg12:Intra_mbAddrB_reg12;
|
| 454 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg2 :Intra_mbAddrB_reg2;
|
| 455 |
|
|
plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b10;
|
| 456 |
|
|
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0;
|
| 457 |
|
|
end
|
| 458 |
|
|
9,4 : // x4,x6
|
| 459 |
|
|
begin
|
| 460 |
|
|
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
| 461 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg11:Intra_mbAddrB_reg11;
|
| 462 |
|
|
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg3 :Intra_mbAddrB_reg3;
|
| 463 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg13:Intra_mbAddrB_reg13;
|
| 464 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg1 :Intra_mbAddrB_reg1;
|
| 465 |
|
|
plane_HV_shifter1_len <= 2'b10; plane_HV_shifter2_len <= 2'b10;
|
| 466 |
|
|
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1;
|
| 467 |
|
|
end
|
| 468 |
|
|
8,3 : // x8,x7
|
| 469 |
|
|
begin
|
| 470 |
|
|
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b1;
|
| 471 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg15:Intra_mbAddrB_reg15;
|
| 472 |
|
|
plane_HV_A2 <= Intra_mbAddrD_window;
|
| 473 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg14:Intra_mbAddrB_reg14;
|
| 474 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg0 :Intra_mbAddrB_reg0;
|
| 475 |
|
|
plane_HV_shifter1_len <= 2'b11; plane_HV_shifter2_len <= 2'b11;
|
| 476 |
|
|
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0;
|
| 477 |
|
|
end
|
| 478 |
|
|
default:
|
| 479 |
|
|
begin
|
| 480 |
|
|
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
| 481 |
|
|
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
| 482 |
|
|
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
| 483 |
|
|
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
| 484 |
|
|
end
|
| 485 |
|
|
endcase
|
| 486 |
|
|
//Chroma Cb/Cr plane
|
| 487 |
|
|
else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)
|
| 488 |
|
|
case (blk4x4_intra_precompute_counter)
|
| 489 |
|
|
7,4: //x1,x3
|
| 490 |
|
|
begin
|
| 491 |
|
|
plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0;
|
| 492 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg4:Intra_mbAddrB_reg4;
|
| 493 |
|
|
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg2:Intra_mbAddrB_reg2;
|
| 494 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg6:Intra_mbAddrB_reg6;
|
| 495 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg0:Intra_mbAddrB_reg0;
|
| 496 |
|
|
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01;
|
| 497 |
|
|
plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0;
|
| 498 |
|
|
end
|
| 499 |
|
|
6,3: //x2,x4
|
| 500 |
|
|
begin
|
| 501 |
|
|
plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0;
|
| 502 |
|
|
plane_HV_A1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg5:Intra_mbAddrB_reg5;
|
| 503 |
|
|
plane_HV_A2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg1:Intra_mbAddrB_reg1;
|
| 504 |
|
|
plane_HV_B1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg7:Intra_mbAddrB_reg7;
|
| 505 |
|
|
plane_HV_B2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrD_window :Intra_mbAddrD_window;
|
| 506 |
|
|
plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b01;
|
| 507 |
|
|
plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1;
|
| 508 |
|
|
end
|
| 509 |
|
|
default:
|
| 510 |
|
|
begin
|
| 511 |
|
|
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
| 512 |
|
|
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
| 513 |
|
|
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
| 514 |
|
|
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
| 515 |
|
|
end
|
| 516 |
|
|
endcase
|
| 517 |
|
|
else
|
| 518 |
|
|
begin
|
| 519 |
|
|
plane_HV_prev_in <= 0; plane_HV_Is7 <= 0;
|
| 520 |
|
|
plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0;
|
| 521 |
|
|
plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0;
|
| 522 |
|
|
plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0;
|
| 523 |
|
|
end
|
| 524 |
|
|
|
| 525 |
|
|
wire Is_HV_latch;
|
| 526 |
|
|
assign Is_HV_latch = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter != 7 && blk4x4_intra_precompute_counter != 2 &&
|
| 527 |
|
|
blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0) || (
|
| 528 |
|
|
(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && (blk4x4_intra_precompute_counter != 5 &&
|
| 529 |
|
|
blk4x4_intra_precompute_counter != 2 && blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0)));
|
| 530 |
|
|
always @ (posedge clk)
|
| 531 |
|
|
if (reset_n == 1'b0)
|
| 532 |
|
|
plane_HV_out_reg <= 0;
|
| 533 |
|
|
else if (Is_HV_latch)
|
| 534 |
|
|
plane_HV_out_reg <= plane_HV_out;
|
| 535 |
|
|
|
| 536 |
|
|
// 2.2 precomputation for b,c
|
| 537 |
|
|
reg [14:0] plane_bc_in;
|
| 538 |
|
|
reg plane_bc_IsLuma;
|
| 539 |
|
|
wire [11:0] plane_bc;
|
| 540 |
|
|
plane_bc_precomputation plane_bc_precomputation (
|
| 541 |
|
|
.HV_in(plane_bc_in),
|
| 542 |
|
|
.IsLuma(plane_bc_IsLuma),
|
| 543 |
|
|
.bc_out(plane_bc)
|
| 544 |
|
|
);
|
| 545 |
|
|
always @ (mb_type_general[3:2] or Intra16x16_predmode or blk4x4_rec_counter or blk4x4_intra_precompute_counter or plane_HV_out_reg)
|
| 546 |
|
|
//Intra16x16 plane
|
| 547 |
|
|
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_rec_counter == 0)
|
| 548 |
|
|
case (blk4x4_intra_precompute_counter)
|
| 549 |
|
|
7,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b1; end
|
| 550 |
|
|
default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
| 551 |
|
|
endcase
|
| 552 |
|
|
//Chroma Cb,Cr plane
|
| 553 |
|
|
else if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20))
|
| 554 |
|
|
case (blk4x4_intra_precompute_counter)
|
| 555 |
|
|
5,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b0; end
|
| 556 |
|
|
default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
| 557 |
|
|
endcase
|
| 558 |
|
|
else
|
| 559 |
|
|
begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end
|
| 560 |
|
|
|
| 561 |
|
|
wire c_latch_ena;
|
| 562 |
|
|
assign c_latch_ena = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 7) ||
|
| 563 |
|
|
((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 5));
|
| 564 |
|
|
always @ (posedge clk)
|
| 565 |
|
|
if (reset_n == 0)
|
| 566 |
|
|
plane_c_reg <= 0;
|
| 567 |
|
|
else if (c_latch_ena)
|
| 568 |
|
|
plane_c_reg <= plane_bc;
|
| 569 |
|
|
// 2.3 precomputation for a,and latch a & b at the same time at cycle 2
|
| 570 |
|
|
reg [7:0] plane_a_pix_in1,plane_a_pix_in2;
|
| 571 |
|
|
wire [13:0] plane_a;
|
| 572 |
|
|
reg [13:0] plane_a_reg;
|
| 573 |
|
|
|
| 574 |
|
|
plane_a_precomputation plane_a_precomputation(
|
| 575 |
|
|
.pix_in1(plane_a_pix_in1),
|
| 576 |
|
|
.pix_in2(plane_a_pix_in2),
|
| 577 |
|
|
.a_out(plane_a)
|
| 578 |
|
|
);
|
| 579 |
|
|
always @ (blk4x4_rec_counter or blk4x4_intra_precompute_counter or Intra_mbAddrA_reg15
|
| 580 |
|
|
or Intra_mbAddrB_reg15 or Intra_mbAddrA_reg7 or Intra_mbAddrB_reg7)
|
| 581 |
|
|
//Intra16x16
|
| 582 |
|
|
if (blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 2)
|
| 583 |
|
|
begin
|
| 584 |
|
|
plane_a_pix_in1 <= Intra_mbAddrA_reg15;
|
| 585 |
|
|
plane_a_pix_in2 <= Intra_mbAddrB_reg15;
|
| 586 |
|
|
end
|
| 587 |
|
|
//Chroma
|
| 588 |
|
|
else if((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 2)
|
| 589 |
|
|
begin
|
| 590 |
|
|
plane_a_pix_in1 <= Intra_mbAddrA_reg7;
|
| 591 |
|
|
plane_a_pix_in2 <= Intra_mbAddrB_reg7;
|
| 592 |
|
|
end
|
| 593 |
|
|
else
|
| 594 |
|
|
begin
|
| 595 |
|
|
plane_a_pix_in1 <= 0;
|
| 596 |
|
|
plane_a_pix_in2 <= 0;
|
| 597 |
|
|
end
|
| 598 |
|
|
|
| 599 |
|
|
wire ab_latch_ena;
|
| 600 |
|
|
assign ab_latch_ena = (blk4x4_intra_precompute_counter == 2);
|
| 601 |
|
|
always @ (posedge clk)
|
| 602 |
|
|
if (reset_n == 1'b0)
|
| 603 |
|
|
begin
|
| 604 |
|
|
plane_a_reg <= 0;
|
| 605 |
|
|
plane_b_reg <= 0;
|
| 606 |
|
|
end
|
| 607 |
|
|
else if (ab_latch_ena)
|
| 608 |
|
|
begin
|
| 609 |
|
|
plane_a_reg <= plane_a;
|
| 610 |
|
|
plane_b_reg <= plane_bc;
|
| 611 |
|
|
end
|
| 612 |
|
|
// 2.4 precomputation for main seed @ blk4x4_intra_precompute_counter == 1
|
| 613 |
|
|
wire [13:0] main_seed_a;
|
| 614 |
|
|
wire [11:0] main_seed_b,main_seed_c;
|
| 615 |
|
|
wire main_seed_IsIntra16x16;
|
| 616 |
|
|
|
| 617 |
|
|
main_seed_precomputation main_seed_precomputation (
|
| 618 |
|
|
.a(main_seed_a),
|
| 619 |
|
|
.b(main_seed_b),
|
| 620 |
|
|
.c(main_seed_c),
|
| 621 |
|
|
.IsIntra16x16(main_seed_IsIntra16x16),
|
| 622 |
|
|
.main_seed(main_seed)
|
| 623 |
|
|
);
|
| 624 |
|
|
assign main_seed_a = (blk4x4_intra_precompute_counter == 1)? plane_a_reg:0;
|
| 625 |
|
|
assign main_seed_b = (blk4x4_intra_precompute_counter == 1)? plane_b_reg:0;
|
| 626 |
|
|
assign main_seed_c = (blk4x4_intra_precompute_counter == 1)? plane_c_reg:0;
|
| 627 |
|
|
assign main_seed_IsIntra16x16 = (blk4x4_intra_precompute_counter == 1)? ((blk4x4_rec_counter == 0)? 1'b1:1'b0):1'b0;
|
| 628 |
|
|
|
| 629 |
|
|
//----------------------------------------------------------------------------------------
|
| 630 |
|
|
//3.calculation: by Intra_pred_PE.v
|
| 631 |
|
|
//----------------------------------------------------------------------------------------
|
| 632 |
|
|
|
| 633 |
|
|
endmodule
|
| 634 |
|
|
|
| 635 |
|
|
module plane_a_precomputation (pix_in1,pix_in2,a_out);
|
| 636 |
|
|
input [7:0] pix_in1,pix_in2;
|
| 637 |
|
|
output [13:0] a_out;
|
| 638 |
|
|
|
| 639 |
|
|
wire [8:0] sum;
|
| 640 |
|
|
assign sum = pix_in1 + pix_in2;
|
| 641 |
|
|
assign a_out = {1'b0,sum,4'b0};
|
| 642 |
|
|
endmodule
|
| 643 |
|
|
|
| 644 |
|
|
module plane_bc_precomputation (HV_in,IsLuma,bc_out);
|
| 645 |
|
|
input [14:0] HV_in;
|
| 646 |
|
|
input IsLuma;
|
| 647 |
|
|
output [11:0] bc_out;
|
| 648 |
|
|
|
| 649 |
|
|
wire [16:0] multiply_4or16;
|
| 650 |
|
|
wire [16:0] product;
|
| 651 |
|
|
wire [5:0] addend;
|
| 652 |
|
|
wire [16:0] sum;
|
| 653 |
|
|
|
| 654 |
|
|
assign multiply_4or16 = (IsLuma)? {HV_in,2'b0}:{HV_in[12:0],4'b0};
|
| 655 |
|
|
assign product = multiply_4or16 + {{2{HV_in[14]}},HV_in};
|
| 656 |
|
|
assign addend = (IsLuma)? 6'b100000:6'b010000; //32 for luma,16 for chroma
|
| 657 |
|
|
assign sum = product + addend;
|
| 658 |
|
|
assign bc_out = (IsLuma)? {sum[16],sum[16:6]}:sum[16:5];
|
| 659 |
|
|
|
| 660 |
|
|
endmodule
|
| 661 |
|
|
|
| 662 |
|
|
module plane_HV_precomputation (prev_in,A1,A2,B1,B2,shifter1_len,shifter2_len,mux1_sel,mux2_sel,Is7,HV_out);
|
| 663 |
|
|
input [14:0] prev_in;
|
| 664 |
|
|
input [7:0] A1,A2,B1,B2;
|
| 665 |
|
|
input [1:0] shifter1_len,shifter2_len;
|
| 666 |
|
|
input mux1_sel,mux2_sel;
|
| 667 |
|
|
input Is7;
|
| 668 |
|
|
output [14:0] HV_out;
|
| 669 |
|
|
|
| 670 |
|
|
wire [7:0] neg_A2;
|
| 671 |
|
|
wire signed [8:0] A1_minus_A2;
|
| 672 |
|
|
wire signed [11:0] shifter1_out;
|
| 673 |
|
|
wire [11:0] mux1_out;
|
| 674 |
|
|
wire [14:0] adder1_out;
|
| 675 |
|
|
wire [7:0] neg_B2;
|
| 676 |
|
|
wire signed [8:0] B1_minus_B2;
|
| 677 |
|
|
wire signed [11:0] shifter2_out;
|
| 678 |
|
|
wire [9:0] mux2_out;
|
| 679 |
|
|
wire [9:0] neg_mux2_out;
|
| 680 |
|
|
wire [11:0] adder2_out;
|
| 681 |
|
|
//Left part,multiply by 1,2,4,8
|
| 682 |
|
|
assign neg_A2 = ~A2;
|
| 683 |
|
|
assign A1_minus_A2 = {1'b0,A1} + {1'b1,neg_A2} + 1;
|
| 684 |
|
|
assign shifter1_out = A1_minus_A2 <<< shifter1_len;
|
| 685 |
|
|
assign mux1_out = (mux1_sel == 1'b0)? {{3{A1_minus_A2[8]}},A1_minus_A2}:shifter1_out;
|
| 686 |
|
|
assign adder1_out = prev_in + {{3{mux1_out[11]}},mux1_out};
|
| 687 |
|
|
//Right part,multiply by 3,5,6,7
|
| 688 |
|
|
assign neg_B2 = ~B2;
|
| 689 |
|
|
assign B1_minus_B2 = {1'b0,B1} + {1'b1,neg_B2} + 1;
|
| 690 |
|
|
assign shifter2_out = B1_minus_B2 <<< shifter2_len;
|
| 691 |
|
|
assign mux2_out = (mux2_sel == 1'b0)? {B1_minus_B2[8],B1_minus_B2}:{B1_minus_B2,1'b0};
|
| 692 |
|
|
assign neg_mux2_out = (Is7 == 1'b1)? (~mux2_out + 1):mux2_out;
|
| 693 |
|
|
assign adder2_out = shifter2_out + {{2{neg_mux2_out[9]}},neg_mux2_out};
|
| 694 |
|
|
assign HV_out = adder1_out + {{3{adder2_out[11]}},adder2_out};
|
| 695 |
|
|
endmodule
|
| 696 |
|
|
|
| 697 |
|
|
module main_seed_precomputation (a,b,c,IsIntra16x16,main_seed);
|
| 698 |
|
|
input [13:0] a;
|
| 699 |
|
|
input [11:0] b,c;
|
| 700 |
|
|
input IsIntra16x16;
|
| 701 |
|
|
output [15:0] main_seed;
|
| 702 |
|
|
|
| 703 |
|
|
wire [14:0] b_x8_or_x4;
|
| 704 |
|
|
wire [14:0] c_x8_or_x4;
|
| 705 |
|
|
wire [11:0] neg_b;
|
| 706 |
|
|
wire [14:0] b_x7_or_x3;
|
| 707 |
|
|
wire [15:0] neg_b_x7_or_x3;
|
| 708 |
|
|
wire [15:0] neg_c_x8_or_x4;
|
| 709 |
|
|
|
| 710 |
|
|
assign b_x8_or_x4 = (IsIntra16x16)? {b[11:0],3'b0}:{b[11],b[11:0],2'b0};
|
| 711 |
|
|
assign c_x8_or_x4 = (IsIntra16x16)? {c[11:0],3'b0}:{c[11],c[11:0],2'b0};
|
| 712 |
|
|
assign neg_b = ~ b;
|
| 713 |
|
|
assign b_x7_or_x3 = b_x8_or_x4 + {{3{neg_b[11]}},neg_b} + 1;
|
| 714 |
|
|
assign neg_b_x7_or_x3 = {~b_x7_or_x3[14],~b_x7_or_x3} + 1;
|
| 715 |
|
|
assign neg_c_x8_or_x4 = {~c_x8_or_x4[14],~c_x8_or_x4} + 1;
|
| 716 |
|
|
assign main_seed = {a[13],a[13],a} + (neg_c_x8_or_x4 + neg_b_x7_or_x3);
|
| 717 |
|
|
endmodule
|
| 718 |
|
|
|
| 719 |
|
|
|
| 720 |
|
|
|
| 721 |
|
|
|
| 722 |
|
|
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
|
| 740 |
|
|
|
| 741 |
|
|
|
| 742 |
|
|
|
| 743 |
|
|
|
