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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : Intra_pred_reg_ctrl.v
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// Generated : Sep 25, 2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Prepare the appropriate registers for PE0 ~ PE3
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,
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gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
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mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter,
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blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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Intra_mbAddrB_RAM_dout,sum_right_column_reg,
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blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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main_seed,PE0_sum_out,PE3_sum_out,
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Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
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Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
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Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
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Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
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Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
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Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
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Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
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Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
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Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
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Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
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Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window,
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seed);
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input reset_n;
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input gclk_intra_mbAddrA_luma;
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input gclk_intra_mbAddrA_Cb;
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input gclk_intra_mbAddrA_Cr;
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input gclk_intra_mbAddrB;
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input gclk_intra_mbAddrC_luma;
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input gclk_intra_mbAddrD;
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input gclk_seed;
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input mbAddrA_availability;
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input mbAddrC_availability;
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input [4:0] blk4x4_rec_counter;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_intra_preload_counter;
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input [3:0] blk4x4_intra_precompute_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [3:0] mb_type_general;
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input [3:0] Intra4x4_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra_chroma_predmode;
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input [31:0] Intra_mbAddrB_RAM_dout;
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input [23:0] sum_right_column_reg;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [15:0] main_seed;
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input [15:0] PE0_sum_out,PE3_sum_out;
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output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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output [7:0] Intra_mbAddrD_window;
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output [15:0] seed;
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reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3;
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reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7;
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reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11;
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reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15;
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reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3;
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reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7;
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reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3;
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reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7;
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reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3;
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reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2;
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reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4;
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reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg;
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reg [7:0] Intra_mbAddrD_window;
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reg [15:0] seed_0,seed_1,seed_2,seed_3;
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reg [15:0] seed;
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//---------------------------------------------------------------------
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//Intra_mbAddrA_luma_reg0 ~ 15
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//Intra_mbAddrA_Cb_reg0 ~ 7
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//Intra_mbAddrA_Cr_reg0 ~ 7
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//---------------------------------------------------------------------
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always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n)
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if (reset_n == 1'b0)
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begin
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Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0;
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Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0;
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Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0;
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Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0;
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Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0;
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Intra_mbAddrA_luma_reg15 <= 0;
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end
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else
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case (blk4x4_rec_counter)
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0,1,4,5:
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begin
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Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out;
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end
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2,3,6,7:
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begin
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Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out;
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end
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8,9,12,13:
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begin
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Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out;
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end
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10,11,14,15:
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begin
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Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out;
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end
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endcase
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always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n)
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if (reset_n == 1'b0)
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begin
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Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0;
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Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0;
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Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0;
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end
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else if (blk4x4_rec_counter == 17)
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begin
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Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out;
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end
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else
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begin
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Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out;
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end
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always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n)
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if (reset_n == 1'b0)
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begin
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Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0;
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Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0;
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Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0;
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end
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else if (blk4x4_rec_counter == 21)
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begin
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Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out;
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end
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else
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begin
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Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8];
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| 200 |
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Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out;
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end
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//---------------------------------------------------------------------
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//Intra_mbAddrB_reg0 ~ 15
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//---------------------------------------------------------------------
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always @ (posedge gclk_intra_mbAddrB or negedge reset_n)
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if (reset_n == 1'b0)
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begin
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Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0;
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| 210 |
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Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0;
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| 211 |
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Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0;
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| 212 |
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Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0;
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Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0;
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Intra_mbAddrB_reg15 <= 0;
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end
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//Intra4x4
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else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
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begin
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// blk 0,1,4,5,load from RAM
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| 220 |
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if (blk4x4_intra_preload_counter == 3'b001)
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case (blk4x4_rec_counter)
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0:
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begin
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|
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 225 |
|
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 226 |
|
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 227 |
|
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 228 |
|
|
end
|
| 229 |
|
|
1:
|
| 230 |
|
|
begin
|
| 231 |
|
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 232 |
|
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 233 |
|
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 234 |
|
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 235 |
|
|
end
|
| 236 |
|
|
4:
|
| 237 |
|
|
begin
|
| 238 |
|
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 239 |
|
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 240 |
|
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 241 |
|
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 242 |
|
|
end
|
| 243 |
|
|
5:
|
| 244 |
|
|
begin
|
| 245 |
|
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 246 |
|
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 247 |
|
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 248 |
|
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 249 |
|
|
end
|
| 250 |
|
|
endcase
|
| 251 |
|
|
//other blocks,from blk4x4_sum output
|
| 252 |
|
|
else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 ||
|
| 253 |
|
|
blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3)
|
| 254 |
|
|
case (blk4x4_rec_counter)
|
| 255 |
|
|
0,2,8:
|
| 256 |
|
|
begin
|
| 257 |
|
|
Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out;
|
| 258 |
|
|
Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out;
|
| 259 |
|
|
Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out;
|
| 260 |
|
|
Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out;
|
| 261 |
|
|
end
|
| 262 |
|
|
1,3,9:
|
| 263 |
|
|
begin
|
| 264 |
|
|
Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out;
|
| 265 |
|
|
Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out;
|
| 266 |
|
|
Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out;
|
| 267 |
|
|
Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out;
|
| 268 |
|
|
end
|
| 269 |
|
|
4,6,12:
|
| 270 |
|
|
begin
|
| 271 |
|
|
Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out;
|
| 272 |
|
|
Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out;
|
| 273 |
|
|
Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out;
|
| 274 |
|
|
Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out;
|
| 275 |
|
|
end
|
| 276 |
|
|
5,7,13:
|
| 277 |
|
|
begin
|
| 278 |
|
|
Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out;
|
| 279 |
|
|
Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out;
|
| 280 |
|
|
Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out;
|
| 281 |
|
|
Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out;
|
| 282 |
|
|
end
|
| 283 |
|
|
endcase
|
| 284 |
|
|
end
|
| 285 |
|
|
//Intra16x16
|
| 286 |
|
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
| 287 |
|
|
case (blk4x4_intra_preload_counter)
|
| 288 |
|
|
3'b100:
|
| 289 |
|
|
begin
|
| 290 |
|
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 291 |
|
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 292 |
|
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 293 |
|
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 294 |
|
|
end
|
| 295 |
|
|
3'b011:
|
| 296 |
|
|
begin
|
| 297 |
|
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 298 |
|
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 299 |
|
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 300 |
|
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 301 |
|
|
end
|
| 302 |
|
|
3'b010:
|
| 303 |
|
|
begin
|
| 304 |
|
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 305 |
|
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 306 |
|
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 307 |
|
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 308 |
|
|
end
|
| 309 |
|
|
3'b001:
|
| 310 |
|
|
begin
|
| 311 |
|
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 312 |
|
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 313 |
|
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 314 |
|
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 315 |
|
|
end
|
| 316 |
|
|
endcase
|
| 317 |
|
|
//Chroma
|
| 318 |
|
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
| 319 |
|
|
begin
|
| 320 |
|
|
if (blk4x4_intra_preload_counter == 3'b010)
|
| 321 |
|
|
begin
|
| 322 |
|
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 323 |
|
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 324 |
|
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 325 |
|
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 326 |
|
|
end
|
| 327 |
|
|
else if (blk4x4_intra_preload_counter == 3'b001)
|
| 328 |
|
|
begin
|
| 329 |
|
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 330 |
|
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 331 |
|
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 332 |
|
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 333 |
|
|
end
|
| 334 |
|
|
end
|
| 335 |
|
|
//--------------------------------------------------------
|
| 336 |
|
|
//Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with
|
| 337 |
|
|
// blkIdx = 0/1/4/5
|
| 338 |
|
|
//--------------------------------------------------------
|
| 339 |
|
|
|
| 340 |
|
|
always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n)
|
| 341 |
|
|
if (reset_n == 1'b0)
|
| 342 |
|
|
begin
|
| 343 |
|
|
Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0;
|
| 344 |
|
|
Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0;
|
| 345 |
|
|
end
|
| 346 |
|
|
else
|
| 347 |
|
|
begin
|
| 348 |
|
|
Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
| 349 |
|
|
Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
| 350 |
|
|
Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
| 351 |
|
|
Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 352 |
|
|
end
|
| 353 |
|
|
//--------------------------------------------------------
|
| 354 |
|
|
//Intra_mbAddrD_reg0 ~ 5
|
| 355 |
|
|
//Intra_mbAddrD_LeftMB_reg
|
| 356 |
|
|
//--------------------------------------------------------
|
| 357 |
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
| 358 |
|
|
if (reset_n == 1'b0)
|
| 359 |
|
|
Intra_mbAddrD_LeftMB_luma_reg <= 0;
|
| 360 |
|
|
else if (blk4x4_rec_counter == 15)
|
| 361 |
|
|
Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
| 362 |
|
|
else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4
|
| 363 |
|
|
case (blk4x4_rec_counter)
|
| 364 |
|
|
0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3;
|
| 365 |
|
|
2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7;
|
| 366 |
|
|
8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11;
|
| 367 |
|
|
endcase
|
| 368 |
|
|
|
| 369 |
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
| 370 |
|
|
if (reset_n == 1'b0)
|
| 371 |
|
|
Intra_mbAddrD_LeftMB_Cb_reg <= 0;
|
| 372 |
|
|
else if (blk4x4_rec_counter == 19)
|
| 373 |
|
|
Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
| 374 |
|
|
|
| 375 |
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
| 376 |
|
|
if (reset_n == 1'b0)
|
| 377 |
|
|
Intra_mbAddrD_LeftMB_Cr_reg <= 0;
|
| 378 |
|
|
else if (blk4x4_rec_counter == 23)
|
| 379 |
|
|
Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
| 380 |
|
|
|
| 381 |
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
| 382 |
|
|
if (reset_n == 1'b0)
|
| 383 |
|
|
begin
|
| 384 |
|
|
Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0;
|
| 385 |
|
|
Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0;
|
| 386 |
|
|
end
|
| 387 |
|
|
else if (mb_type_general[3:2] == 2'b11)
|
| 388 |
|
|
begin
|
| 389 |
|
|
//load from Intra_mbAddrB_RAM for blk 1/4/5
|
| 390 |
|
|
if (blk4x4_intra_preload_counter == 3'b010)
|
| 391 |
|
|
case (blk4x4_rec_counter)
|
| 392 |
|
|
1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 393 |
|
|
4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 394 |
|
|
5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24];
|
| 395 |
|
|
endcase
|
| 396 |
|
|
//update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4
|
| 397 |
|
|
//After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7
|
| 398 |
|
|
//After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13
|
| 399 |
|
|
//After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15
|
| 400 |
|
|
else
|
| 401 |
|
|
case (blk4x4_rec_counter)
|
| 402 |
|
|
0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out;
|
| 403 |
|
|
1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out;
|
| 404 |
|
|
2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out;
|
| 405 |
|
|
3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out;
|
| 406 |
|
|
4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out;
|
| 407 |
|
|
endcase
|
| 408 |
|
|
end
|
| 409 |
|
|
//---------------------------
|
| 410 |
|
|
//sliding window output
|
| 411 |
|
|
//---------------------------
|
| 412 |
|
|
//Intra_mbAddrA_reg0 ~ 15
|
| 413 |
|
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or
|
| 414 |
|
|
blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode
|
| 415 |
|
|
or mbAddrA_availability
|
| 416 |
|
|
|
| 417 |
|
|
or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2
|
| 418 |
|
|
or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5
|
| 419 |
|
|
or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8
|
| 420 |
|
|
or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11
|
| 421 |
|
|
or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14
|
| 422 |
|
|
or Intra_mbAddrA_luma_reg15
|
| 423 |
|
|
|
| 424 |
|
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2
|
| 425 |
|
|
or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5
|
| 426 |
|
|
or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
| 427 |
|
|
|
| 428 |
|
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2
|
| 429 |
|
|
or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5
|
| 430 |
|
|
or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
| 431 |
|
|
if (mb_type_general[3] == 1'b1)
|
| 432 |
|
|
begin
|
| 433 |
|
|
//Intra4x4
|
| 434 |
|
|
//Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane
|
| 435 |
|
|
if (blk4x4_rec_counter < 16 &&
|
| 436 |
|
|
(mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && (
|
| 437 |
|
|
(Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
| 438 |
|
|
(Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
| 439 |
|
|
(Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0)))))
|
| 440 |
|
|
begin
|
| 441 |
|
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0;
|
| 442 |
|
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1;
|
| 443 |
|
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2;
|
| 444 |
|
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3;
|
| 445 |
|
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4;
|
| 446 |
|
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5;
|
| 447 |
|
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6;
|
| 448 |
|
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7;
|
| 449 |
|
|
Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8;
|
| 450 |
|
|
Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9;
|
| 451 |
|
|
Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10;
|
| 452 |
|
|
Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11;
|
| 453 |
|
|
Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12;
|
| 454 |
|
|
Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13;
|
| 455 |
|
|
Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14;
|
| 456 |
|
|
Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15;
|
| 457 |
|
|
end
|
| 458 |
|
|
//Chroma Cb
|
| 459 |
|
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && (
|
| 460 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
| 461 |
|
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
| 462 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
| 463 |
|
|
begin
|
| 464 |
|
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0;
|
| 465 |
|
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1;
|
| 466 |
|
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2;
|
| 467 |
|
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3;
|
| 468 |
|
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4;
|
| 469 |
|
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5;
|
| 470 |
|
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6;
|
| 471 |
|
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7;
|
| 472 |
|
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
| 473 |
|
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
| 474 |
|
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
| 475 |
|
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
| 476 |
|
|
end
|
| 477 |
|
|
//Chroma Cr
|
| 478 |
|
|
else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && (
|
| 479 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
| 480 |
|
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
| 481 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
| 482 |
|
|
begin
|
| 483 |
|
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0;
|
| 484 |
|
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1;
|
| 485 |
|
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2;
|
| 486 |
|
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3;
|
| 487 |
|
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4;
|
| 488 |
|
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5;
|
| 489 |
|
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6;
|
| 490 |
|
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7;
|
| 491 |
|
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
| 492 |
|
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
| 493 |
|
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
| 494 |
|
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
| 495 |
|
|
end
|
| 496 |
|
|
else
|
| 497 |
|
|
begin
|
| 498 |
|
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
| 499 |
|
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
| 500 |
|
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
| 501 |
|
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
| 502 |
|
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
| 503 |
|
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
| 504 |
|
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
| 505 |
|
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
| 506 |
|
|
end
|
| 507 |
|
|
end
|
| 508 |
|
|
else
|
| 509 |
|
|
begin
|
| 510 |
|
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
| 511 |
|
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
| 512 |
|
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
| 513 |
|
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
| 514 |
|
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
| 515 |
|
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
| 516 |
|
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
| 517 |
|
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
| 518 |
|
|
end
|
| 519 |
|
|
//Intra_mbAddrA_window0 ~ 3
|
| 520 |
|
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
| 521 |
|
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability
|
| 522 |
|
|
|
| 523 |
|
|
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
| 524 |
|
|
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
| 525 |
|
|
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
| 526 |
|
|
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
| 527 |
|
|
|
| 528 |
|
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3
|
| 529 |
|
|
or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
| 530 |
|
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3
|
| 531 |
|
|
or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
| 532 |
|
|
if (mb_type_general[3] == 1'b1)
|
| 533 |
|
|
begin
|
| 534 |
|
|
//Intra4x4 && Intra16x16_horizontal
|
| 535 |
|
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
| 536 |
|
|
(mb_type_general[2] == 1'b1 || (
|
| 537 |
|
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal))))
|
| 538 |
|
|
case (blk4x4_rec_counter)
|
| 539 |
|
|
0,1,4,5:
|
| 540 |
|
|
begin
|
| 541 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1;
|
| 542 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3;
|
| 543 |
|
|
end
|
| 544 |
|
|
2,3,6,7:
|
| 545 |
|
|
begin
|
| 546 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5;
|
| 547 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7;
|
| 548 |
|
|
end
|
| 549 |
|
|
8,9,12,13:
|
| 550 |
|
|
begin
|
| 551 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9;
|
| 552 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11;
|
| 553 |
|
|
end
|
| 554 |
|
|
10,11,14,15:
|
| 555 |
|
|
begin
|
| 556 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13;
|
| 557 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15;
|
| 558 |
|
|
end
|
| 559 |
|
|
default:
|
| 560 |
|
|
begin
|
| 561 |
|
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
| 562 |
|
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
| 563 |
|
|
end
|
| 564 |
|
|
endcase
|
| 565 |
|
|
//Chroma Cb/Cr Horizontal & DC
|
| 566 |
|
|
else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 &&
|
| 567 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability)))
|
| 568 |
|
|
case (blk4x4_rec_counter)
|
| 569 |
|
|
16,17:
|
| 570 |
|
|
begin
|
| 571 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0;
|
| 572 |
|
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1;
|
| 573 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2;
|
| 574 |
|
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3;
|
| 575 |
|
|
end
|
| 576 |
|
|
18,19:
|
| 577 |
|
|
begin
|
| 578 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4;
|
| 579 |
|
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5;
|
| 580 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6;
|
| 581 |
|
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7;
|
| 582 |
|
|
end
|
| 583 |
|
|
20,21:
|
| 584 |
|
|
begin
|
| 585 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0;
|
| 586 |
|
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1;
|
| 587 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2;
|
| 588 |
|
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3;
|
| 589 |
|
|
end
|
| 590 |
|
|
22,23:
|
| 591 |
|
|
begin
|
| 592 |
|
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4;
|
| 593 |
|
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5;
|
| 594 |
|
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6;
|
| 595 |
|
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7;
|
| 596 |
|
|
end
|
| 597 |
|
|
default:
|
| 598 |
|
|
begin
|
| 599 |
|
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
| 600 |
|
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
| 601 |
|
|
end
|
| 602 |
|
|
endcase
|
| 603 |
|
|
else
|
| 604 |
|
|
begin
|
| 605 |
|
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
| 606 |
|
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
| 607 |
|
|
end
|
| 608 |
|
|
end
|
| 609 |
|
|
else
|
| 610 |
|
|
begin
|
| 611 |
|
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
| 612 |
|
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
| 613 |
|
|
end
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
//Intra_mbAddrB_window0 ~ 3
|
| 617 |
|
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
| 618 |
|
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter
|
| 619 |
|
|
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2
|
| 620 |
|
|
or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5
|
| 621 |
|
|
or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8
|
| 622 |
|
|
or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
| 623 |
|
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14
|
| 624 |
|
|
or Intra_mbAddrB_reg15)
|
| 625 |
|
|
if (mb_type_general[3] == 1'b1)
|
| 626 |
|
|
begin
|
| 627 |
|
|
//Intra4x4 && Intra16x16_Vertical
|
| 628 |
|
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
| 629 |
|
|
(mb_type_general[2] == 1'b1 || (
|
| 630 |
|
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical))))
|
| 631 |
|
|
case (blk4x4_rec_counter)
|
| 632 |
|
|
0,2,8,10:
|
| 633 |
|
|
begin
|
| 634 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
| 635 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
| 636 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
| 637 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
| 638 |
|
|
end
|
| 639 |
|
|
1,3,9,11:
|
| 640 |
|
|
begin
|
| 641 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
| 642 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
| 643 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
| 644 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
| 645 |
|
|
end
|
| 646 |
|
|
4,6,12,14:
|
| 647 |
|
|
begin
|
| 648 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8;
|
| 649 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9;
|
| 650 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10;
|
| 651 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11;
|
| 652 |
|
|
end
|
| 653 |
|
|
5,7,13,15:
|
| 654 |
|
|
begin
|
| 655 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12;
|
| 656 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13;
|
| 657 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14;
|
| 658 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15;
|
| 659 |
|
|
end
|
| 660 |
|
|
default:
|
| 661 |
|
|
begin
|
| 662 |
|
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
| 663 |
|
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
| 664 |
|
|
end
|
| 665 |
|
|
endcase
|
| 666 |
|
|
//Chroma Cb/Cr Vertical and DC
|
| 667 |
|
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 &&
|
| 668 |
|
|
(Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0)
|
| 669 |
|
|
case (blk4x4_rec_counter)
|
| 670 |
|
|
16,18,20,22:
|
| 671 |
|
|
begin
|
| 672 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
| 673 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
| 674 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
| 675 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
| 676 |
|
|
end
|
| 677 |
|
|
17,19,21,23:
|
| 678 |
|
|
begin
|
| 679 |
|
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
| 680 |
|
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
| 681 |
|
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
| 682 |
|
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
| 683 |
|
|
end
|
| 684 |
|
|
default:
|
| 685 |
|
|
begin
|
| 686 |
|
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
| 687 |
|
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
| 688 |
|
|
end
|
| 689 |
|
|
endcase
|
| 690 |
|
|
else
|
| 691 |
|
|
begin
|
| 692 |
|
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
| 693 |
|
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
| 694 |
|
|
end
|
| 695 |
|
|
end
|
| 696 |
|
|
else
|
| 697 |
|
|
begin
|
| 698 |
|
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
| 699 |
|
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
| 700 |
|
|
end
|
| 701 |
|
|
//Intra_mbAddrC_window0 ~ 3
|
| 702 |
|
|
always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode
|
| 703 |
|
|
or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3
|
| 704 |
|
|
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
| 705 |
|
|
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
| 706 |
|
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
| 707 |
|
|
or mbAddrC_availability or Intra_mbAddrB_window3)
|
| 708 |
|
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && (
|
| 709 |
|
|
Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16)
|
| 710 |
|
|
case (blk4x4_rec_counter)
|
| 711 |
|
|
0,1,4:
|
| 712 |
|
|
begin
|
| 713 |
|
|
Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0;
|
| 714 |
|
|
Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1;
|
| 715 |
|
|
Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2;
|
| 716 |
|
|
Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3;
|
| 717 |
|
|
end
|
| 718 |
|
|
5:
|
| 719 |
|
|
begin
|
| 720 |
|
|
Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15;
|
| 721 |
|
|
Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15;
|
| 722 |
|
|
Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15;
|
| 723 |
|
|
Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15;
|
| 724 |
|
|
end
|
| 725 |
|
|
2,8,10:
|
| 726 |
|
|
begin
|
| 727 |
|
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4;
|
| 728 |
|
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5;
|
| 729 |
|
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6;
|
| 730 |
|
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7;
|
| 731 |
|
|
end
|
| 732 |
|
|
9:
|
| 733 |
|
|
begin
|
| 734 |
|
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8;
|
| 735 |
|
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9;
|
| 736 |
|
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10;
|
| 737 |
|
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11;
|
| 738 |
|
|
end
|
| 739 |
|
|
6,12,14:
|
| 740 |
|
|
begin
|
| 741 |
|
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12;
|
| 742 |
|
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13;
|
| 743 |
|
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14;
|
| 744 |
|
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15;
|
| 745 |
|
|
end
|
| 746 |
|
|
3,11,7,13,15:
|
| 747 |
|
|
begin
|
| 748 |
|
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_window3;
|
| 749 |
|
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_window3;
|
| 750 |
|
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_window3;
|
| 751 |
|
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_window3;
|
| 752 |
|
|
end
|
| 753 |
|
|
default:
|
| 754 |
|
|
begin
|
| 755 |
|
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
| 756 |
|
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
| 757 |
|
|
end
|
| 758 |
|
|
endcase
|
| 759 |
|
|
else
|
| 760 |
|
|
begin
|
| 761 |
|
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
| 762 |
|
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
| 763 |
|
|
end
|
| 764 |
|
|
|
| 765 |
|
|
//Intra_mbAddrD_window
|
| 766 |
|
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter
|
| 767 |
|
|
or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter
|
| 768 |
|
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
| 769 |
|
|
or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2
|
| 770 |
|
|
or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4
|
| 771 |
|
|
or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg)
|
| 772 |
|
|
//Intra
|
| 773 |
|
|
if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0))
|
| 774 |
|
|
begin
|
| 775 |
|
|
//Intra luma
|
| 776 |
|
|
if (blk4x4_rec_counter[4] == 1'b0)
|
| 777 |
|
|
begin
|
| 778 |
|
|
//Intra4x4 luma
|
| 779 |
|
|
if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right ||
|
| 780 |
|
|
Intra4x4_predmode == `Intra4x4_Vertical_Right ||
|
| 781 |
|
|
Intra4x4_predmode == `Intra4x4_Horizontal_Down))
|
| 782 |
|
|
case (blk4x4_rec_counter[3:0])
|
| 783 |
|
|
0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg;
|
| 784 |
|
|
3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0;
|
| 785 |
|
|
1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1;
|
| 786 |
|
|
9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2;
|
| 787 |
|
|
12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3;
|
| 788 |
|
|
4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4;
|
| 789 |
|
|
endcase
|
| 790 |
|
|
//Intra16x16
|
| 791 |
|
|
else
|
| 792 |
|
|
Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0;
|
| 793 |
|
|
end
|
| 794 |
|
|
//Intra chroma
|
| 795 |
|
|
else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane)
|
| 796 |
|
|
Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg;
|
| 797 |
|
|
else
|
| 798 |
|
|
Intra_mbAddrD_window <= 0;
|
| 799 |
|
|
end
|
| 800 |
|
|
//Inter
|
| 801 |
|
|
else
|
| 802 |
|
|
Intra_mbAddrD_window <= 0;
|
| 803 |
|
|
|
| 804 |
|
|
//seed
|
| 805 |
|
|
always @ (posedge gclk_seed or negedge reset_n)
|
| 806 |
|
|
if (reset_n == 1'b0)
|
| 807 |
|
|
begin
|
| 808 |
|
|
seed_0 <= 0; seed_1 <= 0; seed_2 <= 0;
|
| 809 |
|
|
end
|
| 810 |
|
|
else if (blk4x4_intra_precompute_counter == 1)
|
| 811 |
|
|
seed_0 <= main_seed;
|
| 812 |
|
|
else
|
| 813 |
|
|
case (blk4x4_rec_counter)
|
| 814 |
|
|
0,2,8,16,20 :seed_0 <= PE3_sum_out;
|
| 815 |
|
|
1,9 :seed_1 <= PE0_sum_out;
|
| 816 |
|
|
3,11 :seed_2 <= PE0_sum_out;
|
| 817 |
|
|
endcase
|
| 818 |
|
|
|
| 819 |
|
|
always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode
|
| 820 |
|
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2)
|
| 821 |
|
|
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16)
|
| 822 |
|
|
case (blk4x4_rec_counter)
|
| 823 |
|
|
0,2,8,10:seed <= seed_0;
|
| 824 |
|
|
4,12 :seed <= seed_1;
|
| 825 |
|
|
6,14 :seed <= seed_2;
|
| 826 |
|
|
default :seed <= 0;
|
| 827 |
|
|
endcase
|
| 828 |
|
|
else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15)
|
| 829 |
|
|
if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22
|
| 830 |
|
|
seed <= seed_0;
|
| 831 |
|
|
else
|
| 832 |
|
|
seed <= 0;
|
| 833 |
|
|
else
|
| 834 |
|
|
seed <= 0;
|
| 835 |
|
|
|
| 836 |
|
|
endmodule
|
| 837 |
|
|
|
| 838 |
|
|
|
| 839 |
|
|
|
