OpenCores
URL https://opencores.org/ocsvn/nova/nova/trunk

Subversion Repositories nova

[/] [nova/] [trunk/] [src/] [bs_decoding.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 eexuke 
//--------------------------------------------------------------------------------------------------
2 
// Design    : nova
3 
// Author(s) : Ke Xu
4 
// Email           : eexuke@yahoo.com
5 
// File      : bs_decoding.v
6 
// Generated : Nov 17,2005
7 
// Copyright (C) 2008 Ke Xu
8 
//-------------------------------------------------------------------------------------------------
9 
// Description
10 
// Deblocking Filter Boundary Strength decoding
11 
//-------------------------------------------------------------------------------------------------
12 
 
13 
// synopsys translate_off
14 
`include "timescale.v"
15 
// synopsys translate_on
16 
`include "nova_defines.v"
17 
 
18 
module bs_decoding (clk,reset_n,gclk_bs_dec,gclk_end_of_MB_DEC,end_of_MB_DEC,end_of_one_blk4x4_sum,mb_num_h,mb_num_v,
19 
        disable_DF,blk4x4_rec_counter,CodedBlockPatternLuma,mb_type_general,slice_data_state,residual_state,
20 
        MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,end_of_one_residual_block,TotalCoeff,
21 
        curr_DC_IsZero,Is_skipMB_mv_calc,
22 
        mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout,
23 
        mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
24 
 
25 
        bs_dec_counter,end_of_BS_DEC,mv_mbAddrB_rd_for_DF,
26 
        bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3
27 
        );
28 
        input clk;
29 
        input reset_n;
30 
        input gclk_bs_dec;
31 
        input gclk_end_of_MB_DEC;
32 
        input end_of_MB_DEC;
33 
        input end_of_one_blk4x4_sum;
34 
        input [3:0] mb_num_h;
35 
        input [3:0] mb_num_v;
36 
        input [4:0] blk4x4_rec_counter;
37 
        input disable_DF;
38 
        input [3:0] CodedBlockPatternLuma;
39 
        input [3:0] mb_type_general;
40 
        input [3:0] slice_data_state;
41 
        input [3:0] residual_state;
42 
        input [1:0]  MBTypeGen_mbAddrA;
43 
        input [21:0] MBTypeGen_mbAddrB_reg;
44 
        input end_of_one_residual_block;
45 
        input [4:0] TotalCoeff;
46 
        input curr_DC_IsZero;
47 
        input Is_skipMB_mv_calc;
48 
        input [31:0] mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout;
49 
        input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
50 
        input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
51 
 
52 
        output [1:0] bs_dec_counter;
53 
        output end_of_BS_DEC;
54 
        output mv_mbAddrB_rd_for_DF;
55 
        output [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
56 
 
57 
        reg [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3;
58 
 
59 
        //-------------------------------------------
60 
        //mb_type_general needs to be latched for DF
61 
        //-------------------------------------------
62 
        reg [3:0] mb_type_general_DF;
63 
        always @ (posedge clk)
64 
                if (reset_n == 1'b0)
65 
                        mb_type_general_DF <= 4'b0;
66 
                else if (!disable_DF && end_of_one_blk4x4_sum && blk4x4_rec_counter == 5'd22)
67 
                        mb_type_general_DF <= mb_type_general;
68 
 
69 
        reg [1:0] MB_inter_size;
70 
        always @ (mb_type_general_DF)
71 
                if (mb_type_general_DF[3] == 1'b0)
72 
                        case (mb_type_general_DF[2:0])
73 
                                3'b000,3'b101:MB_inter_size <= `I16x16;
74 
                                3'b001           :MB_inter_size <= `I16x8;
75 
                                3'b010           :MB_inter_size <= `I8x16;
76 
                                default          :MB_inter_size <= `I8x8;
77 
                        endcase
78 
                else //Although it should be Intra,but we have no other choice
79 
                        MB_inter_size <= `I8x8;
80 
 
81 
        reg [1:0] MBTypeGen_mbAddrB;
82 
        always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
83 
                case (mb_num_h)
84 
                        0: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
85 
                        1: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
86 
                        2: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
87 
                        3: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
88 
                        4: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
89 
                        5: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
90 
                        6: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
91 
                        7: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
92 
                        8: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
93 
                        9: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
94 
                        10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
95 
                        default:MBTypeGen_mbAddrB <= 0;
96 
                endcase
97 
 
98 
        reg [1:0] bs_dec_counter;
99 
        always @ (posedge gclk_bs_dec or negedge reset_n)
100 
                if (reset_n == 1'b0)
101 
                        bs_dec_counter <= 0;
102 
                else
103 
                        bs_dec_counter <= bs_dec_counter - 1;
104 
 
105 
        assign end_of_BS_DEC = (bs_dec_counter == 2'd1)? 1'b1:1'b0;
106 
 
107 
        wire mvx_V0_diff_GE4,mvx_V1_diff_GE4,mvx_V2_diff_GE4,mvx_V3_diff_GE4;
108 
        wire mvy_V0_diff_GE4,mvy_V1_diff_GE4,mvy_V2_diff_GE4,mvy_V3_diff_GE4;
109 
        wire mvx_H0_diff_GE4,mvx_H1_diff_GE4,mvx_H2_diff_GE4,mvx_H3_diff_GE4;
110 
        wire mvy_H0_diff_GE4,mvy_H1_diff_GE4,mvy_H2_diff_GE4,mvy_H3_diff_GE4;
111 
 
112 
 
113 
        //--------------------------------------------------------------------
114 
        //If current MB is Inter,derive current MB non-zero coeff information
115 
        //No need to do this for P_skip or Intra.No need for chroma,either.
116 
        //--------------------------------------------------------------------
117 
        reg [15:0] currMB_coeff;//whether each 4x4blk of current MB has at least one non-zero transform coeff
118 
                                                        //currMB_coeff is organized in zig-zag order,according to blk4x4_rec_counter
119 
                                                        //= 1'b1:this 4x4blk has at least one non-zero transform coeff
120 
                                                        //= 1'b0:this 4x4blk has all 16 zero transform coeff
121 
                                                        //only useful for Inter (excluding P_skip) MB
122 
        always @ (posedge clk)
123 
                if (reset_n == 1'b0)
124 
                        currMB_coeff <= 16'd0;
125 
                else if (!disable_DF)
126 
                        begin
127 
                                //need to be reset evey MB
128 
                                //Since only Inter MB needs currMB_coeff,we can use "coded_block_pattern_s" state as timing slot
129 
                                if (slice_data_state == `coded_block_pattern_s)
130 
                                        currMB_coeff <= 16'd0;
131 
                                else if (mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101)   //Inter but not P_skip
132 
                                        case (residual_state)
133 
                                                `Intra16x16ACLevel_s:
134 
                                                if (end_of_one_residual_block)
135 
                                                        case (blk4x4_rec_counter[3:0])
136 
                                                                4'd0 :currMB_coeff[0]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
137 
                                                                4'd1 :currMB_coeff[1]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
138 
                                                                4'd2 :currMB_coeff[2]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
139 
                                                                4'd3 :currMB_coeff[3]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
140 
                                                                4'd4 :currMB_coeff[4]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
141 
                                                                4'd5 :currMB_coeff[5]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
142 
                                                                4'd6 :currMB_coeff[6]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
143 
                                                                4'd7 :currMB_coeff[7]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
144 
                                                                4'd8 :currMB_coeff[8]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
145 
                                                                4'd9 :currMB_coeff[9]  <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
146 
                                                                4'd10:currMB_coeff[10] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
147 
                                                                4'd11:currMB_coeff[11] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
148 
                                                                4'd12:currMB_coeff[12] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
149 
                                                                4'd13:currMB_coeff[13] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
150 
                                                                4'd14:currMB_coeff[14] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
151 
                                                                4'd15:currMB_coeff[15] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1;
152 
                                                        endcase
153 
                                                `Intra16x16ACLevel_0_s:
154 
                                                case (blk4x4_rec_counter[3:0])
155 
                                                        4'd0:currMB_coeff[0]   <= ~curr_DC_IsZero;
156 
                                                        4'd1:currMB_coeff[1]   <= ~curr_DC_IsZero;
157 
                                                        4'd2:currMB_coeff[2]   <= ~curr_DC_IsZero;
158 
                                                        4'd3:currMB_coeff[3]   <= ~curr_DC_IsZero;
159 
                                                        4'd4:currMB_coeff[4]   <= ~curr_DC_IsZero;
160 
                                                        4'd5:currMB_coeff[5]   <= ~curr_DC_IsZero;
161 
                                                        4'd6:currMB_coeff[6]   <= ~curr_DC_IsZero;
162 
                                                        4'd7:currMB_coeff[7]   <= ~curr_DC_IsZero;
163 
                                                        4'd8:currMB_coeff[8]   <= ~curr_DC_IsZero;
164 
                                                        4'd9:currMB_coeff[9]   <= ~curr_DC_IsZero;
165 
                                                        4'd10:currMB_coeff[10] <= ~curr_DC_IsZero;
166 
                                                        4'd11:currMB_coeff[11] <= ~curr_DC_IsZero;
167 
                                                        4'd12:currMB_coeff[12] <= ~curr_DC_IsZero;
168 
                                                        4'd13:currMB_coeff[13] <= ~curr_DC_IsZero;
169 
                                                        4'd14:currMB_coeff[14] <= ~curr_DC_IsZero;
170 
                                                        4'd15:currMB_coeff[15] <= ~curr_DC_IsZero;
171 
                                                endcase
172 
                                                `LumaLevel_s:
173 
                                                case (blk4x4_rec_counter[3:0])
174 
                                                        4'd0 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[0]  <= 1'b0;
175 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[0]  <= (TotalCoeff == 0)? 1'b0:1'b1;
176 
                                                        4'd1 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[1]      <= 1'b0;
177 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[1]  <= (TotalCoeff == 0)? 1'b0:1'b1;
178 
                                                        4'd2 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[2]      <= 1'b0;
179 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[2]  <= (TotalCoeff == 0)? 1'b0:1'b1;
180 
                                                        4'd3 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[3]      <= 1'b0;
181 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[3]  <= (TotalCoeff == 0)? 1'b0:1'b1;
182 
                                                        4'd4 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[4]     <= 1'b0;
183 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[4]  <= (TotalCoeff == 0)? 1'b0:1'b1;
184 
                                                        4'd5 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[5]     <= 1'b0;
185 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[5]  <= (TotalCoeff == 0)? 1'b0:1'b1;
186 
                                                        4'd6 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[6]     <= 1'b0;
187 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[6]  <= (TotalCoeff == 0)? 1'b0:1'b1;
188 
                                                        4'd7 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[7]     <= 1'b0;
189 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[7]  <= (TotalCoeff == 0)? 1'b0:1'b1;
190 
                                                        4'd8 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[8]     <= 1'b0;
191 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[8]  <= (TotalCoeff == 0)? 1'b0:1'b1;
192 
                                                        4'd9 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[9]     <= 1'b0;
193 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[9]  <= (TotalCoeff == 0)? 1'b0:1'b1;
194 
                                                        4'd10:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[10]    <= 1'b0;
195 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[10] <= (TotalCoeff == 0)? 1'b0:1'b1;
196 
                                                        4'd11:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[11] <= 1'b0;
197 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[11] <= (TotalCoeff == 0)? 1'b0:1'b1;
198 
                                                        4'd12:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[12] <= 1'b0;
199 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[12] <= (TotalCoeff == 0)? 1'b0:1'b1;
200 
                                                        4'd13:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[13] <= 1'b0;
201 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[13] <= (TotalCoeff == 0)? 1'b0:1'b1;
202 
                                                        4'd14:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[14] <= 1'b0;
203 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[14] <= (TotalCoeff == 0)? 1'b0:1'b1;
204 
                                                        4'd15:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[15] <= 1'b0;
205 
                                                                  else if (end_of_one_residual_block)   currMB_coeff[15] <= (TotalCoeff == 0)? 1'b0:1'b1;
206 
                                                endcase
207 
                                                `LumaLevel_0_s:currMB_coeff <= 16'd0;
208 
                                        endcase
209 
                        end
210 
 
211 
        //whether each 4x4blk of MB at mbAddrB has at least one non-zero transform coeff
212 
        reg [43:0] mbAddrB_coeff_reg;
213 
        always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
214 
                if (reset_n == 1'b0)
215 
                        mbAddrB_coeff_reg <= 44'd0;
216 
                else if (!disable_DF && mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101 && mb_num_v != 8) //Inter but not P_skip
217 
                        case (mb_num_h)
218 
                                4'd0 :mbAddrB_coeff_reg[3:0]   <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
219 
                                4'd1 :mbAddrB_coeff_reg[7:4]   <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
220 
                                4'd2 :mbAddrB_coeff_reg[11:8]  <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
221 
                                4'd3 :mbAddrB_coeff_reg[15:12] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
222 
                                4'd4 :mbAddrB_coeff_reg[19:16] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
223 
                                4'd5 :mbAddrB_coeff_reg[23:20] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
224 
                                4'd6 :mbAddrB_coeff_reg[27:24] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
225 
                                4'd7 :mbAddrB_coeff_reg[31:28] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
226 
                                4'd8 :mbAddrB_coeff_reg[35:32] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
227 
                                4'd9 :mbAddrB_coeff_reg[39:36] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
228 
                                4'd10:mbAddrB_coeff_reg[43:40] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]};
229 
                        endcase
230 
        //-------------------------------------------------
231 
        //backup mbAddrA coding information to derive bs_V0
232 
        //-------------------------------------------------
233 
        reg [3:0] mbAddrA_coeff;
234 
        reg [31:0] mbAddrA_mvx;
235 
        reg [31:0] mbAddrA_mvy;
236 
        always @ (posedge clk)
237 
                if (reset_n == 1'b0)
238 
                        begin
239 
                                mbAddrA_coeff <= 4'b0;
240 
                                mbAddrA_mvx      <= 32'b0;
241 
                                mbAddrA_mvy  <= 32'b0;
242 
                        end
243 
                else if (!disable_DF && mb_num_h != 0 &&
244 
                        ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrA[1] == 1'b0) //Current MB is P_skip
245 
                        || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0)))                             //Current MB is Inter
246 
                        begin
247 
                                mbAddrA_mvx <= mvx_mbAddrA;     mbAddrA_mvy <= mvy_mbAddrA;
248 
                                //if mbAddrA is Inter (not P_skip),back up non-zero residual coeff information
249 
                                if (MBTypeGen_mbAddrA[0] == 1'b0)        mbAddrA_coeff <= {currMB_coeff[15],currMB_coeff[13],currMB_coeff[7],currMB_coeff[5]};
250 
                        end
251 
        //-------------------------------------------------
252 
        //backup mbAddrB coding information to derive bs_H0
253 
        //-------------------------------------------------
254 
 
255 
        //1)For P_skip,at "Is_skipMB_mv_calc", no matter DF is enabled or not,mvx_mbAddrB/mvy_mbAddrB should be read to
256 
        //      derive current motion vector
257 
        //2)For Inter other than P_skip, mvx_mbAddrB/mvy_mbAddrB are read at mb_pred or sub_mb_pred state.So we add a new
258 
        //      signal "mv_mbAddrB_rd_for_DF" at "slice_data_state == `mb_type_s"
259 
        assign mv_mbAddrB_rd_for_DF = (!disable_DF && slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0 && mb_num_v != 0);
260 
        reg [3:0] mbAddrB_coeff;
261 
        reg [31:0] mbAddrB_mvx;
262 
        reg [31:0] mbAddrB_mvy;
263 
        always @ (posedge clk)
264 
                if (reset_n == 1'b0)
265 
                        begin
266 
                                mbAddrB_coeff <= 4'b0;
267 
                                mbAddrB_mvx      <= 32'b0;
268 
                                mbAddrB_mvy  <= 32'b0;
269 
                        end
270 
                else if (!disable_DF && mb_num_v != 0 &&
271 
                        ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrB[1] == 1'b0)   //Current MB is P_skip
272 
                        || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0)))                             //Current MB is Inter
273 
                        begin
274 
                                mbAddrB_mvx <= mvx_mbAddrB_dout;        mbAddrB_mvy <= mvy_mbAddrB_dout;
275 
                                //if mbAddrB is Inter (not P_skip),back up non-zero residual coeff information
276 
                                if (MBTypeGen_mbAddrB[0] == 1'b0)
277 
                                        case (mb_num_h)
278 
                                                4'd0 :mbAddrB_coeff <= mbAddrB_coeff_reg[3:0];
279 
                                                4'd1 :mbAddrB_coeff <= mbAddrB_coeff_reg[7:4];
280 
                                                4'd2 :mbAddrB_coeff <= mbAddrB_coeff_reg[11:8];
281 
                                                4'd3 :mbAddrB_coeff <= mbAddrB_coeff_reg[15:12];
282 
                                                4'd4 :mbAddrB_coeff <= mbAddrB_coeff_reg[19:16];
283 
                                                4'd5 :mbAddrB_coeff <= mbAddrB_coeff_reg[23:20];
284 
                                                4'd6 :mbAddrB_coeff <= mbAddrB_coeff_reg[27:24];
285 
                                                4'd7 :mbAddrB_coeff <= mbAddrB_coeff_reg[31:28];
286 
                                                4'd8 :mbAddrB_coeff <= mbAddrB_coeff_reg[35:32];
287 
                                                4'd9 :mbAddrB_coeff <= mbAddrB_coeff_reg[39:36];
288 
                                                4'd10:mbAddrB_coeff <= mbAddrB_coeff_reg[43:40];
289 
                                        endcase
290 
                        end
291 
 
292 
        always @ (posedge gclk_bs_dec or negedge reset_n)
293 
                if (reset_n == 1'b0)
294 
                        begin
295 
                                bs_V0 <= 0;      bs_V1 <= 0;      bs_V2 <= 0;      bs_V3 <= 0;
296 
                                bs_H0 <= 0;      bs_H1 <= 0;      bs_H2 <= 0;      bs_H3 <= 0;
297 
                        end
298 
                //-----------------------
299 
                //Current MB is P_skip
300 
                //-----------------------
301 
                else if (mb_type_general_DF == `MB_P_skip)
302 
                        case (bs_dec_counter)
303 
                                2'b00:
304 
                                begin
305 
                                        //V0
306 
                                        if (mb_num_h == 0)                                               //edge of frame,bs = 0
307 
                                                bs_V0 <= 12'b0;
308 
                                        else if (MBTypeGen_mbAddrA[1] == 1'b1)  //mbAddrA is Intra,bs = 4
309 
                                                bs_V0 <= 12'b100100100100;
310 
                                        else if (MBTypeGen_mbAddrA    == `MB_addrA_addrB_P_skip)        //mbAddrA is P_skip
311 
                                                bs_V0 <= (mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 12'b001001001001:12'b0;
312 
                                        else                                                                    //mbAddrA is Inter
313 
                                                begin
314 
                                                        bs_V0[2:0]  <= (mbAddrA_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
315 
                                                        bs_V0[5:3]  <= (mbAddrA_coeff[1])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
316 
                                                        bs_V0[8:6]  <= (mbAddrA_coeff[2])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
317 
                                                        bs_V0[11:9] <= (mbAddrA_coeff[3])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
318 
                                                end
319 
                                        //H0
320 
                                        if (mb_num_v == 0)                                               //edge of frame,bs = 0
321 
                                                bs_H0 <= 12'b0;
322 
                                        else if (MBTypeGen_mbAddrB[1] == 1'b1)  //mbAddrB is Intra,bs=4
323 
                                                bs_H0 <= 12'b100100100100;
324 
                                        else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip)   //mbAddrB is P_skip
325 
                                                bs_H0 <= (mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 12'b001001001001:12'b0;
326 
                                        else
327 
                                                begin
328 
                                                        bs_H0[2:0]  <= (mbAddrB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
329 
                                                        bs_H0[5:3]  <= (mbAddrB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
330 
                                                        bs_H0[8:6]  <= (mbAddrB_coeff[2])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
331 
                                                        bs_H0[11:9] <= (mbAddrB_coeff[3])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
332 
                                                end
333 
                                end
334 
                                2'b11:begin     bs_V1 <= 0;      bs_H1 <= 0;      end
335 
                                2'b10:begin     bs_V2 <= 0;      bs_H2 <= 0;      end
336 
                                2'b01:begin     bs_V3 <= 0;      bs_H3 <= 0;      end
337 
                        endcase
338 
                        //--------------------
339 
                        //Current MB is Intra
340 
                        //-----------------------
341 
                        else if (mb_type_general_DF[3] == 1'b1)
342 
                                case (bs_dec_counter)
343 
                                        2'b00:
344 
                                        begin
345 
                                                bs_V0 <= (mb_num_h == 0)? 12'b0:12'b100100100100;
346 
                                                bs_H0 <= (mb_num_v == 0)? 12'b0:12'b100100100100;
347 
                                        end
348 
                                        2'b11:begin bs_V1 <= 12'b011011011011;  bs_H1 <= 12'b011011011011; end
349 
                                        2'b10:begin bs_V2 <= 12'b011011011011;  bs_H2 <= 12'b011011011011; end
350 
                                        2'b01:begin     bs_V3 <= 12'b011011011011;      bs_H3 <= 12'b011011011011; end
351 
                                endcase
352 
                        //-----------------------
353 
                        //Current MB is Inter
354 
                        //-----------------------
355 
                        else
356 
                                case (bs_dec_counter)
357 
                                        2'b00:  //V0,H0
358 
                                        begin
359 
                                                //V0
360 
                                                if (mb_num_h == 0)                                               //edge of frame,bs = 0
361 
                                                        bs_V0 <= 12'b0;
362 
                                                else if (MBTypeGen_mbAddrA[1] == 1'b1)  //mbAddrA is Intra,bs = 4
363 
                                                        bs_V0 <= 12'b100100100100;
364 
                                                else if (MBTypeGen_mbAddrA    == `MB_addrA_addrB_P_skip)        //mbAddrA is P_skip
365 
                                                        begin
366 
                                                                bs_V0[2:0]  <= (currMB_coeff[0])?  3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
367 
                                                                bs_V0[5:3]  <= (currMB_coeff[2])?  3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
368 
                                                                bs_V0[8:6]  <= (currMB_coeff[8])?  3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
369 
                                                                bs_V0[11:9] <= (currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
370 
                                                        end
371 
                                                else                                                                    //mbAddrA is Inter
372 
                                                        begin
373 
                                                                bs_V0[2:0]  <= (mbAddrA_coeff[0] || currMB_coeff[0])?  3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
374 
                                                                bs_V0[5:3]  <= (mbAddrA_coeff[1] || currMB_coeff[2])?  3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
375 
                                                                bs_V0[8:6]  <= (mbAddrA_coeff[2] || currMB_coeff[8])?  3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
376 
                                                                bs_V0[11:9] <= (mbAddrA_coeff[3] || currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
377 
                                                        end
378 
                                                //H0
379 
                                                if (mb_num_v == 0)                                               //edge of frame,bs = 0
380 
                                                        bs_H0 <= 12'b0;
381 
                                                else if (MBTypeGen_mbAddrB[1] == 1'b1)  //mbAddrB is Intra,bs = 4
382 
                                                        bs_H0 <= 12'b100100100100;
383 
                                                else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip)   //mbAddrB is P_skip
384 
                                                        begin
385 
                                                                bs_H0[2:0]  <= (currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
386 
                                                                bs_H0[5:3]  <= (currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
387 
                                                                bs_H0[8:6]  <= (currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
388 
                                                                bs_H0[11:9] <= (currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
389 
                                                        end
390 
                                                else                                                                            //mbAddrB is Inter
391 
                                                        begin
392 
                                                                bs_H0[2:0]  <= (mbAddrB_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
393 
                                                                bs_H0[5:3]  <= (mbAddrB_coeff[1] || currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
394 
                                                                bs_H0[8:6]  <= (mbAddrB_coeff[2] || currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
395 
                                                                bs_H0[11:9] <= (mbAddrB_coeff[3] || currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
396 
                                                        end
397 
                                        end
398 
                                        2'b11://V1,H1
399 
                                        begin
400 
                                                bs_V1[2:0]  <= (currMB_coeff[0]  || currMB_coeff[1])?  3'd2:(MB_inter_size != `I8x8)?
401 
                                                                                0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
402 
 
403 
                                                bs_V1[5:3]  <= (currMB_coeff[2]  || currMB_coeff[3])?  3'd2:(MB_inter_size != `I8x8)?
404 
                                                                                0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
405 
 
406 
                                                bs_V1[8:6]  <= (currMB_coeff[8]  || currMB_coeff[9])?  3'd2:(MB_inter_size != `I8x8)?
407 
                                                                                0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
408 
 
409 
                                                bs_V1[11:9] <= (currMB_coeff[10] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)?
410 
                                                                                0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
411 
 
412 
                                                bs_H1[2:0]  <= (currMB_coeff[0]  || currMB_coeff[2])?  3'd2:(MB_inter_size != `I8x8)?
413 
                                                                                0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
414 
 
415 
                                                bs_H1[5:3]  <= (currMB_coeff[1]  || currMB_coeff[3])?  3'd2:(MB_inter_size != `I8x8)?
416 
                                                                                0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
417 
 
418 
                                                bs_H1[8:6]  <= (currMB_coeff[4]  || currMB_coeff[6])?  3'd2:(MB_inter_size != `I8x8)?
419 
                                                                                0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
420 
                                                bs_H1[11:9] <= (currMB_coeff[5]  || currMB_coeff[7])?  3'd2:(MB_inter_size != `I8x8)?
421 
                                                                                0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
422 
                                        end
423 
                                        2'b10://V2,H2
424 
                                        begin
425 
                                                bs_V2[2:0]  <= (currMB_coeff[1]  || currMB_coeff[4])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
426 
                                                                                0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
427 
 
428 
                                                bs_V2[5:3]  <= (currMB_coeff[3]  || currMB_coeff[6])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
429 
                                                                                0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
430 
 
431 
                                                bs_V2[8:6]  <= (currMB_coeff[9]  || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
432 
                                                                                0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
433 
 
434 
                                                bs_V2[11:9] <= (currMB_coeff[11] || currMB_coeff[14])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)?
435 
                                                                                0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
436 
 
437 
                                                bs_H2[2:0]  <= (currMB_coeff[2]  || currMB_coeff[8])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
438 
                                                                                0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
439 
 
440 
                                                bs_H2[5:3]  <= (currMB_coeff[3]  || currMB_coeff[9])?  3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
441 
                                                                                0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
442 
 
443 
                                                bs_H2[8:6]  <= (currMB_coeff[6]  || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
444 
                                                                                0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
445 
 
446 
                                                bs_H2[11:9] <= (currMB_coeff[7]  || currMB_coeff[13])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)?
447 
                                                                                0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
448 
                                        end
449 
                                        2'b01://V3,H3
450 
                                        begin
451 
                                                bs_V3[2:0]  <= (currMB_coeff[4]  || currMB_coeff[5])?  3'd2:(MB_inter_size != `I8x8)?
452 
                                                                                0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0;
453 
 
454 
                                                bs_V3[5:3]  <= (currMB_coeff[6]  || currMB_coeff[7])?  3'd2:(MB_inter_size != `I8x8)?
455 
                                                                                0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0;
456 
 
457 
                                                bs_V3[8:6]  <= (currMB_coeff[12] || currMB_coeff[13])? 3'd2:(MB_inter_size != `I8x8)?
458 
                                                                                0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0;
459 
 
460 
                                                bs_V3[11:9] <= (currMB_coeff[14] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)?
461 
                                                                                0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0;
462 
 
463 
                                                bs_H3[2:0]  <= (currMB_coeff[8]  || currMB_coeff[10])? 3'd2:(MB_inter_size != `I8x8)?
464 
                                                                                0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0;
465 
 
466 
                                                bs_H3[5:3]  <= (currMB_coeff[9]  || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)?
467 
                                                                                0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0;
468 
 
469 
                                                bs_H3[8:6]  <= (currMB_coeff[12] || currMB_coeff[14])? 3'd2:(MB_inter_size != `I8x8)?
470 
                                                                                0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0;
471 
 
472 
                                                bs_H3[11:9]  <= (currMB_coeff[13] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)?
473 
                                                                                0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0;
474 
                                        end
475 
                                endcase
476 
 
477 
        reg [7:0] mvx_V0_diff_a,mvx_V0_diff_b;
478 
        reg [7:0] mvx_V1_diff_a,mvx_V1_diff_b;
479 
        reg [7:0] mvx_V2_diff_a,mvx_V2_diff_b;
480 
        reg [7:0] mvx_V3_diff_a,mvx_V3_diff_b;
481 
        reg [7:0] mvy_V0_diff_a,mvy_V0_diff_b;
482 
        reg [7:0] mvy_V1_diff_a,mvy_V1_diff_b;
483 
        reg [7:0] mvy_V2_diff_a,mvy_V2_diff_b;
484 
        reg [7:0] mvy_V3_diff_a,mvy_V3_diff_b;
485 
 
486 
        reg [7:0] mvx_H0_diff_a,mvx_H0_diff_b;
487 
        reg [7:0] mvx_H1_diff_a,mvx_H1_diff_b;
488 
        reg [7:0] mvx_H2_diff_a,mvx_H2_diff_b;
489 
        reg [7:0] mvx_H3_diff_a,mvx_H3_diff_b;
490 
        reg [7:0] mvy_H0_diff_a,mvy_H0_diff_b;
491 
        reg [7:0] mvy_H1_diff_a,mvy_H1_diff_b;
492 
        reg [7:0] mvy_H2_diff_a,mvy_H2_diff_b;
493 
        reg [7:0] mvy_H3_diff_a,mvy_H3_diff_b;
494 
 
495 
        mv_diff_GE4 mvx_V0_diff (.mv_a(mvx_V0_diff_a),.mv_b(mvx_V0_diff_b),.diff_GE4(mvx_V0_diff_GE4));
496 
        mv_diff_GE4 mvx_V1_diff (.mv_a(mvx_V1_diff_a),.mv_b(mvx_V1_diff_b),.diff_GE4(mvx_V1_diff_GE4));
497 
        mv_diff_GE4 mvx_V2_diff (.mv_a(mvx_V2_diff_a),.mv_b(mvx_V2_diff_b),.diff_GE4(mvx_V2_diff_GE4));
498 
        mv_diff_GE4 mvx_V3_diff (.mv_a(mvx_V3_diff_a),.mv_b(mvx_V3_diff_b),.diff_GE4(mvx_V3_diff_GE4));
499 
        mv_diff_GE4 mvy_V0_diff (.mv_a(mvy_V0_diff_a),.mv_b(mvy_V0_diff_b),.diff_GE4(mvy_V0_diff_GE4));
500 
        mv_diff_GE4 mvy_V1_diff (.mv_a(mvy_V1_diff_a),.mv_b(mvy_V1_diff_b),.diff_GE4(mvy_V1_diff_GE4));
501 
        mv_diff_GE4 mvy_V2_diff (.mv_a(mvy_V2_diff_a),.mv_b(mvy_V2_diff_b),.diff_GE4(mvy_V2_diff_GE4));
502 
        mv_diff_GE4 mvy_V3_diff (.mv_a(mvy_V3_diff_a),.mv_b(mvy_V3_diff_b),.diff_GE4(mvy_V3_diff_GE4));
503 
 
504 
        mv_diff_GE4 mvx_H0_diff (.mv_a(mvx_H0_diff_a),.mv_b(mvx_H0_diff_b),.diff_GE4(mvx_H0_diff_GE4));
505 
        mv_diff_GE4 mvx_H1_diff (.mv_a(mvx_H1_diff_a),.mv_b(mvx_H1_diff_b),.diff_GE4(mvx_H1_diff_GE4));
506 
        mv_diff_GE4 mvx_H2_diff (.mv_a(mvx_H2_diff_a),.mv_b(mvx_H2_diff_b),.diff_GE4(mvx_H2_diff_GE4));
507 
        mv_diff_GE4 mvx_H3_diff (.mv_a(mvx_H3_diff_a),.mv_b(mvx_H3_diff_b),.diff_GE4(mvx_H3_diff_GE4));
508 
        mv_diff_GE4 mvy_H0_diff (.mv_a(mvy_H0_diff_a),.mv_b(mvy_H0_diff_b),.diff_GE4(mvy_H0_diff_GE4));
509 
        mv_diff_GE4 mvy_H1_diff (.mv_a(mvy_H1_diff_a),.mv_b(mvy_H1_diff_b),.diff_GE4(mvy_H1_diff_GE4));
510 
        mv_diff_GE4 mvy_H2_diff (.mv_a(mvy_H2_diff_a),.mv_b(mvy_H2_diff_b),.diff_GE4(mvy_H2_diff_GE4));
511 
        mv_diff_GE4 mvy_H3_diff (.mv_a(mvy_H3_diff_a),.mv_b(mvy_H3_diff_b),.diff_GE4(mvy_H3_diff_GE4));
512 
 
513 
        always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF
514 
                or mb_num_h or MB_inter_size or MBTypeGen_mbAddrA
515 
                or mbAddrA_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
516 
                or mbAddrA_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3)
517 
                if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0)
518 
                        begin
519 
                                //-----------------------
520 
                                //Current MB is P_skip
521 
                                //-----------------------
522 
                                if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00)//V0
523 
                                        begin
524 
                                                if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip)                //mbAddrA is P_skip
525 
                                                        begin
526 
                                                                mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0];
527 
                                                                mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
528 
                                                                mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
529 
                                                                mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
530 
                                                                mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0];
531 
                                                                mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
532 
                                                                mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
533 
                                                                mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
534 
                                                        end
535 
                                                else if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_Inter)    //mbAddrA is Inter
536 
                                                        begin
537 
                                                                mvx_V0_diff_a <= mbAddrA_mvx[7:0];  mvx_V0_diff_b <= mvx_CurrMb0[7:0];
538 
                                                                mvx_V1_diff_a <= mbAddrA_mvx[15:8]; mvx_V1_diff_b <= mvx_CurrMb0[7:0];
539 
                                                                mvx_V2_diff_a <= mbAddrA_mvx[23:16];mvx_V2_diff_b <= mvx_CurrMb0[7:0];
540 
                                                                mvx_V3_diff_a <= mbAddrA_mvx[31:24];mvx_V3_diff_b <= mvx_CurrMb0[7:0];
541 
                                                                mvy_V0_diff_a <= mbAddrA_mvy[7:0];  mvy_V0_diff_b <= mvy_CurrMb0[7:0];
542 
                                                                mvy_V1_diff_a <= mbAddrA_mvy[15:8]; mvy_V1_diff_b <= mvy_CurrMb0[7:0];
543 
                                                                mvy_V2_diff_a <= mbAddrA_mvy[23:16];mvy_V2_diff_b <= mvy_CurrMb0[7:0];
544 
                                                                mvy_V3_diff_a <= mbAddrA_mvy[31:24];mvy_V3_diff_b <= mvy_CurrMb0[7:0];
545 
                                                        end
546 
                                                else
547 
                                                        begin
548 
                                                                mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
549 
                                                                mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
550 
                                                                mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
551 
                                                                mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
552 
                                                                mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
553 
                                                                mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
554 
                                                                mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
555 
                                                                mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
556 
                                                        end
557 
                                        end
558 
                                //-----------------------
559 
                                //Current MB is Inter
560 
                                //-----------------------
561 
                                else if (mb_type_general_DF[3] == 1'b0)
562 
                                        case (bs_dec_counter)
563 
                                                2'b00:  //V0
564 
                                                if (mb_num_h != 0 && (MBTypeGen_mbAddrA[1] == 1'b0)) //mbAddrA is P_skip or Inter
565 
                                                        begin
566 
                                                                mvx_V0_diff_a <= mbAddrA_mvx[7:0];  mvx_V0_diff_b <= mvx_CurrMb0[7:0];
567 
 
568 
                                                                mvx_V1_diff_a <= mbAddrA_mvx[15:8];
569 
                                                                mvx_V1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[23:16];
570 
 
571 
                                                                mvx_V2_diff_a <= mbAddrA_mvx[23:16];
572 
                                                                mvx_V2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[7:0];
573 
 
574 
                                                                mvx_V3_diff_a <= mbAddrA_mvx[31:24];
575 
                                                                mvx_V3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[23:16];
576 
 
577 
                                                                mvy_V0_diff_a <= mbAddrA_mvy[7:0];  mvy_V0_diff_b <= mvy_CurrMb0[7:0];
578 
 
579 
                                                                mvy_V1_diff_a <= mbAddrA_mvy[15:8];
580 
                                                                mvy_V1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[23:16];
581 
 
582 
                                                                mvy_V2_diff_a <= mbAddrA_mvy[23:16];
583 
                                                                mvy_V2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[7:0];
584 
 
585 
                                                                mvy_V3_diff_a <= mbAddrA_mvy[31:24];
586 
                                                                mvy_V3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[23:16];
587 
                                                        end
588 
                                                else
589 
                                                        begin
590 
                                                                mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
591 
                                                                mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
592 
                                                                mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
593 
                                                                mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
594 
                                                                mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
595 
                                                                mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
596 
                                                                mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
597 
                                                                mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
598 
                                                        end
599 
                                                2'b11:  //V1
600 
                                                begin
601 
                                                        mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0];
602 
                                                        mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8];
603 
                                                        mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16];
604 
                                                        mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24];
605 
                                                        mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0];
606 
                                                        mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8];
607 
                                                        mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16];
608 
                                                        mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24];
609 
 
610 
                                                        mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0];
611 
                                                        mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8];
612 
                                                        mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16];
613 
                                                        mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24];
614 
                                                        mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0];
615 
                                                        mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8];
616 
                                                        mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16];
617 
                                                        mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24];
618 
                                                end
619 
                                                2'b10:  //V2
620 
                                                begin
621 
                                                        mvx_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[15:8];
622 
                                                        mvx_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[7:0];
623 
                                                        mvx_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[31:24];
624 
                                                        mvx_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[23:16];
625 
                                                        mvx_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[15:8];
626 
                                                        mvx_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[7:0];
627 
                                                        mvx_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[31:24];
628 
                                                        mvx_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[23:16];
629 
                                                        mvy_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[15:8];
630 
                                                        mvy_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[7:0];
631 
                                                        mvy_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[31:24];
632 
                                                        mvy_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[23:16];
633 
                                                        mvy_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[15:8];
634 
                                                        mvy_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[7:0];
635 
                                                        mvy_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[31:24];
636 
                                                        mvy_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[23:16];
637 
                                                end
638 
                                                2'b01:  //V3
639 
                                                begin
640 
                                                        mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0];
641 
                                                        mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8];
642 
                                                        mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16];
643 
                                                        mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24];
644 
                                                        mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0];
645 
                                                        mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8];
646 
                                                        mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16];
647 
                                                        mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24];
648 
 
649 
                                                        mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0];
650 
                                                        mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8];
651 
                                                        mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16];
652 
                                                        mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24];
653 
                                                        mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0];
654 
                                                        mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8];
655 
                                                        mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16];
656 
                                                        mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24];
657 
                                                end
658 
                                        endcase
659 
                                else
660 
                                        begin
661 
                                                mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
662 
                                                mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
663 
                                                mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
664 
                                                mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
665 
                                                mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
666 
                                                mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
667 
                                                mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
668 
                                                mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
669 
                                        end
670 
                        end
671 
                else
672 
                        begin
673 
                                mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0;
674 
                                mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0;
675 
                                mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0;
676 
                                mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0;
677 
                                mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0;
678 
                                mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0;
679 
                                mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0;
680 
                                mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0;
681 
                        end
682 
 
683 
 
684 
        always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF
685 
                or mb_num_v or MBTypeGen_mbAddrB or MB_inter_size
686 
                or mbAddrB_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3
687 
                or mbAddrB_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3)
688 
                if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0)
689 
                        begin
690 
                                //-----------------------
691 
                                //Current MB is P_skip
692 
                                //-----------------------
693 
                                if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00)        //H0
694 
                                        begin
695 
                                                if (mb_num_v != 0 && MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip)                //mbAddrB is P_skip
696 
                                                        begin
697 
                                                                mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
698 
                                                                mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
699 
                                                                mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
700 
                                                                mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
701 
                                                                mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
702 
                                                                mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
703 
                                                                mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
704 
                                                                mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
705 
                                                        end
706 
                                                else if (mb_num_v != 0 && MBTypeGen_mbAddrB == 2'b00)    //mbAddrB is Inter
707 
                                                        begin
708 
                                                                mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
709 
                                                                mvx_H1_diff_a <= mbAddrB_mvx[23:16]; mvx_H1_diff_b <= mvx_CurrMb0[7:0];
710 
                                                                mvx_H2_diff_a <= mbAddrB_mvx[15:8];  mvx_H2_diff_b <= mvx_CurrMb0[7:0];
711 
                                                                mvx_H3_diff_a <= mbAddrB_mvx[7:0];   mvx_H3_diff_b <= mvx_CurrMb0[7:0];
712 
                                                                mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
713 
                                                                mvy_H1_diff_a <= mbAddrB_mvy[23:16]; mvy_H1_diff_b <= mvy_CurrMb0[7:0];
714 
                                                                mvy_H2_diff_a <= mbAddrB_mvy[15:8];  mvy_H2_diff_b <= mvy_CurrMb0[7:0];
715 
                                                                mvy_H3_diff_a <= mbAddrB_mvy[7:0];   mvy_H3_diff_b <= mvy_CurrMb0[7:0];
716 
                                                        end
717 
                                                else
718 
                                                        begin
719 
                                                                mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
720 
                                                                mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
721 
                                                                mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
722 
                                                                mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
723 
                                                                mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
724 
                                                                mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
725 
                                                                mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
726 
                                                                mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
727 
                                                        end
728 
                                        end
729 
                                //-----------------------
730 
                                //Current MB is Inter
731 
                                //-----------------------
732 
                                else if (mb_type_general_DF[3] == 1'b0)
733 
                                        case (bs_dec_counter)
734 
                                                2'b00:  //H0
735 
                                                if (mb_num_v != 0 && (MBTypeGen_mbAddrB[1] == 1'b0))//mbAddrB is P_skip or Inter
736 
                                                        begin
737 
                                                                mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0];
738 
 
739 
                                                                mvx_H1_diff_a <= mbAddrB_mvx[23:16];
740 
                                                                mvx_H1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[15:8];
741 
 
742 
                                                                mvx_H2_diff_a <= mbAddrB_mvx[15:8];
743 
                                                                mvx_H2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[7:0];
744 
 
745 
                                                                mvx_H3_diff_a <= mbAddrB_mvx[7:0];
746 
                                                                mvx_H3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[15:8];
747 
 
748 
                                                                mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0];
749 
 
750 
                                                                mvy_H1_diff_a <= mbAddrB_mvy[23:16];
751 
                                                                mvy_H1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[15:8];
752 
 
753 
                                                                mvy_H2_diff_a <= mbAddrB_mvy[15:8];
754 
                                                                mvy_H2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[7:0];
755 
 
756 
                                                                mvy_H3_diff_a <= mbAddrB_mvy[7:0];
757 
                                                                mvy_H3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[15:8];
758 
                                                        end
759 
                                                else
760 
                                                        begin
761 
                                                                mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
762 
                                                                mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
763 
                                                                mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
764 
                                                                mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
765 
                                                                mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
766 
                                                                mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
767 
                                                                mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
768 
                                                                mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
769 
                                                        end
770 
                                                2'b11:  //H1
771 
                                                begin
772 
                                                        mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0];
773 
                                                        mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16];
774 
                                                        mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8];
775 
                                                        mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24];
776 
                                                        mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0];
777 
                                                        mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16];
778 
                                                        mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8];
779 
                                                        mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24];
780 
 
781 
                                                        mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0];
782 
                                                        mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16];
783 
                                                        mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8];
784 
                                                        mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24];
785 
                                                        mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0];
786 
                                                        mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16];
787 
                                                        mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8];
788 
                                                        mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24];
789 
                                                end
790 
                                                2'b10:  //H2
791 
                                                begin
792 
                                                        mvx_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[23:16];
793 
                                                        mvx_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[7:0];
794 
                                                        mvx_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[31:24];
795 
                                                        mvx_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[15:8];
796 
                                                        mvx_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[23:16];
797 
                                                        mvx_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[7:0];
798 
                                                        mvx_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[31:24];
799 
                                                        mvx_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[15:8];
800 
 
801 
                                                        mvy_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[23:16];
802 
                                                        mvy_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[7:0];
803 
                                                        mvy_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[31:24];
804 
                                                        mvy_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[15:8];
805 
                                                        mvy_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[23:16];
806 
                                                        mvy_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[7:0];
807 
                                                        mvy_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[31:24];
808 
                                                        mvy_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[15:8];
809 
 
810 
                                                end
811 
                                                2'b01:  //H3
812 
                                                begin
813 
                                                        mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0];
814 
                                                        mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16];
815 
                                                        mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8];
816 
                                                        mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24];
817 
                                                        mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0];
818 
                                                        mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16];
819 
                                                        mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8];
820 
                                                        mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24];
821 
 
822 
                                                        mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0];
823 
                                                        mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16];
824 
                                                        mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8];
825 
                                                        mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24];
826 
                                                        mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0];
827 
                                                        mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16];
828 
                                                        mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8];
829 
                                                        mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24];
830 
                                                end
831 
                                        endcase
832 
                                else
833 
                                        begin
834 
                                                mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
835 
                                                mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
836 
                                                mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
837 
                                                mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
838 
                                                mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
839 
                                                mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
840 
                                                mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
841 
                                                mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
842 
                                        end
843 
                        end
844 
                else
845 
                        begin
846 
                                mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0;
847 
                                mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0;
848 
                                mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0;
849 
                                mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0;
850 
                                mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0;
851 
                                mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0;
852 
                                mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0;
853 
                                mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0;
854 
                        end
855 
        /*
856 
        // synopsys translate_off
857 
        integer tracefile;
858 
        integer pic_num;
859 
        wire [6:0] mb_num;
860 
        assign mb_num = mb_num_v * 11 + mb_num_h;
861 
 
862 
        initial
863 
                begin
864 
                        tracefile = $fopen("bs_trace.txt");
865 
                end
866 
        reg bs_dec_will_end;
867 
        always @ (posedge clk)
868 
                if (bs_dec_counter == 2'b01)
869 
                        bs_dec_will_end <= 1'b1;
870 
                else
871 
                        bs_dec_will_end <= 1'b0;
872 
        always @ (posedge clk or negedge reset_n)
873 
                if (reset_n == 1'b0)
874 
                        pic_num <= 0;
875 
                else if (bs_dec_will_end)
876 
                        begin
877 
                                $fdisplay (tracefile, "-------------------------------");
878 
                                if (mb_num == 0)
879 
                                        $fdisplay (tracefile, " Pic_num = %3d,MB_num =  98",(pic_num - 1));
880 
                                else
881 
                                        $fdisplay (tracefile, " Pic_num = %3d,MB_num = %3d",pic_num,(mb_num - 1));
882 
                                $fdisplay (tracefile, " Vertical   Edge 0:Bs = %d,%d,%d,%d",bs_V0[2:0],bs_V0[5:3],bs_V0[8:6],bs_V0[11:9]);
883 
                                $fdisplay (tracefile, " Vertical   Edge 1:Bs = %d,%d,%d,%d",bs_V1[2:0],bs_V1[5:3],bs_V1[8:6],bs_V1[11:9]);
884 
                                $fdisplay (tracefile, " Vertical   Edge 2:Bs = %d,%d,%d,%d",bs_V2[2:0],bs_V2[5:3],bs_V2[8:6],bs_V2[11:9]);
885 
                                $fdisplay (tracefile, " Vertical   Edge 3:Bs = %d,%d,%d,%d",bs_V3[2:0],bs_V3[5:3],bs_V3[8:6],bs_V3[11:9]);
886 
                                $fdisplay (tracefile, " Horizontal Edge 0:Bs = %d,%d,%d,%d",bs_H0[2:0],bs_H0[5:3],bs_H0[8:6],bs_H0[11:9]);
887 
                                $fdisplay (tracefile, " Horizontal Edge 1:Bs = %d,%d,%d,%d",bs_H1[2:0],bs_H1[5:3],bs_H1[8:6],bs_H1[11:9]);
888 
                                $fdisplay (tracefile, " Horizontal Edge 2:Bs = %d,%d,%d,%d",bs_H2[2:0],bs_H2[5:3],bs_H2[8:6],bs_H2[11:9]);
889 
                                $fdisplay (tracefile, " Horizontal Edge 3:Bs = %d,%d,%d,%d",bs_H3[2:0],bs_H3[5:3],bs_H3[8:6],bs_H3[11:9]);
890 
                                if (mb_num == 98)
891 
                                        pic_num <= pic_num + 1;
892 
                        end
893 
        // synopsys translate_on
894 
        */
895 
endmodule
896 
 
897 
module mv_diff_GE4 (mv_a,mv_b,diff_GE4);
898 
        input [7:0] mv_a,mv_b;
899 
        output diff_GE4;
900 
        wire [7:0] diff_tmp;
901 
        wire [6:0] diff;
902 
        assign diff_tmp = mv_a + ~ mv_b + 1;
903 
        assign diff     = (diff_tmp[7] == 1'b1)? (~diff_tmp[6:0] + 1):diff_tmp[6:0];
904 
        assign diff_GE4 = (diff[6:2] != 0)? 1'b1:1'b0;
905 
endmodule
906 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.