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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : nova.v
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// Generated : Feb 25,2006
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Top module of nova design, including two main blocks: BitStream controller and reconstruction datapath
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module nova (clk,reset_n,BitStream_buffer_input,BitStream_ram_ren,BitStream_ram_addr,
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pic_num,pin_disable_DF,freq_ctrl0,freq_ctrl1,
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ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
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ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data,
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dis_frame_RAM_din,
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slice_header_s6
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);
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input clk,reset_n;
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input [15:0] BitStream_buffer_input;
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input pin_disable_DF;
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input freq_ctrl0;
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input freq_ctrl1;
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output BitStream_ram_ren;
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output [16:0] BitStream_ram_addr;
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output [5:0] pic_num;
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//---ext_frame_RAM0---
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output ext_frame_RAM0_cs_n;
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output ext_frame_RAM0_wr;
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output [13:0] ext_frame_RAM0_addr;
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//inout [31:0] ext_frame_RAM0_data;
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input [31:0] ext_frame_RAM0_data;
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//---ext_frame_RAM1---
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output ext_frame_RAM1_cs_n;
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output ext_frame_RAM1_wr;
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output [13:0] ext_frame_RAM1_addr;
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//inout [31:0] ext_frame_RAM1_data;
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input [31:0] ext_frame_RAM1_data;
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output [31:0] dis_frame_RAM_din;
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output slice_header_s6;
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wire trigger_CAVLC;
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wire end_of_NonZeroCoeff_CAVLC;
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wire end_of_DCBlk_IQIT;
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wire end_of_one_blk4x4_sum;
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wire end_of_MB_DEC;
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wire gclk_end_of_MB_DEC;
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wire end_of_one_residual_block;
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wire end_of_one_frame;
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wire Is_skip_run_entry;
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wire Is_skip_run_end;
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wire skip_mv_calc;
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wire [3:0] mb_type_general;
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wire [3:0] mb_num_h;
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wire [3:0] mb_num_v;
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wire NextMB_IsSkip;
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wire LowerMB_IsSkip;
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wire [4:0] blk4x4_rec_counter;
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wire [3:0] slice_data_state;
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wire [3:0] residual_state;
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wire [3:0] cavlc_decoder_state;
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wire [1:0] Intra16x16_predmode;
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wire [63:0] Intra4x4_predmode_CurrMb;
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wire [1:0] Intra_chroma_predmode;
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wire [5:0] QPy;
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wire [5:0] QPc;
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wire [1:0] i4x4_CbCr;
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wire [3:0] slice_alpha_c0_offset_div2;
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wire [3:0] slice_beta_offset_div2;
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wire [3:0] CodedBlockPatternLuma;
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wire [1:0] CodedBlockPatternChroma;
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wire [4:0] TotalCoeff;
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wire disable_DF;
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wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
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wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
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wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
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wire mv_is16x16;
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wire [3:0] mv_below8x8;
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wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
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wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
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wire curr_DC_IsZero;
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wire end_of_BS_DEC;
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BitStream_controller BitStream_controller (
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.clk(clk),
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.reset_n(reset_n),
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.freq_ctrl0(freq_ctrl0),
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.freq_ctrl1(freq_ctrl1),
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.BitStream_buffer_input(BitStream_buffer_input),
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.pin_disable_DF(pin_disable_DF),
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.trigger_CAVLC(trigger_CAVLC),
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.blk4x4_rec_counter(blk4x4_rec_counter),
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.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
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.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
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.end_of_MB_DEC(end_of_MB_DEC),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.curr_DC_IsZero(curr_DC_IsZero),
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.BitStream_ram_ren(BitStream_ram_ren),
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.BitStream_ram_addr(BitStream_ram_addr),
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.pic_num(pic_num),
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.mb_type_general(mb_type_general),
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.mb_num_h(mb_num_h),
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.mb_num_v(mb_num_v),
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.NextMB_IsSkip(NextMB_IsSkip),
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.LowerMB_IsSkip(LowerMB_IsSkip),
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.slice_data_state(slice_data_state),
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.residual_state(residual_state),
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.cavlc_decoder_state(cavlc_decoder_state),
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.end_of_one_residual_block(end_of_one_residual_block),
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.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
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.end_of_one_frame(end_of_one_frame),
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.Intra16x16_predmode(Intra16x16_predmode),
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.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
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.Intra_chroma_predmode(Intra_chroma_predmode),
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.QPy(QPy),
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.QPc(QPc),
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.i4x4_CbCr(i4x4_CbCr),
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.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
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.slice_beta_offset_div2(slice_beta_offset_div2),
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.CodedBlockPatternLuma(CodedBlockPatternLuma),
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.CodedBlockPatternChroma(CodedBlockPatternChroma),
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.TotalCoeff(TotalCoeff),
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.Is_skip_run_entry(Is_skip_run_entry),
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.skip_mv_calc(skip_mv_calc),
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.disable_DF(disable_DF),
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.coeffLevel_0(coeffLevel_0),
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.coeffLevel_1(coeffLevel_1),
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.coeffLevel_2(coeffLevel_2),
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.coeffLevel_3(coeffLevel_3),
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.coeffLevel_4(coeffLevel_4),
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.coeffLevel_5(coeffLevel_5),
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.coeffLevel_6(coeffLevel_6),
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.coeffLevel_7(coeffLevel_7),
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.coeffLevel_8(coeffLevel_8),
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.coeffLevel_9(coeffLevel_9),
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.coeffLevel_10(coeffLevel_10),
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.coeffLevel_11(coeffLevel_11),
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.coeffLevel_12(coeffLevel_12),
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.coeffLevel_13(coeffLevel_13),
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.coeffLevel_14(coeffLevel_14),
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.coeffLevel_15(coeffLevel_15),
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.mv_is16x16(mv_is16x16),
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.mv_below8x8(mv_below8x8),
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.mvx_CurrMb0(mvx_CurrMb0),
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.mvx_CurrMb1(mvx_CurrMb1),
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.mvx_CurrMb2(mvx_CurrMb2),
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.mvx_CurrMb3(mvx_CurrMb3),
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.mvy_CurrMb0(mvy_CurrMb0),
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.mvy_CurrMb1(mvy_CurrMb1),
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.mvy_CurrMb2(mvy_CurrMb2),
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.mvy_CurrMb3(mvy_CurrMb3),
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.end_of_BS_DEC(end_of_BS_DEC),
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.bs_V0(bs_V0),
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.bs_V1(bs_V1),
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.bs_V2(bs_V2),
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.bs_V3(bs_V3),
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.bs_H0(bs_H0),
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.bs_H1(bs_H1),
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.bs_H2(bs_H2),
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.bs_H3(bs_H3),
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.slice_header_s6(slice_header_s6)
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);
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reconstruction reconstruction (
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.clk(clk),
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.reset_n(reset_n),
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.mb_type_general(mb_type_general),
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.mb_num_h(mb_num_h),
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.mb_num_v(mb_num_v),
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.NextMB_IsSkip(NextMB_IsSkip),
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.LowerMB_IsSkip(LowerMB_IsSkip),
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.slice_data_state(slice_data_state),
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.residual_state(residual_state),
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.cavlc_decoder_state(cavlc_decoder_state),
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.end_of_one_residual_block(end_of_one_residual_block),
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.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
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.end_of_one_frame(end_of_one_frame),
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.Intra16x16_predmode(Intra16x16_predmode),
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.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
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.Intra_chroma_predmode(Intra_chroma_predmode),
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.QPy(QPy),
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.QPc(QPc),
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.i4x4_CbCr(i4x4_CbCr),
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.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
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.slice_beta_offset_div2(slice_beta_offset_div2),
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.CodedBlockPatternLuma(CodedBlockPatternLuma),
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.CodedBlockPatternChroma(CodedBlockPatternChroma),
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.TotalCoeff(TotalCoeff),
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.Is_skip_run_entry(Is_skip_run_entry),
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.skip_mv_calc(skip_mv_calc),
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.disable_DF(disable_DF),
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.coeffLevel_0(coeffLevel_0),
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.coeffLevel_1(coeffLevel_1),
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.coeffLevel_2(coeffLevel_2),
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.coeffLevel_3(coeffLevel_3),
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.coeffLevel_4(coeffLevel_4),
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.coeffLevel_5(coeffLevel_5),
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.coeffLevel_6(coeffLevel_6),
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.coeffLevel_7(coeffLevel_7),
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.coeffLevel_8(coeffLevel_8),
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.coeffLevel_9(coeffLevel_9),
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.coeffLevel_10(coeffLevel_10),
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.coeffLevel_11(coeffLevel_11),
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.coeffLevel_12(coeffLevel_12),
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.coeffLevel_13(coeffLevel_13),
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.coeffLevel_14(coeffLevel_14),
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.coeffLevel_15(coeffLevel_15),
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.mv_is16x16(mv_is16x16),
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.mv_below8x8(mv_below8x8),
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.mvx_CurrMb0(mvx_CurrMb0),
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.mvx_CurrMb1(mvx_CurrMb1),
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.mvx_CurrMb2(mvx_CurrMb2),
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.mvx_CurrMb3(mvx_CurrMb3),
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.mvy_CurrMb0(mvy_CurrMb0),
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.mvy_CurrMb1(mvy_CurrMb1),
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.mvy_CurrMb2(mvy_CurrMb2),
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.mvy_CurrMb3(mvy_CurrMb3),
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.end_of_BS_DEC(end_of_BS_DEC),
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.bs_V0(bs_V0),
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.bs_V1(bs_V1),
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.bs_V2(bs_V2),
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.bs_V3(bs_V3),
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.bs_H0(bs_H0),
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.bs_H1(bs_H1),
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.bs_H2(bs_H2),
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.bs_H3(bs_H3),
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.trigger_CAVLC(trigger_CAVLC),
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.blk4x4_rec_counter(blk4x4_rec_counter),
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.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
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.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
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.end_of_MB_DEC(end_of_MB_DEC),
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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.curr_DC_IsZero(curr_DC_IsZero),
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.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
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.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
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.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
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.ext_frame_RAM0_data(ext_frame_RAM0_data),
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.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
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.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
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.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
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.ext_frame_RAM1_data(ext_frame_RAM1_data),
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.dis_frame_RAM_din(dis_frame_RAM_din)
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);
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endmodule
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