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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : reconstruction.v
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// Generated : Jan 3,2006
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// reconstruction top module,including:
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// rec_gclk_gen
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// hybrid_pipeline_ctrl
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// IQIT
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// Intra_pred_top
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// sum
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// DF_top
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// rec_DF_RAM_ctrl
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// rec_DF_RAM0
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// rec_DF_RAM1
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// ext_RAM_ctrl
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module reconstruction (clk,reset_n,mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip,
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slice_data_state,residual_state,cavlc_decoder_state,
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end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame,
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Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
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QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
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CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,Is_skip_run_entry,
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skip_mv_calc,disable_DF,
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coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
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coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15,
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mv_is16x16,mv_below8x8,
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mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
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end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
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trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,
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end_of_MB_DEC,gclk_end_of_MB_DEC,curr_DC_IsZero,
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ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
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ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data,
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dis_frame_RAM_din
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);
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input clk;
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input reset_n;
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input [3:0] mb_type_general;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input NextMB_IsSkip;
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input LowerMB_IsSkip;
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input [3:0] slice_data_state;
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input [3:0] residual_state;
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input [3:0] cavlc_decoder_state;
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input end_of_one_residual_block;
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input end_of_NonZeroCoeff_CAVLC;
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input end_of_one_frame;
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input [1:0] Intra16x16_predmode;
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input [63:0] Intra4x4_predmode_CurrMb;
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input [1:0] Intra_chroma_predmode;
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input [5:0] QPy;
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input [5:0] QPc;
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input [1:0] i4x4_CbCr;
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input [3:0] slice_alpha_c0_offset_div2;
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input [3:0] slice_beta_offset_div2;
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input [3:0] CodedBlockPatternLuma;
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input [1:0] CodedBlockPatternChroma;
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input [4:0] TotalCoeff;
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input Is_skip_run_entry;
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input skip_mv_calc;
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input disable_DF;
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input [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5;
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input [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
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input [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
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input mv_is16x16;
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input [3:0] mv_below8x8;
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input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
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input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
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input end_of_BS_DEC;
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input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
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input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
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input [31:0] ext_frame_RAM0_data;
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input [31:0] ext_frame_RAM1_data;
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output trigger_CAVLC;
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output [4:0] blk4x4_rec_counter;
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output end_of_DCBlk_IQIT;
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output end_of_one_blk4x4_sum;
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output end_of_MB_DEC;
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output gclk_end_of_MB_DEC;
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output curr_DC_IsZero;
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output ext_frame_RAM0_cs_n;
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output ext_frame_RAM0_wr;
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output [13:0] ext_frame_RAM0_addr;
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output ext_frame_RAM1_cs_n;
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output ext_frame_RAM1_wr;
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output [13:0] ext_frame_RAM1_addr;
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output [31:0] dis_frame_RAM_din;
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wire gclk_endof1resblk;
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wire gclk_1D;
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wire gclk_2D;
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wire gclk_rescale;
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wire gclk_rounding;
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wire gclk_intra_mbAddrA_luma;
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wire gclk_intra_mbAddrA_Cb;
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wire gclk_intra_mbAddrA_Cr;
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wire gclk_intra_mbAddrB;
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wire gclk_intra_mbAddrC_luma;
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wire gclk_intra_mbAddrD;
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wire gclk_seed;
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wire gclk_Inter_ref_rf;
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wire gclk_pred_output;
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wire gclk_blk4x4_sum;
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wire gclk_DF;
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wire gclk_end_of_MB_DEC;
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wire curr_CBPLuma_IsZero;
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wire curr_DC_IsZero;
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wire end_of_ACBlk4x4_IQIT;
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wire end_of_one_blk4x4_intra;
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wire end_of_one_blk4x4_inter;
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wire end_of_one_blk4x4_sum;
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wire end_of_MB_DF;
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wire end_of_MB_DEC;
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wire trigger_blk4x4_intra_pred;
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wire trigger_blk4x4_inter_pred;
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wire trigger_blk4x4_rec_sum;
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wire [15:0] res_luma_DConly;
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wire res_chroma_DConly;
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wire res_AC;
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wire res_DC;
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wire res_luma;
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wire [2:0] OneD_counter;
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wire [2:0] TwoD_counter;
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wire [2:0] rescale_counter;
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wire [2:0] rounding_counter;
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wire [2:0] blk4x4_intra_preload_counter;
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wire [3:0] blk4x4_intra_precompute_counter;
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wire [2:0] blk4x4_intra_calculate_counter;
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wire [5:0] blk4x4_inter_preload_counter;
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wire [3:0] blk4x4_inter_calculate_counter;
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wire [1:0] Inter_chroma2x2_counter;
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wire [4:0] blk4x4_rec_counter;
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wire [2:0] blk4x4_sum_counter;
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wire [4:0] blk4x4_rec_counter_2_raster_order;
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wire [5:0] DF_edge_counter_MR;
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wire [1:0] one_edge_counter_MR;
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wire [1:0] Inter_blk4x4_pred_output_valid;
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wire mv_below8x8_curr;
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wire [3:0] pos_FracL;
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wire [3:0] Intra4x4_predmode;
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wire [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3;
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wire [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7;
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wire [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11;
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wire [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15;
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wire [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out;
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wire [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
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wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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wire [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
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wire [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
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wire [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
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wire [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
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wire [8:0] curr_DC_scaled;
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wire [23:0] sum_right_column_reg;
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wire DF_duration;
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wire gclk_Intra_mbAddrB_RAM;
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wire Intra_mbAddrB_RAM_rd;
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wire Intra_mbAddrB_RAM_wr;
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wire [6:0] Intra_mbAddrB_RAM_rd_addr,Intra_mbAddrB_RAM_wr_addr;
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wire [31:0] Intra_mbAddrB_RAM_din;
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wire [31:0] Intra_mbAddrB_RAM_dout;
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wire gclk_DF_mbAddrA_RF;
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wire DF_mbAddrA_RF_rd;
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wire DF_mbAddrA_RF_wr;
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wire [4:0] DF_mbAddrA_RF_rd_addr;
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wire [4:0] DF_mbAddrA_RF_wr_addr;
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wire [31:0] DF_mbAddrA_RF_din;
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wire [31:0] DF_mbAddrA_RF_dout;
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wire gclk_DF_mbAddrB_RAM;
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wire DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
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wire [8:0] DF_mbAddrB_RAM_addr;
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wire [31:0] DF_mbAddrB_RAM_din;
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wire [31:0] DF_mbAddrB_RAM_dout;
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wire gclk_rec_DF_RAM0,gclk_rec_DF_RAM1;
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wire [31:0] rec_DF_RAM_dout;
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wire rec_DF_RAM0_wr,rec_DF_RAM1_wr;
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wire rec_DF_RAM0_rd,rec_DF_RAM1_rd;
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wire [6:0] rec_DF_RAM0_addr,rec_DF_RAM1_addr;
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wire [31:0] rec_DF_RAM0_din,rec_DF_RAM1_din;
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wire [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout;
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| 200 |
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wire dis_frame_RAM_wr;
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wire [13:0] dis_frame_RAM_wr_addr;
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wire [31:0] dis_frame_RAM_din;
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wire ref_frame_RAM_rd;
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wire [13:0] ref_frame_RAM_rd_addr;
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wire [31:0] ref_frame_RAM_dout;
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rec_gclk_gen rec_gclk_gen (
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.clk(clk),
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.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
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| 211 |
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.OneD_counter(OneD_counter),
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| 212 |
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.TwoD_counter(TwoD_counter),
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| 213 |
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.rescale_counter(rescale_counter),
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| 214 |
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.rounding_counter(rounding_counter),
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| 215 |
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.residual_state(residual_state),
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| 216 |
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.cavlc_decoder_state(cavlc_decoder_state),
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| 217 |
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.gclk_1D(gclk_1D),
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| 218 |
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.gclk_2D(gclk_2D),
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| 219 |
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.gclk_rescale(gclk_rescale),
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| 220 |
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.gclk_rounding(gclk_rounding),
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| 221 |
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.mb_num_h(mb_num_h),
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| 222 |
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.mb_num_v(mb_num_v),
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| 223 |
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.NextMB_IsSkip(NextMB_IsSkip),
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| 224 |
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.mb_type_general(mb_type_general),
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| 225 |
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.blk4x4_rec_counter(blk4x4_rec_counter),
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| 226 |
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.blk4x4_sum_counter(blk4x4_sum_counter),
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| 227 |
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.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
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| 228 |
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.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
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| 229 |
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.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
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| 230 |
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.Intra4x4_predmode(Intra4x4_predmode),
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| 231 |
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.Intra16x16_predmode(Intra16x16_predmode),
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| 232 |
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.Intra_chroma_predmode(Intra_chroma_predmode),
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| 233 |
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.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
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| 234 |
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.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
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| 235 |
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.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
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| 236 |
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.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
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| 237 |
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.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
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| 238 |
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.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
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| 239 |
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.gclk_seed(gclk_seed),
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| 240 |
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.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
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| 241 |
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.gclk_Inter_ref_rf(gclk_Inter_ref_rf),
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| 242 |
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.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
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| 243 |
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.gclk_pred_output(gclk_pred_output),
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| 244 |
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.gclk_blk4x4_sum(gclk_blk4x4_sum),
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| 245 |
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.end_of_MB_DEC(end_of_MB_DEC),
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| 246 |
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.end_of_BS_DEC(end_of_BS_DEC),
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| 247 |
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.DF_duration(DF_duration),
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| 248 |
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.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
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| 249 |
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.gclk_DF(gclk_DF),
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| 250 |
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.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
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| 251 |
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.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
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| 252 |
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.gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM),
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| 253 |
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.rec_DF_RAM0_cs_n(rec_DF_RAM0_cs_n),
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| 254 |
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.gclk_rec_DF_RAM0(gclk_rec_DF_RAM0),
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| 255 |
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.rec_DF_RAM1_cs_n(rec_DF_RAM1_cs_n),
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| 256 |
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.gclk_rec_DF_RAM1(gclk_rec_DF_RAM1),
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| 257 |
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.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
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| 258 |
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.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
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| 259 |
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.gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF),
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| 260 |
|
|
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
| 261 |
|
|
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
| 262 |
|
|
.gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM)
|
| 263 |
|
|
);
|
| 264 |
|
|
hybrid_pipeline_ctrl hybrid_pipeline_ctrl (
|
| 265 |
|
|
.clk(clk),
|
| 266 |
|
|
.reset_n(reset_n),
|
| 267 |
|
|
.mb_num_h(mb_num_h),
|
| 268 |
|
|
.mb_num_v(mb_num_v),
|
| 269 |
|
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
| 270 |
|
|
.CodedBlockPatternLuma(CodedBlockPatternLuma),
|
| 271 |
|
|
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
| 272 |
|
|
.mb_type_general(mb_type_general),
|
| 273 |
|
|
.slice_data_state(slice_data_state),
|
| 274 |
|
|
.residual_state(residual_state),
|
| 275 |
|
|
.TotalCoeff(TotalCoeff),
|
| 276 |
|
|
.Is_skip_run_entry(Is_skip_run_entry),
|
| 277 |
|
|
.skip_mv_calc(skip_mv_calc),
|
| 278 |
|
|
.end_of_one_residual_block(end_of_one_residual_block),
|
| 279 |
|
|
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
|
| 280 |
|
|
.end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT),
|
| 281 |
|
|
.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
|
| 282 |
|
|
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter),
|
| 283 |
|
|
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
| 284 |
|
|
.end_of_MB_DF(end_of_MB_DF),
|
| 285 |
|
|
.disable_DF(disable_DF),
|
| 286 |
|
|
|
| 287 |
|
|
.curr_CBPLuma_IsZero(curr_CBPLuma_IsZero),
|
| 288 |
|
|
.end_of_MB_DEC(end_of_MB_DEC),
|
| 289 |
|
|
.trigger_CAVLC(trigger_CAVLC),
|
| 290 |
|
|
.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
|
| 291 |
|
|
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred),
|
| 292 |
|
|
.trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum)
|
| 293 |
|
|
);
|
| 294 |
|
|
IQIT IQIT (
|
| 295 |
|
|
.clk(clk),
|
| 296 |
|
|
.reset_n(reset_n),
|
| 297 |
|
|
.TotalCoeff(TotalCoeff),
|
| 298 |
|
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
| 299 |
|
|
.gclk_1D(gclk_1D),
|
| 300 |
|
|
.gclk_2D(gclk_2D),
|
| 301 |
|
|
.gclk_rescale(gclk_rescale),
|
| 302 |
|
|
.gclk_rounding(gclk_rounding),
|
| 303 |
|
|
.residual_state(residual_state),
|
| 304 |
|
|
.cavlc_decoder_state(cavlc_decoder_state),
|
| 305 |
|
|
.end_of_one_residual_block(end_of_one_residual_block),
|
| 306 |
|
|
.end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC),
|
| 307 |
|
|
.QPy(QPy),
|
| 308 |
|
|
.QPc(QPc),
|
| 309 |
|
|
.i4x4_CbCr(i4x4_CbCr),
|
| 310 |
|
|
.coeffLevel_ext_0({{7{coeffLevel_0[8]}},coeffLevel_0}),
|
| 311 |
|
|
.coeffLevel_ext_1({{7{coeffLevel_1[8]}},coeffLevel_1}),
|
| 312 |
|
|
.coeffLevel_ext_2({{7{coeffLevel_2[8]}},coeffLevel_2}),
|
| 313 |
|
|
.coeffLevel_ext_3({{7{coeffLevel_3[8]}},coeffLevel_3}),
|
| 314 |
|
|
.coeffLevel_ext_4({{7{coeffLevel_4[8]}},coeffLevel_4}),
|
| 315 |
|
|
.coeffLevel_ext_5({{7{coeffLevel_5[8]}},coeffLevel_5}),
|
| 316 |
|
|
.coeffLevel_ext_6({{7{coeffLevel_6[8]}},coeffLevel_6}),
|
| 317 |
|
|
.coeffLevel_ext_7({{7{coeffLevel_7[8]}},coeffLevel_7}),
|
| 318 |
|
|
.coeffLevel_ext_8({{7{coeffLevel_8[8]}},coeffLevel_8}),
|
| 319 |
|
|
.coeffLevel_ext_9({{7{coeffLevel_9[8]}},coeffLevel_9}),
|
| 320 |
|
|
.coeffLevel_ext_10({{7{coeffLevel_10[8]}},coeffLevel_10}),
|
| 321 |
|
|
.coeffLevel_ext_11({{7{coeffLevel_11[8]}},coeffLevel_11}),
|
| 322 |
|
|
.coeffLevel_ext_12({{7{coeffLevel_12[8]}},coeffLevel_12}),
|
| 323 |
|
|
.coeffLevel_ext_13({{7{coeffLevel_13[8]}},coeffLevel_13}),
|
| 324 |
|
|
.coeffLevel_ext_14({{7{coeffLevel_14[8]}},coeffLevel_14}),
|
| 325 |
|
|
.coeffLevel_ext_15({{7{coeffLevel_15[8]}},coeffLevel_15}),
|
| 326 |
|
|
|
| 327 |
|
|
.OneD_counter(OneD_counter),
|
| 328 |
|
|
.TwoD_counter(TwoD_counter),
|
| 329 |
|
|
.rescale_counter(rescale_counter),
|
| 330 |
|
|
.rounding_counter(rounding_counter),
|
| 331 |
|
|
.curr_DC_IsZero(curr_DC_IsZero),
|
| 332 |
|
|
.curr_DC_scaled(curr_DC_scaled),
|
| 333 |
|
|
.rounding_output_0(IQIT_output_0),
|
| 334 |
|
|
.rounding_output_1(IQIT_output_1),
|
| 335 |
|
|
.rounding_output_2(IQIT_output_2),
|
| 336 |
|
|
.rounding_output_3(IQIT_output_3),
|
| 337 |
|
|
.rounding_output_4(IQIT_output_4),
|
| 338 |
|
|
.rounding_output_5(IQIT_output_5),
|
| 339 |
|
|
.rounding_output_6(IQIT_output_6),
|
| 340 |
|
|
.rounding_output_7(IQIT_output_7),
|
| 341 |
|
|
.rounding_output_8(IQIT_output_8),
|
| 342 |
|
|
.rounding_output_9(IQIT_output_9),
|
| 343 |
|
|
.rounding_output_10(IQIT_output_10),
|
| 344 |
|
|
.rounding_output_11(IQIT_output_11),
|
| 345 |
|
|
.rounding_output_12(IQIT_output_12),
|
| 346 |
|
|
.rounding_output_13(IQIT_output_13),
|
| 347 |
|
|
.rounding_output_14(IQIT_output_14),
|
| 348 |
|
|
.rounding_output_15(IQIT_output_15),
|
| 349 |
|
|
.end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT),
|
| 350 |
|
|
.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT)
|
| 351 |
|
|
);
|
| 352 |
|
|
Intra_pred_top Intra_pred_top (
|
| 353 |
|
|
.clk(clk),
|
| 354 |
|
|
.reset_n(reset_n),
|
| 355 |
|
|
.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
|
| 356 |
|
|
.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
|
| 357 |
|
|
.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
|
| 358 |
|
|
.gclk_intra_mbAddrB(gclk_intra_mbAddrB),
|
| 359 |
|
|
.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),
|
| 360 |
|
|
.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
|
| 361 |
|
|
.gclk_seed(gclk_seed),
|
| 362 |
|
|
.gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM),
|
| 363 |
|
|
.mb_num_h(mb_num_h),
|
| 364 |
|
|
.mb_num_v(mb_num_v),
|
| 365 |
|
|
.mb_type_general(mb_type_general),
|
| 366 |
|
|
.NextMB_IsSkip(NextMB_IsSkip),
|
| 367 |
|
|
.Intra16x16_predmode(Intra16x16_predmode),
|
| 368 |
|
|
.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
|
| 369 |
|
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
| 370 |
|
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
| 371 |
|
|
.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
|
| 372 |
|
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
| 373 |
|
|
.sum_right_column_reg(sum_right_column_reg),
|
| 374 |
|
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
| 375 |
|
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
| 376 |
|
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
| 377 |
|
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
| 378 |
|
|
.blk4x4_pred_output0(blk4x4_pred_output0),
|
| 379 |
|
|
.blk4x4_pred_output1(blk4x4_pred_output1),
|
| 380 |
|
|
.blk4x4_pred_output2(blk4x4_pred_output2),
|
| 381 |
|
|
.blk4x4_pred_output4(blk4x4_pred_output4),
|
| 382 |
|
|
.blk4x4_pred_output5(blk4x4_pred_output5),
|
| 383 |
|
|
.blk4x4_pred_output6(blk4x4_pred_output6),
|
| 384 |
|
|
.blk4x4_pred_output8(blk4x4_pred_output8),
|
| 385 |
|
|
.blk4x4_pred_output9(blk4x4_pred_output9),
|
| 386 |
|
|
.blk4x4_pred_output10(blk4x4_pred_output10),
|
| 387 |
|
|
.blk4x4_pred_output12(blk4x4_pred_output12),
|
| 388 |
|
|
.blk4x4_pred_output13(blk4x4_pred_output13),
|
| 389 |
|
|
.blk4x4_pred_output14(blk4x4_pred_output14),
|
| 390 |
|
|
.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
|
| 391 |
|
|
.Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
| 392 |
|
|
.Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din),
|
| 393 |
|
|
|
| 394 |
|
|
.PE0_out(Intra_pred_PE0_out),
|
| 395 |
|
|
.PE1_out(Intra_pred_PE1_out),
|
| 396 |
|
|
.PE2_out(Intra_pred_PE2_out),
|
| 397 |
|
|
.PE3_out(Intra_pred_PE3_out),
|
| 398 |
|
|
.Intra4x4_predmode(Intra4x4_predmode),
|
| 399 |
|
|
.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
|
| 400 |
|
|
.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
|
| 401 |
|
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
| 402 |
|
|
.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
|
| 403 |
|
|
.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd)
|
| 404 |
|
|
);
|
| 405 |
|
|
Inter_pred_top Inter_pred_top (
|
| 406 |
|
|
.clk(clk),
|
| 407 |
|
|
.gclk_Inter_ref_rf(gclk_Inter_ref_rf),
|
| 408 |
|
|
.reset_n(reset_n),
|
| 409 |
|
|
.mb_num_h(mb_num_h),
|
| 410 |
|
|
.mb_num_v(mb_num_v),
|
| 411 |
|
|
.trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred),
|
| 412 |
|
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
| 413 |
|
|
.mb_type_general_bit3(mb_type_general[3]),
|
| 414 |
|
|
.mv_is16x16(mv_is16x16),
|
| 415 |
|
|
.mv_below8x8(mv_below8x8),
|
| 416 |
|
|
.mvx_CurrMb0(mvx_CurrMb0),
|
| 417 |
|
|
.mvx_CurrMb1(mvx_CurrMb1),
|
| 418 |
|
|
.mvx_CurrMb2(mvx_CurrMb2),
|
| 419 |
|
|
.mvx_CurrMb3(mvx_CurrMb3),
|
| 420 |
|
|
.mvy_CurrMb0(mvy_CurrMb0),
|
| 421 |
|
|
.mvy_CurrMb1(mvy_CurrMb1),
|
| 422 |
|
|
.mvy_CurrMb2(mvy_CurrMb2),
|
| 423 |
|
|
.mvy_CurrMb3(mvy_CurrMb3),
|
| 424 |
|
|
.ref_frame_RAM_dout(ref_frame_RAM_dout),
|
| 425 |
|
|
|
| 426 |
|
|
.Inter_pred_out0(Inter_pred_out0),
|
| 427 |
|
|
.Inter_pred_out1(Inter_pred_out1),
|
| 428 |
|
|
.Inter_pred_out2(Inter_pred_out2),
|
| 429 |
|
|
.Inter_pred_out3(Inter_pred_out3),
|
| 430 |
|
|
.blk4x4_inter_preload_counter(blk4x4_inter_preload_counter),
|
| 431 |
|
|
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
| 432 |
|
|
.Inter_chroma2x2_counter(Inter_chroma2x2_counter),
|
| 433 |
|
|
.mv_below8x8_curr(mv_below8x8_curr),
|
| 434 |
|
|
.pos_FracL(pos_FracL),
|
| 435 |
|
|
.end_of_one_blk4x4_inter(end_of_one_blk4x4_inter),
|
| 436 |
|
|
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
| 437 |
|
|
.ref_frame_RAM_rd(ref_frame_RAM_rd),
|
| 438 |
|
|
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr)
|
| 439 |
|
|
);
|
| 440 |
|
|
sum sum (
|
| 441 |
|
|
.clk(clk),
|
| 442 |
|
|
.reset_n(reset_n),
|
| 443 |
|
|
.slice_data_state(slice_data_state),
|
| 444 |
|
|
.residual_state(residual_state),
|
| 445 |
|
|
.TotalCoeff(TotalCoeff),
|
| 446 |
|
|
.curr_CBPLuma_IsZero(curr_CBPLuma_IsZero),
|
| 447 |
|
|
.CodedBlockPatternChroma(CodedBlockPatternChroma),
|
| 448 |
|
|
.curr_DC_IsZero(curr_DC_IsZero),
|
| 449 |
|
|
.curr_DC_scaled(curr_DC_scaled),
|
| 450 |
|
|
.gclk_pred_output(gclk_pred_output),
|
| 451 |
|
|
.gclk_blk4x4_sum(gclk_blk4x4_sum),
|
| 452 |
|
|
.trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum),
|
| 453 |
|
|
.IQIT_output_0(IQIT_output_0),
|
| 454 |
|
|
.IQIT_output_1(IQIT_output_1),
|
| 455 |
|
|
.IQIT_output_2(IQIT_output_2),
|
| 456 |
|
|
.IQIT_output_3(IQIT_output_3),
|
| 457 |
|
|
.IQIT_output_4(IQIT_output_4),
|
| 458 |
|
|
.IQIT_output_5(IQIT_output_5),
|
| 459 |
|
|
.IQIT_output_6(IQIT_output_6),
|
| 460 |
|
|
.IQIT_output_7(IQIT_output_7),
|
| 461 |
|
|
.IQIT_output_8(IQIT_output_8),
|
| 462 |
|
|
.IQIT_output_9(IQIT_output_9),
|
| 463 |
|
|
.IQIT_output_10(IQIT_output_10),
|
| 464 |
|
|
.IQIT_output_11(IQIT_output_11),
|
| 465 |
|
|
.IQIT_output_12(IQIT_output_12),
|
| 466 |
|
|
.IQIT_output_13(IQIT_output_13),
|
| 467 |
|
|
.IQIT_output_14(IQIT_output_14),
|
| 468 |
|
|
.IQIT_output_15(IQIT_output_15),
|
| 469 |
|
|
.mb_type_general(mb_type_general),
|
| 470 |
|
|
.Intra4x4_predmode(Intra4x4_predmode),
|
| 471 |
|
|
.Intra16x16_predmode(Intra16x16_predmode),
|
| 472 |
|
|
.Intra_chroma_predmode(Intra_chroma_predmode),
|
| 473 |
|
|
.Intra_pred_PE0_out(Intra_pred_PE0_out),
|
| 474 |
|
|
.Intra_pred_PE1_out(Intra_pred_PE1_out),
|
| 475 |
|
|
.Intra_pred_PE2_out(Intra_pred_PE2_out),
|
| 476 |
|
|
.Intra_pred_PE3_out(Intra_pred_PE3_out),
|
| 477 |
|
|
.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
|
| 478 |
|
|
.Inter_pred_out0(Inter_pred_out0),
|
| 479 |
|
|
.Inter_pred_out1(Inter_pred_out1),
|
| 480 |
|
|
.Inter_pred_out2(Inter_pred_out2),
|
| 481 |
|
|
.Inter_pred_out3(Inter_pred_out3),
|
| 482 |
|
|
.blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter),
|
| 483 |
|
|
.Inter_chroma2x2_counter(Inter_chroma2x2_counter),
|
| 484 |
|
|
.Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid),
|
| 485 |
|
|
.mv_below8x8_curr(mv_below8x8_curr),
|
| 486 |
|
|
.pos_FracL(pos_FracL),
|
| 487 |
|
|
.mb_num_h(mb_num_h),
|
| 488 |
|
|
.mb_num_v(mb_num_v),
|
| 489 |
|
|
.LowerMB_IsSkip(LowerMB_IsSkip),
|
| 490 |
|
|
|
| 491 |
|
|
.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
|
| 492 |
|
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
| 493 |
|
|
.blk4x4_rec_counter(blk4x4_rec_counter),
|
| 494 |
|
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
| 495 |
|
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
| 496 |
|
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
| 497 |
|
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
| 498 |
|
|
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
| 499 |
|
|
.sum_right_column_reg(sum_right_column_reg),
|
| 500 |
|
|
.blk4x4_pred_output0(blk4x4_pred_output0),
|
| 501 |
|
|
.blk4x4_pred_output1(blk4x4_pred_output1),
|
| 502 |
|
|
.blk4x4_pred_output2(blk4x4_pred_output2),
|
| 503 |
|
|
.blk4x4_pred_output4(blk4x4_pred_output4),
|
| 504 |
|
|
.blk4x4_pred_output5(blk4x4_pred_output5),
|
| 505 |
|
|
.blk4x4_pred_output6(blk4x4_pred_output6),
|
| 506 |
|
|
.blk4x4_pred_output8(blk4x4_pred_output8),
|
| 507 |
|
|
.blk4x4_pred_output9(blk4x4_pred_output9),
|
| 508 |
|
|
.blk4x4_pred_output10(blk4x4_pred_output10),
|
| 509 |
|
|
.blk4x4_pred_output12(blk4x4_pred_output12),
|
| 510 |
|
|
.blk4x4_pred_output13(blk4x4_pred_output13),
|
| 511 |
|
|
.blk4x4_pred_output14(blk4x4_pred_output14),
|
| 512 |
|
|
.Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr),
|
| 513 |
|
|
.Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr),
|
| 514 |
|
|
.Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din)
|
| 515 |
|
|
);
|
| 516 |
|
|
DF_top DF_top (
|
| 517 |
|
|
.clk(clk),
|
| 518 |
|
|
.reset_n(reset_n),
|
| 519 |
|
|
.gclk_DF(gclk_DF),
|
| 520 |
|
|
.gclk_end_of_MB_DEC(gclk_end_of_MB_DEC),
|
| 521 |
|
|
.gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF),
|
| 522 |
|
|
.gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM),
|
| 523 |
|
|
.end_of_BS_DEC(end_of_BS_DEC),
|
| 524 |
|
|
.disable_DF(disable_DF),
|
| 525 |
|
|
.mb_num_h(mb_num_h),
|
| 526 |
|
|
.mb_num_v(mb_num_v),
|
| 527 |
|
|
.bs_V0(bs_V0),
|
| 528 |
|
|
.bs_V1(bs_V1),
|
| 529 |
|
|
.bs_V2(bs_V2),
|
| 530 |
|
|
.bs_V3(bs_V3),
|
| 531 |
|
|
.bs_H0(bs_H0),
|
| 532 |
|
|
.bs_H1(bs_H1),
|
| 533 |
|
|
.bs_H2(bs_H2),
|
| 534 |
|
|
.bs_H3(bs_H3),
|
| 535 |
|
|
.QPy(QPy),
|
| 536 |
|
|
.QPc(QPc),
|
| 537 |
|
|
.slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2),
|
| 538 |
|
|
.slice_beta_offset_div2(slice_beta_offset_div2),
|
| 539 |
|
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
| 540 |
|
|
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
| 541 |
|
|
.rec_DF_RAM_dout(rec_DF_RAM_dout),
|
| 542 |
|
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
| 543 |
|
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
| 544 |
|
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
| 545 |
|
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
| 546 |
|
|
|
| 547 |
|
|
.DF_duration(DF_duration),
|
| 548 |
|
|
.end_of_MB_DF(end_of_MB_DF),
|
| 549 |
|
|
.DF_edge_counter_MR(DF_edge_counter_MR),
|
| 550 |
|
|
.one_edge_counter_MR(one_edge_counter_MR),
|
| 551 |
|
|
.DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd),
|
| 552 |
|
|
.DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr),
|
| 553 |
|
|
.DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd),
|
| 554 |
|
|
.DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr),
|
| 555 |
|
|
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
| 556 |
|
|
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
| 557 |
|
|
.dis_frame_RAM_din(dis_frame_RAM_din)
|
| 558 |
|
|
);
|
| 559 |
|
|
rec_DF_RAM_ctrl rec_DF_RAM_ctrl (
|
| 560 |
|
|
.clk(clk),
|
| 561 |
|
|
.reset_n(reset_n),
|
| 562 |
|
|
.disable_DF(disable_DF),
|
| 563 |
|
|
.end_of_MB_DEC(end_of_MB_DEC),
|
| 564 |
|
|
.DF_edge_counter_MR(DF_edge_counter_MR),
|
| 565 |
|
|
.one_edge_counter_MR(one_edge_counter_MR),
|
| 566 |
|
|
.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
|
| 567 |
|
|
.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
|
| 568 |
|
|
.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
|
| 569 |
|
|
.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
|
| 570 |
|
|
.blk4x4_sum_counter(blk4x4_sum_counter),
|
| 571 |
|
|
.blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order),
|
| 572 |
|
|
.rec_DF_RAM0_dout(rec_DF_RAM0_dout),
|
| 573 |
|
|
.rec_DF_RAM1_dout(rec_DF_RAM1_dout),
|
| 574 |
|
|
|
| 575 |
|
|
.rec_DF_RAM_dout(rec_DF_RAM_dout),
|
| 576 |
|
|
.rec_DF_RAM0_wr(rec_DF_RAM0_wr),
|
| 577 |
|
|
.rec_DF_RAM0_rd(rec_DF_RAM0_rd),
|
| 578 |
|
|
.rec_DF_RAM0_addr(rec_DF_RAM0_addr),
|
| 579 |
|
|
.rec_DF_RAM0_din(rec_DF_RAM0_din),
|
| 580 |
|
|
.rec_DF_RAM1_wr(rec_DF_RAM1_wr),
|
| 581 |
|
|
.rec_DF_RAM1_rd(rec_DF_RAM1_rd),
|
| 582 |
|
|
.rec_DF_RAM1_addr(rec_DF_RAM1_addr),
|
| 583 |
|
|
.rec_DF_RAM1_din(rec_DF_RAM1_din)
|
| 584 |
|
|
);
|
| 585 |
|
|
ram_sync_1r_sync_1w #(`rec_DF_RAM0_data_width,`rec_DF_RAM0_data_depth)
|
| 586 |
|
|
rec_DF_RAM0 (
|
| 587 |
|
|
.clk(gclk_rec_DF_RAM0),
|
| 588 |
|
|
.rst_n(reset_n),
|
| 589 |
|
|
.wr_n(~rec_DF_RAM0_wr),
|
| 590 |
|
|
.rd_n(~rec_DF_RAM0_rd),
|
| 591 |
|
|
.wr_addr(rec_DF_RAM0_addr),
|
| 592 |
|
|
.rd_addr(rec_DF_RAM0_addr),
|
| 593 |
|
|
.data_in(rec_DF_RAM0_din),
|
| 594 |
|
|
.data_out(rec_DF_RAM0_dout)
|
| 595 |
|
|
);
|
| 596 |
|
|
ram_sync_1r_sync_1w #(`rec_DF_RAM1_data_width,`rec_DF_RAM1_data_depth)
|
| 597 |
|
|
rec_DF_RAM1 (
|
| 598 |
|
|
.clk(gclk_rec_DF_RAM1),
|
| 599 |
|
|
.rst_n(reset_n),
|
| 600 |
|
|
.wr_n(~rec_DF_RAM1_wr),
|
| 601 |
|
|
.rd_n(~rec_DF_RAM1_rd),
|
| 602 |
|
|
.wr_addr(rec_DF_RAM1_addr),
|
| 603 |
|
|
.rd_addr(rec_DF_RAM1_addr),
|
| 604 |
|
|
.data_in(rec_DF_RAM1_din),
|
| 605 |
|
|
.data_out(rec_DF_RAM1_dout)
|
| 606 |
|
|
);
|
| 607 |
|
|
ext_RAM_ctrl ext_RAM_ctrl(
|
| 608 |
|
|
.clk(clk),
|
| 609 |
|
|
.reset_n(reset_n),
|
| 610 |
|
|
.end_of_one_frame(end_of_one_frame),
|
| 611 |
|
|
.ref_frame_RAM_rd(ref_frame_RAM_rd),
|
| 612 |
|
|
.ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr),
|
| 613 |
|
|
.dis_frame_RAM_wr(dis_frame_RAM_wr),
|
| 614 |
|
|
.dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr),
|
| 615 |
|
|
//.dis_frame_RAM_din(dis_frame_RAM_din),
|
| 616 |
|
|
.ref_frame_RAM_dout(ref_frame_RAM_dout),
|
| 617 |
|
|
.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
|
| 618 |
|
|
.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
|
| 619 |
|
|
.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
|
| 620 |
|
|
.ext_frame_RAM0_data(ext_frame_RAM0_data),
|
| 621 |
|
|
.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
|
| 622 |
|
|
.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
|
| 623 |
|
|
.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
|
| 624 |
|
|
.ext_frame_RAM1_data(ext_frame_RAM1_data)
|
| 625 |
|
|
);
|
| 626 |
|
|
endmodule
|
