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[/] [oc_axi_bfm/] [trunk/] [new_component.v] - Blame information for rev 2

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// new_component.v
 
// This file was auto-generated as a prototype implementation of a module
// created in component editor.  It ties off all outputs to ground and
// ignores all inputs.  It needs to be edited to make it do something
// useful.
// 
// This file will not be automatically regenerated.  You should check it in
// to your version control system if you want to keep it.
 
`timescale 1 ps / 1 ps
module new_component (
                input  wire        clock_clk,        //   clock.clk
                output wire [31:0] axm_m0_awaddr,    //  axm_m0.awaddr
                output wire [2:0]  axm_m0_awprot,    //        .awprot
                output wire        axm_m0_awvalid,   //        .awvalid
                input  wire        axm_m0_awready,   //        .awready
                output wire [31:0] axm_m0_wdata,     //        .wdata
                output wire        axm_m0_wlast,     //        .wlast
                output wire        axm_m0_wvalid,    //        .wvalid
                input  wire        axm_m0_wready,    //        .wready
                input  wire        axm_m0_bvalid,    //        .bvalid
                output wire        axm_m0_bready,    //        .bready
                output wire [31:0] axm_m0_araddr,    //        .araddr
                output wire [2:0]  axm_m0_arprot,    //        .arprot
                output wire        axm_m0_arvalid,   //        .arvalid
                input  wire        axm_m0_arready,   //        .arready
                input  wire [31:0] axm_m0_rdata,     //        .rdata
                input  wire        axm_m0_rvalid,    //        .rvalid
                output wire        axm_m0_rready,    //        .rready
                input  wire [31:0] addr,             //  driver.new_signal
                output wire [31:0] r_data,           //        .new_signal_1
                input  wire        transaction_type, //        .new_signal_2
                input  wire [31:0] w_data,           //        .new_signal_3
                output wire        done,             //        .new_signal_4
                input  wire        start,            //        .new_signal_5
                input  wire        reset_reset       // reset_1.reset
        );
 
  parameter IDLE=0, READ=1, WRITE=2;
  parameter N_AW_W=0, AW_NW=1, NAW_W=2, B_WAIT=3 ;
  parameter R_AR=0, R_R=1, R_RSP=2;
 
  reg [1:0] state;
  reg [1:0] write_state;
  reg [1:0] read_state;
 
  reg done_r;
  reg [31:0] r_data_r;
 
  reg [31:0] axm_m0_awaddr_r  ;
  reg        axm_m0_awvalid_r ;
  reg [31:0] axm_m0_wdata_r   ;
  reg        axm_m0_wvalid_r  ;
  reg        axm_m0_bready_r  ;
  reg [31:0] axm_m0_araddr_r  ;
  reg        axm_m0_arvalid_r ;
  reg        axm_m0_rready_r  ;
  reg        axm_m0_wlast_r   ;
  reg [2:0]  axm_m0_awprot_r  ;
 
  assign done           = done_r          ;
  assign axm_m0_awaddr  = axm_m0_awaddr_r ;
  assign axm_m0_awvalid = axm_m0_awvalid_r;
  assign axm_m0_wdata   = axm_m0_wdata_r  ;
  assign axm_m0_wvalid  = axm_m0_wvalid_r ;
  assign axm_m0_bready  = axm_m0_bready_r ;
  assign axm_m0_arvalid = axm_m0_arvalid_r;
  assign axm_m0_araddr  = axm_m0_araddr_r ;
  assign axm_m0_rready  = axm_m0_rready_r ;
  assign axm_m0_wlast   = axm_m0_wlast_r  ;
  assign axm_m0_awprot  = axm_m0_awprot_r ;
  assign r_data         = r_data_r        ;
 
  initial
  begin
    state = IDLE;
    done_r = 0;
    write_state = 0;
    done_r           = '0;
    axm_m0_awaddr_r  = '0;
    axm_m0_awvalid_r = '0;
    axm_m0_wdata_r   = '0;
    axm_m0_wvalid_r  = '0;
    axm_m0_bready_r  = '0;
    axm_m0_arvalid_r = '0;
    axm_m0_araddr_r  = '0;
    axm_m0_rready_r  = '0;
    axm_m0_wlast_r   = '0;
    axm_m0_awprot_r  = '0;
 
  end
 
  always @(posedge clock_clk)
  begin
    if(reset_reset)
    begin
      done_r <= 0;
    end
    else
    begin
      case(state)
        IDLE:
        begin
          if(done_r)
          begin
            done_r <= 1'b0;
          end
 
          if(start)
          begin
            done_r <= 1'b0;
            if(transaction_type)
            begin
              axm_m0_arvalid_r <= 1'b1;
              axm_m0_araddr_r  <= addr;
              state            <= READ;
              read_state       <= R_AR;
            end
            else
            begin
              axm_m0_awaddr_r   <= addr;
              axm_m0_awvalid_r  <= 1'b1;
              axm_m0_wdata_r    <= w_data;
              axm_m0_wvalid_r   <= 1'b1;
              axm_m0_wlast_r    <= 1'b1;
              axm_m0_awprot_r   <= 3'b000;
              state             <= WRITE;
              write_state       <= N_AW_W;
            end
          end
        end
        READ:
        begin
          case(read_state)
            R_AR:
            begin
              if(axm_m0_arvalid & axm_m0_arready)
              begin
                read_state       <= R_R;
                axm_m0_arvalid_r <= 1'b0;
                axm_m0_rready_r  <= 1'b1;
              end
            end
            R_R:
            begin
              if(axm_m0_rready & axm_m0_rvalid)
              begin
                read_state      <= R_RSP;
                r_data_r        <= axm_m0_rdata;
                axm_m0_rready_r <= 1'b0;
              end
            end
            R_RSP:
            begin
              done_r <= 1'b1;
              state             <= IDLE;
            end
          endcase
        end
        WRITE:
        begin
          case(write_state)
            N_AW_W:
            begin
              if(axm_m0_awvalid & axm_m0_awready & axm_m0_wvalid & axm_m0_wready)
              begin
                axm_m0_awvalid_r <= 1'b0;
                axm_m0_wvalid_r <= 1'b0;
                axm_m0_bready_r <= 1'b1;
                write_state <= B_WAIT;
              end
              else if(axm_m0_awvalid & axm_m0_awready)
              begin
                axm_m0_awvalid_r <= 1'b0;
                write_state <= AW_NW;
              end
              else if(axm_m0_wvalid & axm_m0_wready) //Not sure if this can actually happen
              begin
                axm_m0_wvalid_r <= 1'b0;
                write_state <= NAW_W;
              end
            end
            AW_NW:
            begin
                if(axm_m0_wvalid & axm_m0_wready)
                begin
                  axm_m0_wvalid_r <= 1'b0;
                  axm_m0_bready_r <= 1'b1;
                  write_state <= B_WAIT;
                end
            end
            NAW_W:
            begin
              if(axm_m0_awvalid & axm_m0_awready)
              begin
                axm_m0_awvalid_r <= 1'b0;
                axm_m0_bready_r <= 1'b1;
                write_state <= B_WAIT;
              end
            end
            B_WAIT:
            begin
              if(axm_m0_bvalid & axm_m0_bready)
              begin
                state <= IDLE;
                done_r <= 1'b1;
                axm_m0_bready_r <= 1'b0;
              end
            end
          endcase
        end
      endcase
    end
  end
 
 
 
endmodule

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[/] [oc_axi_bfm/] [trunk/] [new_component.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	jackfrye11	`// new_component.v`
2
3			`// This file was auto-generated as a prototype implementation of a module`
4			`// created in component editor. It ties off all outputs to ground and`
5			`// ignores all inputs. It needs to be edited to make it do something`
6			`// useful.`
7			`//`
8			`// This file will not be automatically regenerated. You should check it in`
9			`// to your version control system if you want to keep it.`
10
11			`timescale 1 ps / 1 ps
12			`module new_component (`
13			`input wire clock_clk, // clock.clk`
14			`output wire [31:0] axm_m0_awaddr, // axm_m0.awaddr`
15			`output wire [2:0] axm_m0_awprot, // .awprot`
16			`output wire axm_m0_awvalid, // .awvalid`
17			`input wire axm_m0_awready, // .awready`
18			`output wire [31:0] axm_m0_wdata, // .wdata`
19			`output wire axm_m0_wlast, // .wlast`
20			`output wire axm_m0_wvalid, // .wvalid`
21			`input wire axm_m0_wready, // .wready`
22			`input wire axm_m0_bvalid, // .bvalid`
23			`output wire axm_m0_bready, // .bready`
24			`output wire [31:0] axm_m0_araddr, // .araddr`
25			`output wire [2:0] axm_m0_arprot, // .arprot`
26			`output wire axm_m0_arvalid, // .arvalid`
27			`input wire axm_m0_arready, // .arready`
28			`input wire [31:0] axm_m0_rdata, // .rdata`
29			`input wire axm_m0_rvalid, // .rvalid`
30			`output wire axm_m0_rready, // .rready`
31			`input wire [31:0] addr, // driver.new_signal`
32			`output wire [31:0] r_data, // .new_signal_1`
33			`input wire transaction_type, // .new_signal_2`
34			`input wire [31:0] w_data, // .new_signal_3`
35			`output wire done, // .new_signal_4`
36			`input wire start, // .new_signal_5`
37			`input wire reset_reset // reset_1.reset`
38			`);`
39
40			`parameter IDLE=0, READ=1, WRITE=2;`
41			`parameter N_AW_W=0, AW_NW=1, NAW_W=2, B_WAIT=3 ;`
42			`parameter R_AR=0, R_R=1, R_RSP=2;`
43
44			`reg [1:0] state;`
45			`reg [1:0] write_state;`
46			`reg [1:0] read_state;`
47
48			`reg done_r;`
49			`reg [31:0] r_data_r;`
50
51			`reg [31:0] axm_m0_awaddr_r ;`
52			`reg axm_m0_awvalid_r ;`
53			`reg [31:0] axm_m0_wdata_r ;`
54			`reg axm_m0_wvalid_r ;`
55			`reg axm_m0_bready_r ;`
56			`reg [31:0] axm_m0_araddr_r ;`
57			`reg axm_m0_arvalid_r ;`
58			`reg axm_m0_rready_r ;`
59			`reg axm_m0_wlast_r ;`
60			`reg [2:0] axm_m0_awprot_r ;`
61
62			`assign done = done_r ;`
63			`assign axm_m0_awaddr = axm_m0_awaddr_r ;`
64			`assign axm_m0_awvalid = axm_m0_awvalid_r;`
65			`assign axm_m0_wdata = axm_m0_wdata_r ;`
66			`assign axm_m0_wvalid = axm_m0_wvalid_r ;`
67			`assign axm_m0_bready = axm_m0_bready_r ;`
68			`assign axm_m0_arvalid = axm_m0_arvalid_r;`
69			`assign axm_m0_araddr = axm_m0_araddr_r ;`
70			`assign axm_m0_rready = axm_m0_rready_r ;`
71			`assign axm_m0_wlast = axm_m0_wlast_r ;`
72			`assign axm_m0_awprot = axm_m0_awprot_r ;`
73			`assign r_data = r_data_r ;`
74
75			`initial`
76			`begin`
77			`state = IDLE;`
78			`done_r = 0;`
79			`write_state = 0;`
80			`done_r = '0;`
81			`axm_m0_awaddr_r = '0;`
82			`axm_m0_awvalid_r = '0;`
83			`axm_m0_wdata_r = '0;`
84			`axm_m0_wvalid_r = '0;`
85			`axm_m0_bready_r = '0;`
86			`axm_m0_arvalid_r = '0;`
87			`axm_m0_araddr_r = '0;`
88			`axm_m0_rready_r = '0;`
89			`axm_m0_wlast_r = '0;`
90			`axm_m0_awprot_r = '0;`
91
92			`end`
93
94			`always @(posedge clock_clk)`
95			`begin`
96			`if(reset_reset)`
97			`begin`
98			`done_r <= 0;`
99			`end`
100			`else`
101			`begin`
102			`case(state)`
103			`IDLE:`
104			`begin`
105			`if(done_r)`
106			`begin`
107			`done_r <= 1'b0;`
108			`end`
109
110			`if(start)`
111			`begin`
112			`done_r <= 1'b0;`
113			`if(transaction_type)`
114			`begin`
115			`axm_m0_arvalid_r <= 1'b1;`
116			`axm_m0_araddr_r <= addr;`
117			`state <= READ;`
118			`read_state <= R_AR;`
119			`end`
120			`else`
121			`begin`
122			`axm_m0_awaddr_r <= addr;`
123			`axm_m0_awvalid_r <= 1'b1;`
124			`axm_m0_wdata_r <= w_data;`
125			`axm_m0_wvalid_r <= 1'b1;`
126			`axm_m0_wlast_r <= 1'b1;`
127			`axm_m0_awprot_r <= 3'b000;`
128			`state <= WRITE;`
129			`write_state <= N_AW_W;`
130			`end`
131			`end`
132			`end`
133			`READ:`
134			`begin`
135			`case(read_state)`
136			`R_AR:`
137			`begin`
138			`if(axm_m0_arvalid & axm_m0_arready)`
139			`begin`
140			`read_state <= R_R;`
141			`axm_m0_arvalid_r <= 1'b0;`
142			`axm_m0_rready_r <= 1'b1;`
143			`end`
144			`end`
145			`R_R:`
146			`begin`
147			`if(axm_m0_rready & axm_m0_rvalid)`
148			`begin`
149			`read_state <= R_RSP;`
150			`r_data_r <= axm_m0_rdata;`
151			`axm_m0_rready_r <= 1'b0;`
152			`end`
153			`end`
154			`R_RSP:`
155			`begin`
156			`done_r <= 1'b1;`
157			`state <= IDLE;`
158			`end`
159			`endcase`
160			`end`
161			`WRITE:`
162			`begin`
163			`case(write_state)`
164			`N_AW_W:`
165			`begin`
166			`if(axm_m0_awvalid & axm_m0_awready & axm_m0_wvalid & axm_m0_wready)`
167			`begin`
168			`axm_m0_awvalid_r <= 1'b0;`
169			`axm_m0_wvalid_r <= 1'b0;`
170			`axm_m0_bready_r <= 1'b1;`
171			`write_state <= B_WAIT;`
172			`end`
173			`else if(axm_m0_awvalid & axm_m0_awready)`
174			`begin`
175			`axm_m0_awvalid_r <= 1'b0;`
176			`write_state <= AW_NW;`
177			`end`
178			`else if(axm_m0_wvalid & axm_m0_wready) //Not sure if this can actually happen`
179			`begin`
180			`axm_m0_wvalid_r <= 1'b0;`
181			`write_state <= NAW_W;`
182			`end`
183			`end`
184			`AW_NW:`
185			`begin`
186			`if(axm_m0_wvalid & axm_m0_wready)`
187			`begin`
188			`axm_m0_wvalid_r <= 1'b0;`
189			`axm_m0_bready_r <= 1'b1;`
190			`write_state <= B_WAIT;`
191			`end`
192			`end`
193			`NAW_W:`
194			`begin`
195			`if(axm_m0_awvalid & axm_m0_awready)`
196			`begin`
197			`axm_m0_awvalid_r <= 1'b0;`
198			`axm_m0_bready_r <= 1'b1;`
199			`write_state <= B_WAIT;`
200			`end`
201			`end`
202			`B_WAIT:`
203			`begin`
204			`if(axm_m0_bvalid & axm_m0_bready)`
205			`begin`
206			`state <= IDLE;`
207			`done_r <= 1'b1;`
208			`axm_m0_bready_r <= 1'b0;`
209			`end`
210			`end`
211			`endcase`
212			`end`
213			`endcase`
214			`end`
215			`end`
216
217
218
219			`endmodule`