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smjoshua |
//////////////////////////////////////////////////////////////////
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// //
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// OoOPs Core Instruction Cache module //
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// //
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// This file is part of the OoOPs project //
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// http://www.opencores.org/project,oops //
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// //
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// Description: //
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// Top-level module for Instruction Cache block. This includes//
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// the instantiation of the data and tag RAMs as well as the //
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// cache controller logic. //
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// //
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// Author(s): //
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// - Joshua Smith, smjoshua@umich.edu //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2012 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "ooops_defs.v"
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module icache_top (
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input wire clk,
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input wire rst,
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input wire rob_pipe_flush,
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// Coprocessor interface
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input wire cp0_ic_enable,
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// IF interface
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input wire if_ic_req,
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input wire [`ADDR_SZ-1:0] if_ic_fpc,
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input wire [`ADDR_SZ-1:0] r_if_ic_fpc,
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output wire [`INSTR_SZ-1:0] ic_if_data,
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output wire ic_if_data_valid,
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output wire ic_if_cache_hit,
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output wire ic_if_cache_miss,
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output wire ic_if_ready,
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// Memory interface
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output wire ic2bus_req,
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output wire [`ADDR_SZ-1:0] ic2bus_fpc,
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input wire bus2ic_valid,
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input wire [`SYS_BUS_SZ-1:0] bus2ic_data
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);
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// Internal wires
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wire [`IC_SI_SZ-1:0] ic_dataram_addr;
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wire [`IC_LINE_SZ-1:0] ic_dataram_data;
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wire [`IC_LINE_SZ-1:0] ic_dataram_wr_data;
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wire ic_dataram_wren;
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wire [`IC_SI_SZ-1:0] ic_tagram_addr;
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wire [`IC_TAGRAM_SZ-1:0] ic_tagram_data;
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wire [`IC_TAGRAM_SZ-1:0] ic_tagram_wr_data;
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wire ic_tagram_wren;
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// Instantiate IC controller
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icache_ctl icache_ctl0(
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.clk(clk),
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.rst(rst),
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.rob_pipe_flush(rob_pipe_flush),
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.cp0_ic_enable(cp0_ic_enable),
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.if_ic_req(if_ic_req),
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.if_ic_fpc(if_ic_fpc),
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.r_if_ic_fpc(r_if_ic_fpc),
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.ic_if_data(ic_if_data),
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.ic_if_data_valid(ic_if_data_valid),
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.ic_if_ready(ic_if_ready),
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.ic_tagram_data(ic_tagram_data),
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.ic_dataram_data(ic_dataram_data),
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.ic_dataram_wr_data(ic_dataram_wr_data),
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.ic_dataram_addr(ic_dataram_addr),
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.ic_dataram_wren(ic_dataram_wren),
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.ic_tagram_wr_data(ic_tagram_wr_data),
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.ic_tagram_addr(ic_tagram_addr),
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.ic_tagram_wren(ic_tagram_wren),
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.ic2bus_req(ic2bus_req),
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.ic2bus_fpc(ic2bus_fpc),
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.bus2ic_valid(bus2ic_valid),
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.bus2ic_data(bus2ic_data)
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);
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// Instantiate IC data and tag RAMs
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`ifdef USE_IC
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sp_sram #(.DW(`IC_LINE_SZ), .IW(`IC_SI_SZ)) d0 (
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.clk(clk),
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.addr(ic_dataram_addr),
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.wren(ic_dataram_wren),
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.din(ic_dataram_wr_data),
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.dout(ic_dataram_data)
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);
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sp_sram #(.DW(`IC_TAGRAM_SZ), .IW(`IC_SI_SZ)) t0 (
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.clk(clk),
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.addr(ic_tagram_addr),
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.wren(ic_tagram_wren),
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.din(ic_tagram_wr_data),
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.dout(ic_tagram_data)
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);
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`else
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assign ic_dataram_data = {`IC_LINE_SZ{1'b0}};
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assign ic_tagram_data = {`IC_TAGRAM_SZ{1'b0}};
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`endif
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endmodule
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