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smjoshua |
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//////////////////////////////////////////////////////////////////
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// //
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// OoOPs common module library //
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// //
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// This file is part of the OoOPs project //
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// http://www.opencores.org/project,oops //
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// //
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// Description: //
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// Basic library of common blocks such as different types of //
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// flops, etc... //
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// //
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// Author(s): //
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// - Joshua Smith, smjoshua@umich.edu //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2012 Authors and OPENCORES.ORG //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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`include "ooops_defs.v"
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// Regular DFF
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module MDFF #(parameter DW = 1) (
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input wire clk,
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input wire [DW-1:0] din,
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output reg [DW-1:0] dout
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);
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always @(posedge clk)
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dout <= `SD din;
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endmodule
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// Loadable DFF
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module MDFFL #(parameter DW = 1) (
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input wire clk,
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input wire ld,
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input wire [DW-1:0] din,
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output reg [DW-1:0] dout
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);
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always @(posedge clk)
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if (ld) dout <= `SD din;
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endmodule
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// Resetable DFF
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module MDFFR #(parameter DW = 1) (
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input wire clk,
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input wire rst,
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input wire [DW-1:0] rst_din,
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input wire [DW-1:0] din,
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output reg [DW-1:0] dout
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);
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always @(posedge clk)
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if (rst) dout <= `SD rst_din;
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else dout <= `SD din;
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endmodule
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// Loadable, resetable DFF
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module MDFFLR #(parameter DW = 1) (
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input wire clk,
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input wire rst,
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input wire ld,
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input wire [DW-1:0] rst_din,
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input wire [DW-1:0] din,
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output reg [DW-1:0] dout
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);
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always @(posedge clk)
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if (rst) dout <= `SD rst_din;
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else if (ld) dout <= `SD din;
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endmodule
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