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rehnmaak |
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USB 1.1 PHY
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==========
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Status
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------
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This core is done. It was tested with a USB 1.1 core I have written on
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a XESS XCV800 board with a a Philips PDIUSBP11A transceiver.
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I have NOT yet tested it with my USB 2.0 Function IP core.
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Test Bench
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----------
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There is no test bench, period ! As I said above I have tested this core
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in real hardware and it works just fine.
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Documentation
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-------------
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Sorry, there is none. I just don't have the time to write it. I have tried
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to follow the UTMI interface specification from USB 2.0.
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'phy_mode' selects between single ended and differential tx_phy output. See
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Philips ISP 1105 transceiver data sheet for an explanation of it's MODE
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select pin (see Note below).
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Currently this PHY only operates in Full-Speed mode. Required clock frequency
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is 48MHz, from which the 12MHz USB transmit and receive clocks are derived.
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RxError reports the following errors:
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- sync errors
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Could not synchronize to incoming bit stream
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- Bit Stuff Error
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Stuff bit had the wrong value (expected '0' got '1')
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- Byte Error
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Got a EOP (se0) before finished assembling a full byteAll of those errors
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are or'ed together and reported via RxError.
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Note:
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1) "phy_tx_mode" selects the PHY Transmit Mode:
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When phy_tx_mode is '0' the outputs are encoded as:
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txdn, txdp
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1 0 Single Ended '0'
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1 1 Single Ended '0'
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When phy_tx_mode is '1' the outputs are encoded as:
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txdn, txdp
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1 0 Differential Logic '0'
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1 1 Illegal State
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See PHILIPS Transceiver Data Sheet for: ISP1105, ISP1106 and ISP1107
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for more details.
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2) "usb_rst" Indicates a USB Bus Reset (this output is also or'ed with
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the reset input).
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Misc
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----
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The USB 1.1 Phy Project Page is:
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http://www.opencores.org/cores/usb_phy
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To find out more about me (Rudolf Usselmann), please visit:
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http://www.asics.ws
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Directory Structure
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-------------------
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[core_root]
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+-doc Documentation
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+-bench--+ Test Bench
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| +-verilog Verilog Sources
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| +-vhdl VHDL Sources
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+-rtl----+ Core RTL Sources
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| +-verilog Verilog Sources
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| +-vhdl VHDL Sources
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+-sim----+
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| +-rtl_sim---+ Functional verification Directory
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| | +-bin Makefiles/Run Scripts
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| | +-run Working Directory
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| +-gate_sim--+ Functional & Timing Gate Level
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| | Verification Directory
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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+-lint--+ Lint Directory Tree
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| +-bin Makefiles/Run Scripts
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| +-run Working Directory
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| +-log Linter log & result files
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+-syn---+ Synthesis Directory Tree
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| +-bin Synthesis Scripts
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| +-run Working Directory
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| +-log Synthesis log files
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| +-out Synthesis Output
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