Subversion Repositories opb_usblite

#--

#--    opb_usblite - opb_uartlite replacement

#--

#--    opb_usblite is using components from Rudolf Usselmann see

#--    http://www.opencores.org/cores/usb_phy/

#--    and Joris van Rantwijk see http://www.xs4all.nl/~rjoris/fpga/usb.html

#--

#--    Copyright (C) 2010 Ake Rehnman

#--

#--    This program is free software: you can redistribute it and/or modify

#--    it under the terms of the GNU General Public License as published by

#--    the Free Software Foundation, either version 3 of the License, or

#--    (at your option) any later version.

#--

#--    This program is distributed in the hope that it will be useful,

#--    but WITHOUT ANY WARRANTY; without even the implied warranty of

#--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

#--    GNU General Public License for more details.

#--

#--    You should have received a copy of the GNU General Public License

#--    along with this program.  If not, see .

#--

BEGIN opb_usblite

## Peripheral Options

OPTION IPTYPE = PERIPHERAL

OPTION IMP_NETLIST = TRUE

OPTION HDL = VHDL

OPTION IP_GROUP = MICROBLAZE:PPC:USER

## Bus Interfaces

BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog

PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = SOPB

PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = SOPB

PARAMETER C_BASEADDR = 0xffff0000, DT = std_logic_vector(0 to 31), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SOPB

PARAMETER C_HIGHADDR = 0xffff00ff, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SOPB

PARAMETER C_SYSRST = 1, DT = std_logic

PARAMETER C_PHYMODE = 1, DT = std_logic

PARAMETER C_VENDORID = 0x1234, DT = std_logic_vector(15 downto 0)

PARAMETER C_PRODUCTID = 0x5678, DT = std_logic_vector(15 downto 0)

PARAMETER C_VERSIONBCD = 0x0200, DT = std_logic_vector(15 downto 0)

PARAMETER C_SELFPOWERED = false, DT = BOOLEAN

PARAMETER C_RXBUFSIZE_BITS = 10, DT = INTEGER

PARAMETER C_TXBUFSIZE_BITS = 10, DT = INTEGER

## Ports

PORT OPB_Clk = "", DIR = I, SIGIS = CLK, BUS = SOPB

PORT OPB_Rst = OPB_Rst, DIR = I, SIGIS = RST, BUS = SOPB

PORT SYS_Rst = "", DIR = I, SIGIS = RST

PORT USB_Clk = "", DIR = I, SIGIS = CLK

PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:31], BUS = SOPB

PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:3], BUS = SOPB

PORT OPB_RNW = OPB_RNW, DIR = I, BUS = SOPB

PORT OPB_select = OPB_select, DIR = I, BUS = SOPB

PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = SOPB

PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:31], BUS = SOPB

PORT Sl_DBus = Sl_DBus, DIR = O, VEC = [0:31], BUS = SOPB

PORT Sl_errAck = Sl_errAck, DIR = O, BUS = SOPB

PORT Sl_retry = Sl_retry, DIR = O, BUS = SOPB

PORT Sl_toutSup = Sl_toutSup, DIR = O, BUS = SOPB

PORT Sl_xferAck = Sl_xferAck, DIR = O, BUS = SOPB

PORT Interrupt = "", DIR = O, LEVEL = HIGH, SIGIS = INTERRUPT, INTERRUPT_PRIORITY = LOW

PORT txdp = "", DIR = O

PORT txdn = "", DIR = O

PORT txoe = "", DIR = O

PORT rxd = "", DIR = I

PORT rxdp = "", DIR = I

PORT rxdn = "", DIR = I

END