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################################################################################
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##
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## Copyright (C) 2000-2004 ASICS World Services, LTD.
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## www.asics.ws
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## info@asics.ws
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##
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## Author: Rudolf Usselmann
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## rudi@asics.ws
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##
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################################################################################
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BEGIN opb2wb
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## Peripheral Options
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OPTION IPTYPE = BRIDGE
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OPTION IMP_NETLIST = TRUE
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OPTION CORE_STATE = ACTIVE
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OPTION STYLE = MIX
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OPTION HDL = VERILOG
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## Bus Interfaces
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BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE
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## Generics for VHDL or Parameters for Verilog
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PARAMETER C_BASEADDR = 0x80000000, DT = std_logic_vector, BUS = SOPB, ADDRESS = BASE, MIN_SIZE = 0x100
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PARAMETER C_HIGHADDR = 0x800000ff, DT = std_logic_vector, BUS = SOPB, ADDRESS = HIGH
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# Shared Signals
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PORT OPB_Clk = "", DIR = IN, SIGIS = CLK, BUS = SOPB
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PORT SYS_Rst = OPB_Rst, DIR = IN, SIGIS = RST, BUS = SOPB
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# Ports OPB Slave Attachment
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PORT opb_abus = OPB_ABus, DIR = IN, VEC = [0:31], BUS = SOPB
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PORT opb_be = OPB_BE, DIR = IN, VEC = [0:3], BUS = SOPB
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PORT opb_dbus = OPB_DBus, DIR = IN, VEC = [0:31], BUS = SOPB
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PORT opb_rnw = OPB_RNW, DIR = IN, BUS = SOPB
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PORT opb_select = OPB_select, DIR = IN, BUS = SOPB
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PORT opb_seqaddr = OPB_seqAddr, DIR = IN, BUS = SOPB
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PORT sl_dbus = Sl_DBus, DIR = OUT, VEC = [0:31], BUS = SOPB
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PORT sl_errack = Sl_errAck, DIR = OUT, BUS = SOPB
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PORT sl_retry = Sl_retry, DIR = OUT, BUS = SOPB
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PORT sl_toutsup = Sl_toutSup, DIR = OUT, BUS = SOPB
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PORT sl_xferack = Sl_xferAck, DIR = OUT, BUS = SOPB
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# WISHBONE Master Interface
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PORT wb_data_o = "", DIR = OUT, VEC = [31:0]
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PORT wb_data_i = "", DIR = IN, VEC = [31:0]
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PORT wb_addr_o = "", DIR = OUT, VEC = [31:0]
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PORT wb_cyc_o = "", DIR = OUT
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PORT wb_stb_o = "", DIR = OUT
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PORT wb_sel_o = "", DIR = OUT, VEC = [3:0]
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PORT wb_we_o = "", DIR = OUT
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PORT wb_ack_i = "", DIR = IN
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PORT wb_err_i = "", DIR = IN
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PORT wb_rty_i = "", DIR = IN
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END
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