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[/] [opb_wb_wrapper/] [trunk/] [wb2opb_v1_00_a/] [data/] [wb2opb_v2_1_0.mpd] - Blame information for rev 7

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1 7 ocadmin
################################################################################
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##
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## Copyright (C) 2000-2004 ASICS World Services, LTD.
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##                         www.asics.ws
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##                         info@asics.ws
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##
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##  Author: Rudolf Usselmann
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##          rudi@asics.ws
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##
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################################################################################
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BEGIN wb2opb
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## Peripheral Options
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OPTION IPTYPE = BRIDGE
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OPTION IMP_NETLIST = TRUE
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OPTION CORE_STATE = ACTIVE
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OPTION STYLE = MIX
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OPTION HDL = VERILOG
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## Bus Interfaces
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BUS_INTERFACE BUS = MOPB, BUS_STD = OPB, BUS_TYPE = MASTER
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## Shared Signals
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PORT OPB_Clk     = "",          DIR = IN, SIGIS = CLK, BUS = MOPB
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PORT rst         = OPB_Rst,             DIR = IN, BUS = MOPB
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## Ports OPB Master Attachment
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PORT opb_abus    = M_ABus,      DIR = OUT, VEC = [0:31], BUS = MOPB
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PORT opb_be      = M_BE,        DIR = OUT, VEC = [0:3], BUS = MOPB
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PORT opb_dbus    = M_DBus,      DIR = OUT, VEC = [0:31], BUS = MOPB
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PORT opb_rnw     = M_RNW,       DIR = OUT, BUS = MOPB
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PORT opb_select  = M_select,    DIR = OUT, BUS = MOPB
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PORT opb_seqaddr = M_seqAddr,   DIR = OUT, BUS = MOPB
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PORT sl_dbus     = OPB_DBus,    DIR = IN, VEC = [0:31], BUS = MOPB
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PORT sl_errack   = OPB_errAck,  DIR = IN, BUS = MOPB
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PORT sl_retry    = OPB_retry,   DIR = IN, BUS = MOPB
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PORT sl_xferack  = OPB_xferAck, DIR = IN, BUS = MOPB
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PORT opb_req     = M_request,   DIR = OUT, BUS = MOPB
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PORT opb_gnt     = OPB_MGrant,  DIR = IN, BUS = MOPB
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PORT opb_buslock = M_busLock,   DIR = OUT, BUS = MOPB
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## WISHBONE Slave Interface
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PORT wb_data_o = "", DIR = OUT, VEC = [31:0]
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PORT wb_data_i = "", DIR = IN, VEC = [31:0]
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PORT wb_addr_i = "", DIR = IN, VEC = [31:0]
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PORT wb_cyc_i  = "", DIR = IN
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PORT wb_stb_i  = "", DIR = IN
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PORT wb_sel_i  = "", DIR = IN, VEC = [3:0]
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PORT wb_we_i   = "", DIR = IN
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PORT wb_ack_o  = "", DIR = OUT
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PORT wb_err_o  = "", DIR = OUT
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PORT wb_rty_o  = "", DIR = OUT
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END

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