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[/] [opb_wb_wrapper/] [trunk/] [wb2opb_v1_00_a/] [hdl/] [verilog/] [wb2opb_shell.v] - Blame information for rev 7

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1 7 ocadmin
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  WISHBONE to OPB interface wrapper                          ////
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////                                                             ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////                                                             ////
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////  Proprietary and Confidential Information of                ////
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////  ASICS World Services, LTD                                  ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2004 ASICS World Services, LTD.          ////
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////                         www.asics.ws                        ////
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////                         info@asics.ws                       ////
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////                                                             ////
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//// This software is provided under license and contains        ////
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//// proprietary and confidential material which are the         ////
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//// property of ASICS World Services, LTD.                      ////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  $Id:        $
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module wb2opb(  OPB_Clk, rst,
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                // OPB Master Interface (Connect to OPB Slave)
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                opb_abus, opb_be, opb_dbus, opb_rnw, opb_select, opb_seqaddr,
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                sl_dbus, sl_errack, sl_retry, sl_xferack,
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                opb_req, opb_gnt, opb_buslock,
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                // WISHBONE Slave Interface (Connect to WB Master)
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                wb_data_o, wb_data_i, wb_addr_i,
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                wb_cyc_i, wb_stb_i, wb_sel_i, wb_we_i, wb_ack_o, wb_err_o, wb_rty_o
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        );
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// --------------------------------------
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// System IO
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input                   OPB_Clk;
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input                   rst;
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// --------------------------------------
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// OPB Master Interface (Connect to OPB Slave)
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output  [31:0]           opb_abus;
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output  [3:0]            opb_be;
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output  [31:0]           opb_dbus;
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output                  opb_rnw;
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output                  opb_select;
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output                  opb_seqaddr;
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input   [31:0]           sl_dbus;
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input                   sl_errack;
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input                   sl_retry;
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input                   sl_xferack;
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output                  opb_req, opb_buslock;
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input                   opb_gnt;
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// --------------------------------------
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// WISHBONE Slave Interface (Connect to WB Master)
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output  [31:0]           wb_data_o;
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input   [31:0]           wb_data_i;
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input   [31:0]           wb_addr_i;
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input                   wb_cyc_i, wb_stb_i;
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input   [3:0]            wb_sel_i;
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input                   wb_we_i;
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output                  wb_ack_o, wb_err_o, wb_rty_o;
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endmodule

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