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<link id=Main-File rel=Main-File href="../CPU%20Instruction%20Set.htm">
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</head>
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<body link=blue vlink=purple>
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<table border=0 cellpadding=0 cellspacing=0 width=1242 style='border-collapse:
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collapse;table-layout:fixed;width:932pt'>
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<col width=185 style='mso-width-source:userset;mso-width-alt:6765;width:139pt'>
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<col width=103 style='mso-width-source:userset;mso-width-alt:3766;width:77pt'>
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<col class=xl67 width=61 style='mso-width-source:userset;mso-width-alt:2230;
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width:46pt'>
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<col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
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width:670pt'>
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<tr height=35 style='height:26.25pt'>
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<td height=35 width=185 style='height:26.25pt;width:139pt'></td>
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<td width=103 style='width:77pt'></td>
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<td class=xl107 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
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CPU Core Generics</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
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<td class=xl67></td>
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<td class=xl68></td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl69 style='height:15.0pt'>Option</td>
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<td class=xl69>Argument Type</td>
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<td class=xl70>Default</td>
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<td class=xl72 width=893 style='width:670pt'>Description</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Program_Start_Addr</td>
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<td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
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<td class=xl103 style='border-top:none;border-left:none'>x"0000"</td>
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<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
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program counter location</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl73 style='height:15.0pt;border-top:none'>ISR_Start_Addr</td>
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<td class=xl73 style='border-top:none;border-left:none'>16-bit Address</td>
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<td class=xl74 style='border-top:none;border-left:none'>x"FFF0"</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
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the initial location of the interrupt vector table</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Stack_Start_Addr</td>
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<td class=xl76 style='border-top:none;border-left:none'>16-bit Address</td>
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<td class=xl103 style='border-top:none;border-left:none'>x"03FF"</td>
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<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Initial
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location of the CPU Stack - Must be located in accessible RAM</td>
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</tr>
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<tr height=40 style='height:30.0pt'>
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<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Allow_Stack_Address_Move</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
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false, the RSP instruction will reset the stack pointer to
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"Stack_Start_Addr" by default. If true, the RSP instruction will
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either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
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depending on the status of the PSR_GP4 (PSR_S) flag.</td>
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</tr>
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<tr height=80 style='height:60.0pt'>
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<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
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true, indexed instructions such as LDX, LDO, STX, STO will automatically
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increment if an odd register is specified. The effect is similar to a normal
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indexed instruction followed by an UPP instruction on the same register pair.
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For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
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at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
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be incremented by 1. If false, specifying either register in a register pair
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will result in normal behavior.</td>
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</tr>
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<tr height=60 style='height:45.0pt'>
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<td height=60 class=xl73 style='height:45.0pt;border-top:none'>BRK_Implements_WAI</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
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true, the BRK instruction will cause the processor to halt as if an INT
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instruction was executed, but without triggering an interrupt. This is useful
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for pausing the CPU until an interrupt occurs. If false, the BRK instruction
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flushes the pipeline and executes an extended (5-clock) NOP cycle.</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>TRUE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
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bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
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</tr>
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<tr height=40 style='height:30.0pt'>
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<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
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interrupts from initiating an ISR if the I-bit is set, making ISRs
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sequential. This potentially blocks interrupt priority by allowing a lower
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level interrupt to block a higher level interrupt. This can be worked around
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by clearing the I-bit in known interruptable ISRs.</td>
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</tr>
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<tr height=40 style='height:30.0pt'>
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<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
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set, preserves the general purpose flags GP_PSR4 (PSR_S) to GP_PSR7 on ISR
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exit, allowing them to be persistently set by interrupts. The lower four flag
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bits are always restored.</td>
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</tr>
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<tr height=40 style='height:30.0pt'>
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<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td>
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<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
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set to true, enables restrictions on RSP, CLP/STP, and SMSK where they only
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can alter internal registers if the I bit is set. Also initializes the CPU to
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start with the I-bit set. If set to false, there are no restrictions on these
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instructions.</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
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whether the offset calculation for LDO/STO is signed or unsigned. Default
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behavior is signed.</td>
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</tr>
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<tr height=40 style='height:30.0pt'>
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<td height=40 class=xl108 style='height:30.0pt;border-top:none'>Rotate_Ignores_Carry</td>
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<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
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<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>By
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default, the V8 uRISC processor included the carry in rotations, making them
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effectively 9-bit rotations. This generic modifies the ALU such that the
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rotations work as classically defined and do NOT involve, or alter, the carry
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bit.</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
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<td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td>
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<td class=xl74 style='border-top:none;border-left:none'>x"FF"</td>
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<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
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the initial interrupt mask (note that bit 0 is ignored if Enable_NMI is set
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TRUE)</td>
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</tr>
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<tr height=20 style='height:15.0pt'>
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<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
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<td class=xl108 style='border-top:none;border-left:none'>Real</td>
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<td class=xl109 style='border-top:none;border-left:none'>-</td>
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<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
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frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
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</tr>
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<![if supportMisalignedColumns]>
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<tr height=0 style='display:none'>
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<td width=185 style='width:139pt'></td>
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<td width=61 style='width:46pt'></td>
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<td width=893 style='width:670pt'></td>
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</tr>
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<![endif]>
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</table>
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</body>
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</html>
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