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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_hd44780_if.vhd] - Blame information for rev 289

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1 286 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
2
-- All rights reserved.
3
--
4
-- Redistribution and use in source and binary forms, with or without
5
-- modification, are permitted provided that the following conditions are met:
6
--     * Redistributions of source code must retain the above copyright
7
--       notice, this list of conditions and the following disclaimer.
8
--     * Redistributions in binary form must reproduce the above copyright
9
--       notice, this list of conditions and the following disclaimer in the
10
--       documentation and/or other materials provided with the distribution,
11
--       where applicable (as part of a user interface, debugging port, etc.)
12
--
13
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
--
24
-- VHDL Entity: o8_hd44780_if
25
-- Description: Provides low-level access to "standard" character LCDs using
26
--               the ST/HD44780(U) control ASIC wired in either 8-bit or
27
--               reduced (4-bit) mode.
28
--              All low-level timing of the control signals are handled by this
29
--               module, allowing client firmware to use a simple register
30
--               interface to program the LCD panel.
31 288 jshamlet
-- Note that this module assumes that the R/Wn line has been tied LOW
32 286 jshamlet
--
33
-- Register Map
34
-- Address  Function
35
-- Offset  Bitfield Description                        Read/Write
36
-- 0x0     AAAAAAAA LCD Register Write                 (Read-Write*)
37
-- 0x1     AAAAAAAA LCD Data Write                     (Read-Write*)
38
-- 0x2     AAAAAAAA LCD Rearm Init Timer               (Read-Write*)
39
-- 0x3     AAAAAAAA LCD Backlight                      (Read-Write)
40
--
41
-- Note: Reading 0x0, 0x1 or 0x2 will report whether the panel is ready or not
42
--        in the MSB (bit 7). 0x00 = NOT READY / 0x80 = READY
43
--
44
--------------------------------------------------------------------------------
45
-- LCD Controller
46
--------------------------------------------------------------------------------
47
--
48
-- LCD Instruction Set (Hitachi Compatible)
49
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
50
------------------------------------------------------------------------
51
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1.52mS
52
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x | 1.52mS
53
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |   37uS
54
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |   37uS
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-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |   37uS
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-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | x | x |   37uS
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-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |   37uS
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-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |   37uS
59
 
60
-- LCD Instruction Set (New Haven)
61
-- Instruction             RS  RW  D7  D6  D5  D4  D3  D2  D1  D0  Time
62
------------------------------------------------------------------------
63
-- Clear Display         | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2.00mS
64
-- Return Home           | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | x |  600uS
65
-- Entry Mode            | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ID| S |  600uS
66
-- Display Pwr           | 0 | 0 | 0 | 0 | 0 | 0 | 1 | D | C | B |  600uS
67
-- Cursor/Display Shift  | 0 | 0 | 0 | 0 | 0 | 1 | SC| RL| x | x |  600uS
68
-- Function Set          | 0 | 0 | 0 | 0 | 1 | DL| N | F | T | T |  600uS
69
-- Set CGRAM Address     | 0 | 0 | 0 | 1 | A | A | A | A | A | A |  600uS
70
-- Set DDRAM Address     | 0 | 0 | 1 | A | A | A | A | A | A | A |  600uS
71
--
72
-- Notes:
73
-- ID = Increment/Decrement DDRAM Address (1 = increment, 0 = decrement)
74
-- S  = Shift Enable (1 = Shift display according to ID, 0 = Don't shift)
75
-- D  = Display On/Off (1 = on, 0 = off)
76
-- C  = Cursor On/Off  (1 = on, 0 = off)
77
-- B  = Cursor Blink   (1 = block cursor, 0 = underline cursor)
78
-- SC / RL = Shift Cursor/Display Right/Left (see data sheet - not needed for init)
79
-- F  = Font (0 = 5x8, 1 = 5x11) Ignored on 2-line displays (N = 1)
80
-- N  = Number of Lines (0 = 1 lines, 1 = 2 lines)
81
-- DL = Data Length (0 = 4-bit bus, 1 = 8-bit bus) This is fixed at 1 in this module
82
-- A  = Address (see data sheet for usage)
83
-- T  = New Haven Only - Changes the character set (see data sheet)
84
--
85
-- Revision History
86
-- Author          Date     Change
87
------------------ -------- ---------------------------------------------------
88 287 jshamlet
-- Seth Henry      04/12/21 Design Start
89 286 jshamlet
 
90
 
91
library ieee;
92
use ieee.std_logic_1164.all;
93
use ieee.std_logic_unsigned.all;
94
use ieee.std_logic_arith.all;
95
 
96
library work;
97
use work.open8_pkg.all;
98
 
99
entity o8_hd44780_if is
100
generic(
101 289 jshamlet
  Use_4Bit_IF                : boolean := FALSE;
102 286 jshamlet
  -- Bus IF timing
103
  Tsu                        : integer :=  40; -- ns
104
  Tpw                        : integer := 250; -- nS
105
  Tcyc                       : integer := 500; -- nS
106
  -- Panel command timing
107
  Tpwrdly                    : integer := 40000; -- uS
108
  Tcldsp                     : integer :=  2000; -- uS
109
  Tbusy                      : integer :=    50; -- uS
110
  -- Contrast/Backlight
111
  Use_Backlight              : boolean := FALSE;
112
  Default_Brightness         : std_logic_vector(7 downto 0) := x"00";
113
  Clock_Frequency            : real;
114
  Address                    : ADDRESS_TYPE
115
);
116
port(
117
  Open8_Bus                  : in  OPEN8_BUS_TYPE;
118
  Write_Qual                 : in  std_logic := '1';
119
  Rd_Data                    : out DATA_TYPE;
120
  Interrupt                  : out std_logic;
121
  --
122
  LCD_E                      : out std_logic;
123
  LCD_RS                     : out std_logic;
124
  LCD_DQ                     : out std_logic_vector(7 downto 0);
125
  LCD_BL                     : out std_logic
126
);
127
end entity;
128
 
129
architecture behave of o8_hd44780_if is
130
 
131
  alias Clock                is Open8_Bus.Clock;
132
  alias Reset                is Open8_Bus.Reset;
133
  alias uSec_Tick            is Open8_Bus.uSec_Tick;
134
 
135
  constant User_Addr         : std_logic_vector(15 downto 2)
136
                               := Address(15 downto 2);
137
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 2);
138
  signal Addr_Match          : std_logic;
139
 
140
  alias  Reg_Sel_d           is Open8_Bus.Address(1 downto 0);
141
  signal Reg_Sel_q           : std_logic_vector(1 downto 0) := "00";
142
  signal Wr_En_d             : std_logic := '0';
143
  signal Wr_En_q             : std_logic := '0';
144
  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
145
  signal Wr_Data_q           : DATA_TYPE := x"00";
146
  signal Rd_En_d             : std_logic := '0';
147
  signal Rd_En_q             : std_logic := '0';
148
 
149
  signal Rearm_Init          : std_logic := '0';
150
 
151
  signal Reg_Valid           : std_logic := '0';
152
  signal Reg_Sel             : std_logic := '0';
153
  signal Reg_Data            : std_logic_vector(7 downto 0) := x"00";
154
 
155
  signal Tx_Ready            : std_logic := '0';
156
 
157
  constant HW_TMR_BITS       : integer := ceil_log2(Tpwrdly);
158
  constant TPWR_DELAY        : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
159
                               conv_std_logic_vector(Tpwrdly,HW_TMR_BITS);
160
 
161
  constant CLDSP_DELAY       : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
162
                               conv_std_logic_vector(Tcldsp,HW_TMR_BITS);
163
 
164
  constant BUSY_DELAY        : std_logic_vector(HW_TMR_BITS-1 downto 0) :=
165
                               conv_std_logic_vector(Tbusy, HW_TMR_BITS);
166
 
167
  signal hw_timer            : std_logic_vector(HW_TMR_BITS-1 downto 0);
168
 
169
  type CTRL_STATES is (INIT, PWR_WAIT, IDLE, PREP_WR, ISSUE_WR, WR_WAIT,
170
                       BUSY_WAIT, ISSUE_INT );
171
 
172
  signal ctrl_state          : CTRL_STATES := INIT;
173
 
174
  signal Wr_Fnset            : std_logic := '0';
175
  signal Wr_Data             : DATA_TYPE := x"00";
176
  signal Wr_Reg              : std_logic := '0';
177
  signal Wr_En               : std_logic := '0';
178
 
179
  signal IO_Done             : std_logic := '0';
180
 
181
  signal LCD_Data            : DATA_TYPE := x"00";
182
  signal LCD_Addr            : std_logic := '0';
183
 
184
--------------------------------------------------------------------------------
185
-- Backlight signals
186
--------------------------------------------------------------------------------
187
 
188
  signal LCD_Bright          : DATA_TYPE := x"00";
189
 
190
begin
191
 
192
--------------------------------------------------------------------------------
193
-- Open8 Register interface
194
--------------------------------------------------------------------------------
195
 
196
  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
197
  Wr_En_d                    <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
198
  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
199
 
200
  io_reg: process( Clock, Reset )
201
  begin
202
    if( Reset = Reset_Level )then
203
      Reg_Sel_q              <= "00";
204
      Wr_En_q                <= '0';
205
      Wr_Data_q              <= x"00";
206
      Rd_En_q                <= '0';
207
      Rd_Data                <= OPEN8_NULLBUS;
208
 
209
      Rearm_Init             <= '0';
210
 
211
      Reg_Valid              <= '0';
212
      Reg_Sel                <= '0';
213
      Reg_Data               <= x"00";
214
 
215
      LCD_Bright             <= Default_Brightness;
216
    elsif( rising_edge( Clock ) )then
217
      Reg_Sel_q              <= Reg_Sel_d;
218
 
219
      Rearm_Init             <= '0';
220
 
221
      Wr_En_q                <= Wr_En_d;
222
      Wr_Data_q              <= Wr_Data_d;
223
      Reg_Valid              <= '0';
224
      if( Wr_En_q = '1' )then
225
        case( Reg_Sel_q )is
226
          when "00" | "01" =>
227
            Reg_Valid        <= '1';
228
            Reg_Sel          <= Reg_Sel_q(0);
229
            Reg_Data         <= Wr_Data_q;
230
          when "10" =>
231
            Rearm_Init       <= '1';
232
          when "11" =>
233
            LCD_Bright       <= Wr_Data_q;
234
          when others => null;
235
        end case;
236
      end if;
237
 
238
      Rd_En_q                <= Rd_En_d;
239
      Rd_Data                <= OPEN8_NULLBUS;
240
      if( Rd_En_q = '1' )then
241
        case( Reg_Sel_q )is
242
          when "00" | "01" | "10" =>
243
            Rd_Data(7)       <= Tx_Ready;
244
          when "11" =>
245
            Rd_Data          <= LCD_Bright;
246
          when others => null;
247
        end case;
248
      end if;
249
    end if;
250
  end process;
251
 
252
--------------------------------------------------------------------------------
253
-- LCD and Register logic
254
--------------------------------------------------------------------------------
255
 
256
  LCD_Ctrl_proc: process( Clock, Reset )
257
  begin
258
    if( Reset = Reset_Level )then
259
      ctrl_state             <= INIT;
260
      hw_timer               <= (others => '0');
261
      Wr_Fnset               <= '0';
262
      Wr_Data                <= x"00";
263
      Wr_Reg                 <= '0';
264
      Wr_En                  <= '0';
265
      Tx_Ready               <= '0';
266
      Interrupt              <= '0';
267
    elsif( rising_edge(Clock) )then
268
      Wr_En                  <= '0';
269
      Tx_Ready               <= '0';
270
      Interrupt              <= '0';
271
      hw_timer               <= hw_timer - uSec_Tick;
272
      case( ctrl_state )is
273
 
274
        when INIT =>
275
          hw_timer           <= TPWR_DELAY;
276
          ctrl_state         <= PWR_WAIT;
277
 
278
        when PWR_WAIT =>
279
          if( hw_timer = 0 )then
280
            ctrl_state       <= IDLE;
281
          end if;
282
 
283
        when IDLE =>
284
          Tx_Ready           <= '1';
285
          if( Rearm_Init = '1' )then
286
            ctrl_state       <= INIT;
287
          elsif( Reg_Valid = '1' )then
288
            Wr_Reg           <= Reg_Sel;
289
            Wr_Data          <= Reg_Data;
290
            ctrl_state       <= PREP_WR;
291
          end if;
292
 
293
        when PREP_WR =>
294
          Wr_Fnset           <= '0';
295
          -- Trap on Function Set if we are in 4-bit mode, so that we can issue
296
          --  the first nibble twice.
297
          if( Use_4Bit_IF and
298
              Wr_Reg = '0' and
299
              Wr_Data(7 downto 4) = "0010" )then
300
            Wr_Fnset         <= '1';
301
          end if;
302
            ctrl_state       <= ISSUE_WR;
303
 
304
        when ISSUE_WR =>
305
          Wr_En              <= '1';
306
          hw_timer           <= BUSY_DELAY;
307 289 jshamlet
          if( Wr_Reg = '0' and Wr_Data < 4 )then
308 286 jshamlet
            hw_timer         <= CLDSP_DELAY;
309
          end if;
310
          ctrl_state         <= WR_WAIT;
311
 
312
        when WR_WAIT =>
313
          if( IO_Done = '1' )then
314
            ctrl_state       <= BUSY_WAIT;
315
          end if;
316
 
317
        when BUSY_WAIT =>
318
          if( hw_timer = 0 )then
319
            ctrl_state       <= ISSUE_INT;
320
          end if;
321
 
322
        when ISSUE_INT =>
323
          Interrupt          <= '1';
324
          ctrl_state         <= IDLE;
325
 
326
        when others => null;
327
 
328
      end case;
329
 
330
    end if;
331
  end process;
332
 
333
--------------------------------------------------------------------------------
334
-- Low-level I/O drivers
335
--------------------------------------------------------------------------------
336
 
337
IF_Type_4bit: if( Use_4Bit_IF )generate
338
 
339
  U_IO : entity work.hd44780_4b
340
  generic map(
341
    Tsu                      => Tsu,
342
    Tpw                      => Tpw,
343
    Tcyc                     => Tcyc,
344
    Clock_Frequency          => Clock_Frequency,
345
    Reset_Level              => Reset_Level
346
  )
347
  port map(
348
    Clock                    => Clock,
349
    Reset                    => Reset,
350
    --
351
    Wr_Fnset                 => Wr_Fnset,
352
    Wr_Data                  => Wr_Data,
353
    Wr_Reg                   => Wr_Reg,
354
    Wr_En                    => Wr_En,
355
    --
356
    IO_Done                  => IO_Done,
357
    --
358
    LCD_RS                   => LCD_RS,
359
    LCD_E                    => LCD_E,
360
    LCD_DQ                   => LCD_DQ
361
  );
362
 
363
end generate;
364
 
365
IF_Type_8bit: if( not Use_4Bit_IF )generate
366
 
367
  U_IO : entity work.hd44780_8b
368
  generic map(
369
    Tsu                      => Tsu,
370
    Tpw                      => Tpw,
371
    Tcyc                     => Tcyc,
372
    Clock_Frequency          => Clock_Frequency,
373
    Reset_Level              => Reset_Level
374
  )
375
  port map(
376
    Clock                    => Clock,
377
    Reset                    => Reset,
378
    --
379
    Wr_Data                  => Wr_Data,
380
    Wr_Reg                   => Wr_Reg,
381
    Wr_En                    => Wr_En,
382
    --
383
    IO_Done                  => IO_Done,
384
    --
385
    LCD_RS                   => LCD_RS,
386
    LCD_E                    => LCD_E,
387
    LCD_DQ                   => LCD_DQ
388
  );
389
 
390
end generate;
391
 
392
--------------------------------------------------------------------------------
393
-- Backlight control logic (optional)
394
--------------------------------------------------------------------------------
395
 
396
Backlight_Disabled: if( not Use_Backlight )generate
397
  LCD_BL                <= '0';
398
end generate;
399
 
400
Backlight_Enabled: if( Use_Backlight )generate
401
 
402
  U_BL : entity work.vdsm8
403
  generic map(
404
    Reset_Level              => Reset_Level
405
  )
406
  port map(
407
    Clock                    => Clock,
408
    Reset                    => Reset,
409
    DACin                    => LCD_Bright,
410
    DACout                   => LCD_BL
411
  );
412
 
413
end generate;
414
 
415
end architecture;

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