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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ltc2355_2p.vhd] - Blame information for rev 244

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1 194 jshamlet
-- Copyright (c)2013, 2020 Jeremy Seth Henry
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--     * Redistributions of source code must retain the above copyright
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--       notice, this list of conditions and the following disclaimer.
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--     * Redistributions in binary form must reproduce the above copyright
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--       notice, this list of conditions and the following disclaimer in the
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--       documentation and/or other materials provided with the distribution,
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--       where applicable (as part of a user interface, debugging port, etc.)
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 194 jshamlet
--
24 191 jshamlet
-- VHDL units : ltc2355_2p
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-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with
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--            :  common clock and CONVERT START inputs. Because they are
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--            :  synchronized, this entity provides simultaneously updated
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--            :  parallel data buses.
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--
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-- Notes      : Depends on the fact that the two LTC2355 converters are wired
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--            :  with their SCLK and CONV lines tied together, and DATA1 and
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--            :  DATA2 independently routed to separate I/O pins.
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--
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--            : Works best when the clock frequency is 96MHz or lower. Module
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--            :  will divide the clock by 2 if it is greater than this.
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--
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-- Revision History
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-- Author          Date     Change
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------------------ -------- ---------------------------------------------------
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-- Seth Henry      04/16/20 Revision block added
41 191 jshamlet
 
42
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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library work;
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  use work.open8_pkg.all;
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entity o8_ltc2355_2p is
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generic(
53 224 jshamlet
  Clock_Frequency            : real;
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  Address                    : ADDRESS_TYPE
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);
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port(
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  Open8_Bus                  : in  OPEN8_BUS_TYPE;
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  Rd_Data                    : out DATA_TYPE;
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  Interrupt                  : out std_logic;
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  -- ADC IF
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  ADC_SCLK                   : out std_logic;
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  ADC_CONV                   : out std_logic;
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  ADC_DATA1                  : in  std_logic;
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  ADC_DATA2                  : in  std_logic
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);
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end entity;
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architecture behave of o8_ltc2355_2p is
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70 224 jshamlet
  alias Clock                is Open8_Bus.Clock;
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  alias Reset                is Open8_Bus.Reset;
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  alias uSec_Tick            is Open8_Bus.uSec_Tick;
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74 224 jshamlet
  constant Divide_SCLK_by_2  : boolean := (Clock_Frequency > 96000000.0);
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76 191 jshamlet
  constant User_Addr         : std_logic_vector(15 downto 3) := Address(15 downto 3);
77 223 jshamlet
  alias  Comp_Addr           is Open8_Bus.Address(15 downto 3);
78 244 jshamlet
  signal Addr_Match          : std_logic;
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  alias  Reg_Sel_d           is Open8_Bus.Address(2 downto 0);
80 191 jshamlet
  signal Reg_Sel_q           : std_logic_vector(2 downto 0);
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  signal Wr_En_d             : std_logic := '0';
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  signal Wr_En_q             : std_logic := '0';
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  alias  Wr_Data_d           is Open8_Bus.Wr_Data;
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  signal Wr_Data_q           : DATA_TYPE := x"00";
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  signal Rd_En_d             : std_logic := '0';
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  signal Rd_En_q             : std_logic := '0';
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  signal User_Trig           : std_logic;
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90
  signal Timer_Int           : DATA_TYPE;
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  signal Timer_Cnt           : DATA_TYPE;
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  signal Timer_Trig          : std_logic;
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94
  type ADC_STATES is ( IDLE, START, CLK_HIGH, CLK_HIGH2, CLK_LOW, CLK_LOW2, UPDATE );
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  signal ad_state            : ADC_STATES;
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  signal rx_buffer1          : std_logic_vector(16 downto 0);
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  signal rx_buffer2          : std_logic_vector(16 downto 0);
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  signal bit_cntr            : std_logic_vector(4 downto 0);
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  constant BIT_COUNT         : std_logic_vector(4 downto 0) :=
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                                conv_std_logic_vector(16,5);
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  signal ADC1_Data           : std_logic_vector(13 downto 0);
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  signal ADC2_Data           : std_logic_vector(13 downto 0);
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  signal ADC_Ready           : std_logic;
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begin
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  Addr_Match                 <= '1' when Comp_Addr = User_Addr else '0';
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  Rd_En_d                    <= Addr_Match and Open8_Bus.Rd_En;
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  io_reg: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Reg_Sel_q              <= "000";
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      Wr_En_q                <= '0';
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      Wr_Data_q              <= x"00";
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      Rd_En_q                <= '0';
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      Rd_Data                <= OPEN8_NULLBUS;
119 244 jshamlet
 
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      User_Trig              <= '0';
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      Timer_Int              <= x"00";
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    elsif( rising_edge( Clock ) )then
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      Reg_Sel_q              <= Reg_Sel_d;
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      Wr_En_q                <= Wr_En_d;
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      Wr_Data_q              <= Wr_Data_d;
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      User_Trig              <= '0';
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      if( Wr_En_q = '1' )then
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        if( Reg_Sel_q = "110" )then
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          Timer_Int          <= Wr_Data_q;
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        end if;
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        if( Reg_Sel_q = "111" )then
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          User_Trig          <= '1';
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        end if;
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      end if;
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138 244 jshamlet
      Rd_En_q                <= Rd_En_d;
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      Rd_Data                <= OPEN8_NULLBUS;
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      if( Rd_En_q = '1' )then
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        case( Reg_Sel_q )is
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          -- Channel 1, Full resolution, lower byte
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          when "000" =>
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            Rd_Data          <= ADC1_Data(7 downto 0);
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          -- Channel 1, Full resolution, upper byte
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          when "001" =>
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            Rd_Data          <= "00" & ADC1_Data(13 downto 8);
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          -- Channel 2, Full resolution, lower byte
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          when "010" =>
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            Rd_Data          <= ADC2_Data(7 downto 0);
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          -- Channel 2, Full resolution, upper byte
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          when "011" =>
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            Rd_Data          <= "00" & ADC2_Data(13 downto 8);
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          -- Channel 1, 8-bit resolution
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          when "100" =>
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            Rd_Data          <= ADC1_Data(13 downto 6);
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          -- Channel 2, 8-bit resolution
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          when "101" =>
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            Rd_Data          <= ADC2_Data(13 downto 6);
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          -- Self-update rate
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          when "110" =>
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            Rd_Data          <= Timer_Int;
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          -- Interface status
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          when "111" =>
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            Rd_Data(7)       <= ADC_Ready;
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          when others =>
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            null;
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        end case;
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      end if;
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    end if;
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  end process;
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  Interval_proc: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      Timer_Cnt              <= x"00";
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      Timer_Trig             <= '0';
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    elsif( rising_edge(Clock) )then
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      Timer_Trig             <= '0';
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      Timer_Cnt              <= Timer_Cnt - uSec_Tick;
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      if( or_reduce(Timer_Cnt) = '0' )then
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        Timer_Cnt            <= Timer_Int;
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        Timer_Trig           <= or_reduce(Timer_Int); -- Only issue output on Int > 0
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      end if;
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    end if;
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  end process;
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  ADC_IO_FSM: process( Clock, Reset )
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  begin
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    if( Reset = Reset_Level )then
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      ad_state               <= IDLE;
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      ADC_Ready              <= '0';
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      rx_buffer1             <= (others => '0');
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      rx_buffer2             <= (others => '0');
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      bit_cntr               <= (others => '0');
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      ADC1_Data              <= (others => '0');
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      ADC2_Data              <= (others => '0');
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      ADC_SCLK               <= '1';
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      ADC_CONV               <= '0';
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      Interrupt              <= '0';
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    elsif( rising_edge(Clock) )then
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      ADC_Ready              <= '0';
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      ADC_SCLK               <= '1';
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      ADC_CONV               <= '0';
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      Interrupt              <= '0';
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      case( ad_state )is
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        when IDLE =>
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          ADC_Ready          <= '1';
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          if( (User_Trig or Timer_Trig) = '1' )then
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            ad_state         <= START;
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          end if;
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        when START =>
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          ADC_SCLK           <= '0';
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          ADC_CONV           <= '1';
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          bit_cntr           <= BIT_COUNT;
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          ad_state           <= CLK_HIGH;
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        when CLK_HIGH =>
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          ad_state           <= CLK_LOW;
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          if( Divide_SCLK_by_2 )then
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            ad_state         <= CLK_HIGH2;
230
          end if;
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        when CLK_HIGH2 =>
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          ad_state           <= CLK_LOW;
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235
        when CLK_LOW =>
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          ADC_SCLK           <= '0';
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          rx_buffer1(conv_integer(bit_cntr)) <= ADC_DATA1;
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          rx_buffer2(conv_integer(bit_cntr)) <= ADC_DATA2;
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          bit_cntr           <= bit_cntr - 1;
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          ad_state           <= CLK_HIGH;
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          if( bit_cntr = 0 )then
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            ad_state         <= UPDATE;
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          elsif( Divide_SCLK_by_2 )then
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            ad_state         <= CLK_LOW2;
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          end if;
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        when CLK_LOW2 =>
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          ADC_SCLK           <= '0';
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          ad_state           <= CLK_HIGH;
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        when UPDATE =>
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          ADC_SCLK           <= '0';
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          ad_state           <= IDLE;
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          ADC1_Data          <= rx_buffer1(14 downto 1);
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          ADC2_Data          <= rx_buffer2(14 downto 1);
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          Interrupt          <= '1';
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258
        when others =>
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          null;
260
      end case;
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262
    end if;
263
  end process;
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end architecture;

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