OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [taskmgr/] [app.s] - Blame information for rev 301

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 301 jshamlet
; Copyright (c)2022 Jeremy Seth Henry
2
; All rights reserved.
3
;
4
; Redistribution and use in source and binary forms, with or without
5
; modification, are permitted provided that the following conditions are met:
6
;     * Redistributions of source code must retain the above copyright
7
;       notice, this list of conditions and the following disclaimer.
8
;     * Redistributions in binary form must reproduce the above copyright
9
;       notice, this list of conditions and the following disclaimer in the
10
;       documentation and/or other materials provided with the distribution,
11
;       where applicable (as part of a user interface, debugging port, etc.)
12
;
13
; THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
14
; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
15
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16
; DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
17
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
20
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22
; THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23
;
24
;------------------------------------------------------------------------------
25
; Sample Task Manager application
26
;
27
; Revision History
28
; Author          Date     Change
29
;---------------- -------- ---------------------------------------------------
30
; Seth Henry      7/15/22  Initial Release
31
;-----------------------------------------------------------------------------
32
 
33
;------------------------------------------------------------------------------
34
; This application requires the following build parameters in the Open8 CPU
35
;  core to function correctly:
36
;
37
; Allow_Stack_Address_Move => true  RSP may relocate/retrieve the SP->R1:R0
38
; Enable_Auto_Increment    => true  Indexed load/store instructions can use
39
;                                    auto-increment feature when Rn is odd
40
;                                    (or Rn++ is specified).
41
; BRK_Implements_WAI       => true  BRK is interpreted as a WAI
42
; Enable_NMI               => true  Interrupt 0 is not maskable
43
; Sequential_Interrupts    => true  ISRs are NOT interruptable
44
; RTI_Ignores_GP_Flags     => true  RTI restores only lower 4 ALU flags
45
; Supervisor_Mode          => true  I-bit is restrictive
46
; Unsigned_Index_Offsets   => true  LDO/SDO treat offset as UNSIGNED
47
; Rotate_Ignores_Carry     => true  Rotate instrs do not use the carry
48
; Default_Int_Mask         => x"00" CPU starts with only the NMI active
49
;
50
; Further note - NOP is mapped to BRK in the assembler. Do NOT use NOP with
51
;  the BRK_Implements_WAI enabled, as the NOP will instead trigger WAI.
52
;------------------------------------------------------------------------------
53
 
54
;------------------------------------------------------------------------------
55
; BNI is used as a BRA (branch always) in user-mode code, since the I-bit
56
;  should never be set. There are checks in each task's main loop that verify
57
;  that this bit is cleared, and will panic the system otherwise.
58
; Similarily, in code running in the supervisor context, the I bit should
59
;  always be set, potentially allowing BRI to be used as a BRA. Note that this
60
;  isn't inherently safe, as ISR's are allowed to clear the I bit themselves
61
;  while user-mode code can't affect the I-bit.
62
;------------------------------------------------------------------------------
63
 
64
;------------------------------------------------------------------------------
65
; Include block - add all of the other source files here
66
;
67
; Note that the order of included files is important due to the way the
68
;  assembler works. Any constant which is used to derive another constant must
69
;  be defined first. The exception is creating pointer tables, which occurs on
70
;  a later pass.
71
;------------------------------------------------------------------------------
72
 
73
.INCLUDE "sys_hw_map.s"      ; System Memory Map (HDL <> ASSY)
74
.INCLUDE "sys_const.s"       ; System-Wide Constants
75
.INCLUDE "sys_version.s"     ; System software version
76
 
77
.INCLUDE "taskmgr_config.s"  ; Task manager cconfiguration constants
78
 
79
.INCLUDE "taskmgr_const.s"   ; Main task scheduler constants
80
 
81
.INCLUDE "task_0_const.s"    ; Task 0 Constants & Macros
82
.INCLUDE "task_1_const.s"    ; Task 1 Constants & Macros
83
 
84
.INCLUDE "taskmgr_func.s"    ; Main task scheduler & ISR code
85
 
86
.INCLUDE "task_0_func.s"     ; Task 0 Executable
87
.INCLUDE "task_1_func.s"     ; Task 1 Executable
88
 
89
;------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.