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[/] [openarty/] [trunk/] [Makefile] - Blame information for rev 60

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################################################################################
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##
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## Filename:    Makefile
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##
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## Project:     OpenArty, an entirely open SoC based upon the Arty platform
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##
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## Purpose:     A master project makefile.  It tries to build all targets
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##              within the project, mostly by directing subdirectory makes.
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##
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##
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## Creator:     Dan Gisselquist, Ph.D.
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##              Gisselquist Technology, LLC
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##
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################################################################################
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##
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## Copyright (C) 2015-2017, Gisselquist Technology, LLC
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##
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## This program is free software (firmware): you can redistribute it and/or
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## modify it under the terms of  the GNU General Public License as published
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## by the Free Software Foundation, either version 3 of the License, or (at
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## your option) any later version.
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##
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## This program is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License along
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## with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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## target there if the PDF file isn't present.)  If not, see
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##  for a copy.
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##
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## License:     GPL, v3, as defined and found on www.gnu.org,
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##              http://www.gnu.org/licenses/gpl.html
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##
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##
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################################################################################
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##
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##
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.PHONY: all
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all:    archive datestamp rtl sim sw
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# all:  datestamp archive rtl sw sim bench bit
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#
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# Could also depend upon load, if desired, but not necessary
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BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
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SIM   := `find sim -name Makefile` `find sim -name "*.cpp"` `find sim -name "*.h"` `find sim -name "*.c"`
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RTL   := `find rtl -name "*.v"` `find rtl -name Makefile`
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NOTES := `find . -name "*.txt"` `find . -name "*.html"`
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SW    := `find sw -name "*.cpp"` `find sw -name "*.c"`  \
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        `find sw -name "*.h"`   `find sw -name "*.sh"`  \
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        `find sw -name "*.py"`  `find sw -name "*.pl"`  \
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        `find sw -name "*.png"` `find sw -name Makefile`
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DEVSW := `find sw-board -name "*.cpp"` `find sw-board -name "*.h"` \
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        `find sw-board -name Makefile`
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PROJ  :=
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BIN  := `find xilinx -name "*.bit"`
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CONSTRAINTS := arty.xdc migmem.xdc
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YYMMDD:=`date +%Y%m%d`
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SUBMAKE := $(MAKE) --no-print-directory
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.PHONY: datestamp
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datestamp:
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        @bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm -f 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi'
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        @bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi'
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.PHONY: archive
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archive:
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        tar --transform s,^,$(YYMMDD)-arty/, -chjf $(YYMMDD)-arty.tjz $(BENCH) $(SW) $(RTL) $(SIM) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS) README.md
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.PHONY: verilated
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verilated: datestamp
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        $(SUBMAKE) --no-print-directory --directory=rtl
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.PHONY: rtl
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rtl: verilated
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.PHONY: sim
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sim: rtl
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        $(SUBMAKE) --directory=sim/verilated
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# .PHONY: bench
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# bench: sw
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#       cd sim/verilated ; $(MAKE) --no-print-directory
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.PHONY: sw
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sw: sw-host sw-board sw-zlib
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.PHONY: sw-host
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sw-host:
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        $(SUBMAKE) --directory=sw/host
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.PHONY: sw-zlib
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sw-zlib:
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        $(SUBMAKE) --directory=sw/zlib
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.PHONY: sw-board
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sw-board: sw-zlib
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        $(SUBMAKE) --directory=sw/board
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# .PHONY: bit
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# bit:
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#       cd xilinx ; $(MAKE) --no-print-directory xula.bit
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.PHONY: clean
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        $(SUBMAKE) --directory=rtl           clean
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        $(SUBMAKE) --directory=sw/host       clean
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        $(SUBMAKE) --directory=sw/board      clean
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        $(SUBMAKE) --directory=sim/verilated clean

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