OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [migmem.xdc] - Blame information for rev 29

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 dgisselq 
# A list of memory associated pins, suitable for ingesting into Xilinx's
2 
# Memory Interface Generator.
3 
 
4 
## Memory
5 
 
6 
# Memory address lines
7 
set_property PACKAGE_PIN R2 [get_ports {ddr3_addr[0]}]
8 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
9 
set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[1]}]
10 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
11 
set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[2]}]
12 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
13 
set_property PACKAGE_PIN T1 [get_ports {ddr3_addr[3]}]
14 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
15 
set_property PACKAGE_PIN N6 [get_ports {ddr3_addr[4]}]
16 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
17 
set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
18 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
19 
set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
20 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
21 
set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[7]}]
22 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
23 
set_property PACKAGE_PIN R8 [get_ports {ddr3_addr[8]}]
24 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
25 
set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
26 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
27 
set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[10]}]
28 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
29 
set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[11]}]
30 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
31 
set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[12]}]
32 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
33 
set_property PACKAGE_PIN T8 [get_ports {ddr3_addr[13]}]
34 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
35 
set_property PACKAGE_PIN R1 [get_ports {ddr3_ba[0]}]
36 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
37 
set_property PACKAGE_PIN P4 [get_ports {ddr3_ba[1]}]
38 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
39 
set_property PACKAGE_PIN P2 [get_ports {ddr3_ba[2]}]
40 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
41 
#
42 
set_property PACKAGE_PIN M4 [get_ports ddr3_cas_n]
43 
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
44 
# Clock lines
45 
set_property PACKAGE_PIN U9 [get_ports {ddr3_ck_p[0]}]
46 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_p[0]}]
47 
set_property PACKAGE_PIN V9 [get_ports {ddr3_ck_n[0]}]
48 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_ck_n[0]}]
49 
#
50 
set_property PACKAGE_PIN N5 [get_ports {ddr3_cke[0]}]
51 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
52 
#
53 
set_property PACKAGE_PIN U8 [get_ports {ddr3_cs_n[0]}]
54 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
55 
set_property PACKAGE_PIN L1 [get_ports {ddr3_dm[0]}]
56 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
57 
set_property PACKAGE_PIN U1 [get_ports {ddr3_dm[1]}]
58 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
59 
# Data (DQ) lines
60 
set_property PACKAGE_PIN K5 [get_ports {ddr3_dq[0]}]
61 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
62 
set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[1]}]
63 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
64 
set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[2]}]
65 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
66 
set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[3]}]
67 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
68 
set_property PACKAGE_PIN M3 [get_ports {ddr3_dq[4]}]
69 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
70 
set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[5]}]
71 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
72 
set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[6]}]
73 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
74 
set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[7]}]
75 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
76 
set_property PACKAGE_PIN V4 [get_ports {ddr3_dq[8]}]
77 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
78 
set_property PACKAGE_PIN T5 [get_ports {ddr3_dq[9]}]
79 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
80 
set_property PACKAGE_PIN U4 [get_ports {ddr3_dq[10]}]
81 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
82 
set_property PACKAGE_PIN V5 [get_ports {ddr3_dq[11]}]
83 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
84 
set_property PACKAGE_PIN V1 [get_ports {ddr3_dq[12]}]
85 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
86 
set_property PACKAGE_PIN T3 [get_ports {ddr3_dq[13]}]
87 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
88 
set_property PACKAGE_PIN U3 [get_ports {ddr3_dq[14]}]
89 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
90 
set_property PACKAGE_PIN R3 [get_ports {ddr3_dq[15]}]
91 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
92 
# DQS
93 
set_property PACKAGE_PIN N1 [get_ports {ddr3_dqs_n[0]}]
94 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
95 
set_property PACKAGE_PIN V2 [get_ports {ddr3_dqs_n[1]}]
96 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
97 
set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_p[0]}]
98 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
99 
set_property PACKAGE_PIN U2 [get_ports {ddr3_dqs_p[1]}]
100 
set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
101 
set_property PACKAGE_PIN R5 [get_ports {ddr3_odt[0]}]
102 
set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
103 
 
104 
set_property PACKAGE_PIN R5 [get_ports { ddr3_odt[0]}]
105 
set_property IOSTANDARD SSTL135 [get_ports { ddr3_odt[0]}]
106 
set_property PACKAGE_PIN P3 [get_ports ddr3_ras_n]
107 
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
108 
set_property PACKAGE_PIN K6 [get_ports ddr3_reset_n]
109 
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
110 
set_property PACKAGE_PIN P5 [get_ports ddr3_we_n]
111 
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
112 
#Internal VREF
113 
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
114 
 
115 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.