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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: busmaster.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose: This is the "bus interconnect", herein called the "busmaster".
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// This module connects all the devices on the Wishbone bus
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// within this project together. It is created by hand, not
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// automatically.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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dgisselq |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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dgisselq |
//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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dgisselq |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define NO_ZIP_WBU_DELAY
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`define ZIPCPU
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//
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//
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`define SDCARD_ACCESS
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`define ETHERNET_ACCESS
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`ifndef VERILATOR
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`define ICAPE_ACCESS
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`endif
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`define FLASH_ACCESS
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`define SDRAM_ACCESS
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`define GPS_CLOCK
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`ifdef VERILATOR
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`define GPSTB
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`endif
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dgisselq |
// UART_ACCESS and GPS_UART have both been placed within fastio
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// `define UART_ACCESS
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// `define GPS_UART
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`define RTC_ACCESS
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`define OLEDRGB_ACCESS
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//
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//
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//
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//
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//
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// Now, conditional compilation based upon what capabilities we have turned
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// on
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//
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`ifdef ZIPCPU
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`define ZIP_SYSTEM
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`ifndef ZIP_SYSTEM
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`define ZIP_BONES
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`endif // ZIP_SYSTEM
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`endif // ZipCPU
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//
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//
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// SCOPE POSITION ZERO
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//
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`ifdef FLASH_ACCESS
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// `define FLASH_SCOPE // Position zero
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`endif
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`ifdef ZIPCPU
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`ifndef FLASH_SCOPE
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`define CPU_SCOPE // Position zero
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`endif
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`endif
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//
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// SCOPE POSITION ONE
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//
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// `define GPS_SCOPE // Position one
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// `ifdef ICAPE_ACCESS
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// `define CFG_SCOPE // Position one
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// `endif
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// `define WBU_SCOPE
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//
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// SCOPE POSITION TWO
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//
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`ifdef SDRAM_ACCESS
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// `define SDRAM_SCOPE // Position two
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`endif
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//
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// SCOPE POSITION THREE
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//
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`ifdef ETHERNET_ACCESS
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`define ENET_SCOPE
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`endif
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//
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//
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dgisselq |
module busmaster(i_clk, i_rst,
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// CNC
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i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
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// Boad I/O
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i_sw, i_btn, o_led,
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o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
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// PMod I/O
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i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n, i_gps_rx, o_gps_tx,
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dgisselq |
// The Quad SPI Flash
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o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
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//
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// The DDR3 SDRAM
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//
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// The actual wires need to be controlled from the device
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// dependent file. In order to keep this device independent,
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// we export only the wishbone interface to the RAM.
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//
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// o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke,
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// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
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dgisselq |
// o_ddr_dqs, i_ddr_data, o_ddr_data,
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//
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// These wires allow us to push how we deal with the RAM
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// to the next level up, where they'll be use to interact
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// with a Xilinx specific core.
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o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata, o_ram_sel,
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i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
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i_ram_dbg,
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dgisselq |
// The SD Card
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o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
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dgisselq |
// Ethernet control (packets) lines
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o_net_reset_n, i_net_rx_clk, i_net_col, i_net_crs, i_net_dv,
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i_net_rxd, i_net_rxerr,
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i_net_tx_clk, o_net_tx_en, o_net_txd,
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dgisselq |
// Ethernet control (MDIO) lines
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o_mdclk, o_mdio, o_mdwe, i_mdio,
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// OLED Control interface (roughly SPI)
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o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
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o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
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// The GPS PMod
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i_gps_pps, i_gps_3df,
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// Other GPIO wires
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i_gpio, o_gpio
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);
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dgisselq |
parameter ZA=28, ZIPINTS=14, RESET_ADDRESS=32'h01380000,
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NGPI = 4, NGPO = 1;
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input i_clk, i_rst;
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// The bus commander, via an external uart port
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input i_rx_stb;
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input [7:0] i_rx_data;
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output wire o_tx_stb;
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output wire [7:0] o_tx_data;
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input i_tx_busy;
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// I/O to/from board level devices
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input [3:0] i_sw; // 16 switch bus
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input [3:0] i_btn; // 5 Buttons
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output wire [3:0] o_led; // 16 wide LED's
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output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
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// PMod UARTs
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input i_aux_rx, i_aux_cts_n;
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output wire o_aux_tx, o_aux_rts_n;
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input i_gps_rx;
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output wire o_gps_tx;
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// Quad-SPI flash control
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output wire o_qspi_cs_n, o_qspi_sck;
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output wire [3:0] o_qspi_dat;
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input [3:0] i_qspi_dat;
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output wire [1:0] o_qspi_mod;
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dgisselq |
//
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// DDR3 RAM controller
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//
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// These would be our RAM control lines. However, these are device,
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// implementation, and architecture dependent, rather than just simply
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// logic dependent. Therefore, this interface as it exists cannot
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// exist here. Instead, we export a device independent wishbone to
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// the RAM rather than the RAM wires themselves.
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dgisselq |
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// output wire o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke,
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dgisselq |
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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dgisselq |
// output wire [2:0] o_ddr_ba;
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// output wire [13:0] o_ddr_addr;
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// output wire o_ddr_odt;
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// output wire [1:0] o_ddr_dm;
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dgisselq |
// output wire [1:0] o_ddr_dqs;
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// input wire [15:0] i_ddr_data;
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// output wire [15:0] o_ddr_data;
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dgisselq |
//
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output wire o_ram_cyc, o_ram_stb, o_ram_we;
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output wire [25:0] o_ram_addr;
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output wire [31:0] o_ram_wdata;
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output wire [3:0] o_ram_sel;
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input i_ram_ack, i_ram_stall;
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input [31:0] i_ram_rdata;
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input i_ram_err;
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input [31:0] i_ram_dbg;
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dgisselq |
// The SD Card
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output wire o_sd_sck;
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output wire o_sd_cmd;
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output wire [3:0] o_sd_data;
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input i_sd_cmd;
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input [3:0] i_sd_data;
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input i_sd_detect;
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dgisselq |
// Ethernet control
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output wire o_net_reset_n;
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input i_net_rx_clk, i_net_col, i_net_crs, i_net_dv;
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input [3:0] i_net_rxd;
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input i_net_rxerr;
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input i_net_tx_clk;
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output wire o_net_tx_en;
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output wire [3:0] o_net_txd;
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dgisselq |
// Ethernet control (MDIO)
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output wire o_mdclk, o_mdio, o_mdwe;
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input i_mdio;
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// OLEDRGB interface
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output wire o_oled_sck, o_oled_cs_n, o_oled_mosi,
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o_oled_dcn, o_oled_reset_n, o_oled_vccen,
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o_oled_pmoden;
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// GPS PMod (GPS UART above)
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input i_gps_pps;
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input i_gps_3df;
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dgisselq |
// Other GPIO wires
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input [(NGPI-1):0] i_gpio;
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output wire [(NGPO-1):0] o_gpio;
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dgisselq |
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//
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//
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// Master wishbone wires
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//
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//
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dgisselq |
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err;
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dgisselq |
wire [31:0] wb_data;
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wire [(ZA-1):0] wb_addr;
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wire [3:0] wb_sel;
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dgisselq |
reg wb_ack;
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reg [31:0] wb_idata;
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// Interrupts
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wire gpio_int, oled_int, flash_int, scop_int;
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wire enet_tx_int, enet_rx_int, sdcard_int, rtc_int, rtc_pps,
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dgisselq |
auxrxf_int, auxtxf_int, gpsrxf_int, gpstxf_int,
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dgisselq |
auxrx_int, auxtx_int, gpsrx_int, gpstx_int,
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sw_int, btn_int;
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dgisselq |
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//
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//
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// First BUS master source: The UART
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//
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//
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wire [31:0] dwb_idata;
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// Wires going to devices
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wire wbu_cyc, wbu_stb, wbu_we;
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wire [31:0] wbu_addr, wbu_data;
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dgisselq |
wire [3:0] wbu_sel;
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dgisselq |
// and then coming from devices
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wire wbu_ack, wbu_stall, wbu_err;
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wire [31:0] wbu_idata;
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// And then headed back home
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dgisselq |
wire w_bus_interrupt;
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dgisselq |
// Oh, and the debug control for the ZIP CPU
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wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
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wire [31:0] zip_dbg_data;
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dgisselq |
`ifdef WBU_SCOPE
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wire [31:0] wbu_debug;
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`endif
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dgisselq |
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
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wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
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(wbu_zip_sel)?zip_dbg_ack:wbu_ack,
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(wbu_zip_sel)?zip_dbg_stall:wbu_stall,
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wbu_err,
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(wbu_zip_sel)?zip_dbg_data:wbu_idata,
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dgisselq |
w_bus_interrupt,
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dgisselq |
o_tx_stb, o_tx_data, i_tx_busy
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// , wbu_debug
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);
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dgisselq |
assign wbu_sel = 4'hf;
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dgisselq |
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dgisselq |
`ifdef WBU_SCOPE
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dgisselq |
// assign o_dbg = (wbu_ack)&&(wbu_cyc);
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30 |
dgisselq |
assign wbu_debug = { wbu_cyc, wbu_stb, wbu_we, wbu_ack, wbu_stall,
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wbu_err, wbu_zip_sel,
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wbu_addr[8:0],
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wbu_data[7:0],
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wbu_idata[7:0] };
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`endif
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3 |
dgisselq |
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wire zip_cpu_int; // True if the CPU suddenly halts
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`ifdef ZIPCPU
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// Are we trying to access the ZipCPU? Such accesses must be special,
|
| 298 |
|
|
// because they must succeed regardless of whether or not the ZipCPU
|
| 299 |
|
|
// is on the bus. Hence, we trap them here.
|
| 300 |
|
|
assign wbu_zip_sel = (wbu_addr[27]);
|
| 301 |
|
|
|
| 302 |
|
|
//
|
| 303 |
|
|
//
|
| 304 |
|
|
// Second BUS master source: The ZipCPU
|
| 305 |
|
|
//
|
| 306 |
|
|
//
|
| 307 |
50 |
dgisselq |
wire zip_cyc, zip_stb, zip_we;
|
| 308 |
|
|
wire [(ZA-1):0] zip_addr;
|
| 309 |
|
|
wire [31:0] zip_data, zip_scope_data;
|
| 310 |
|
|
wire [3:0] zip_sel;
|
| 311 |
3 |
dgisselq |
// and then coming from devices
|
| 312 |
|
|
wire zip_ack, zip_stall, zip_err;
|
| 313 |
|
|
|
| 314 |
|
|
`ifdef ZIP_SYSTEM
|
| 315 |
|
|
wire [(ZIPINTS-1):0] zip_interrupt_vec = {
|
| 316 |
|
|
// Lazy(ier) interrupts
|
| 317 |
36 |
dgisselq |
gpstx_int, gpsrx_int,
|
| 318 |
|
|
auxtx_int, auxrx_int,
|
| 319 |
50 |
dgisselq |
rtc_ppd,
|
| 320 |
|
|
// Fast interrupts
|
| 321 |
|
|
oled_int, w_bus_interrupt,
|
| 322 |
|
|
gpstxf_int, gpsrxf_int,
|
| 323 |
|
|
auxtxf_int, auxrxf_int,
|
| 324 |
36 |
dgisselq |
enet_tx_int, enet_rx_int, rtc_pps
|
| 325 |
3 |
dgisselq |
};
|
| 326 |
|
|
|
| 327 |
30 |
dgisselq |
zipsystem #( .RESET_ADDRESS(RESET_ADDRESS),
|
| 328 |
3 |
dgisselq |
.ADDRESS_WIDTH(ZA),
|
| 329 |
|
|
.LGICACHE(10),
|
| 330 |
|
|
.START_HALTED(1),
|
| 331 |
50 |
dgisselq |
.EXTERNAL_INTERRUPTS(ZIPINTS))
|
| 332 |
|
|
swic(i_clk, i_rst,
|
| 333 |
3 |
dgisselq |
// Zippys wishbone interface
|
| 334 |
50 |
dgisselq |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
| 335 |
3 |
dgisselq |
zip_ack, zip_stall, dwb_idata, zip_err,
|
| 336 |
|
|
zip_interrupt_vec, zip_cpu_int,
|
| 337 |
|
|
// Debug wishbone interface
|
| 338 |
|
|
((wbu_cyc)&&(wbu_zip_sel)),
|
| 339 |
|
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
| 340 |
|
|
wbu_data,
|
| 341 |
|
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
| 342 |
30 |
dgisselq |
`ifdef CPU_SCOPE
|
| 343 |
3 |
dgisselq |
, zip_scope_data
|
| 344 |
|
|
`endif
|
| 345 |
|
|
);
|
| 346 |
|
|
`else // ZIP_SYSTEM
|
| 347 |
|
|
wire w_zip_cpu_int_ignored;
|
| 348 |
30 |
dgisselq |
zipbones #( .RESET_ADDRESS(RESET_ADDRESS),
|
| 349 |
3 |
dgisselq |
.ADDRESS_WIDTH(ZA),
|
| 350 |
|
|
.LGICACHE(10),
|
| 351 |
50 |
dgisselq |
.START_HALTED(1))
|
| 352 |
|
|
swic(i_clk, i_rst,
|
| 353 |
3 |
dgisselq |
// Zippys wishbone interface
|
| 354 |
50 |
dgisselq |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
| 355 |
3 |
dgisselq |
zip_ack, zip_stall, dwb_idata, zip_err,
|
| 356 |
50 |
dgisselq |
w_bus_interrupt, w_zip_cpu_int_ignored,
|
| 357 |
3 |
dgisselq |
// Debug wishbone interface
|
| 358 |
|
|
((wbu_cyc)&&(wbu_zip_sel)),
|
| 359 |
|
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
| 360 |
|
|
wbu_data,
|
| 361 |
|
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
| 362 |
30 |
dgisselq |
`ifdef CPU_SCOPE
|
| 363 |
3 |
dgisselq |
, zip_scope_data
|
| 364 |
|
|
`endif
|
| 365 |
|
|
);
|
| 366 |
|
|
assign zip_cpu_int = 1'b0;
|
| 367 |
|
|
`endif // ZIP_SYSTEM v ZIP_BONES
|
| 368 |
|
|
|
| 369 |
|
|
//
|
| 370 |
|
|
//
|
| 371 |
|
|
// And an arbiter to decide who gets to access the bus
|
| 372 |
|
|
//
|
| 373 |
|
|
//
|
| 374 |
|
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
| 375 |
50 |
dgisselq |
wire [(ZA-1):0] dwb_addr;
|
| 376 |
|
|
wire [31:0] dwb_odata;
|
| 377 |
|
|
wire [3:0] dwb_sel;
|
| 378 |
|
|
wbpriarbiter #(32,ZA) wbu_zip_arbiter(i_clk,
|
| 379 |
3 |
dgisselq |
// The ZIP CPU Master -- Gets the priority slot
|
| 380 |
50 |
dgisselq |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
| 381 |
3 |
dgisselq |
zip_ack, zip_stall, zip_err,
|
| 382 |
|
|
// The UART interface Master
|
| 383 |
30 |
dgisselq |
(wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we,
|
| 384 |
50 |
dgisselq |
wbu_addr[(ZA-1):0], wbu_data, wbu_sel,
|
| 385 |
3 |
dgisselq |
wbu_ack, wbu_stall, wbu_err,
|
| 386 |
|
|
// Common bus returns
|
| 387 |
50 |
dgisselq |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,
|
| 388 |
3 |
dgisselq |
dwb_ack, dwb_stall, dwb_err);
|
| 389 |
|
|
|
| 390 |
50 |
dgisselq |
//
|
| 391 |
|
|
//
|
| 392 |
3 |
dgisselq |
// And because the ZIP CPU and the Arbiter create an unacceptable
|
| 393 |
|
|
// delay, we fail timing. So we add in a delay cycle ...
|
| 394 |
50 |
dgisselq |
//
|
| 395 |
|
|
//
|
| 396 |
3 |
dgisselq |
assign wbu_idata = dwb_idata;
|
| 397 |
50 |
dgisselq |
busdelay #(ZA) wbu_zip_delay(i_clk,
|
| 398 |
|
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,
|
| 399 |
3 |
dgisselq |
dwb_ack, dwb_stall, dwb_idata, dwb_err,
|
| 400 |
50 |
dgisselq |
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel,
|
| 401 |
3 |
dgisselq |
wb_ack, wb_stall, wb_idata, wb_err);
|
| 402 |
|
|
|
| 403 |
|
|
`else // ZIPCPU
|
| 404 |
|
|
assign zip_cpu_int = 1'b0; // No CPU here to halt
|
| 405 |
|
|
assign wbu_zip_sel = 1'b0;
|
| 406 |
|
|
|
| 407 |
|
|
// If there's no ZipCPU, there's no need for a Zip/WB-Uart bus delay.
|
| 408 |
|
|
// We can go directly from the WB-Uart master bus to the master bus
|
| 409 |
|
|
// itself.
|
| 410 |
|
|
assign wb_cyc = wbu_cyc;
|
| 411 |
|
|
assign wb_stb = wbu_stb;
|
| 412 |
|
|
assign wb_we = wbu_we;
|
| 413 |
|
|
assign wb_addr = wbu_addr;
|
| 414 |
|
|
assign wb_data = wbu_data;
|
| 415 |
50 |
dgisselq |
assign wb_sel = wbu_sel;
|
| 416 |
3 |
dgisselq |
assign wbu_idata = wb_idata;
|
| 417 |
|
|
assign wbu_ack = wb_ack;
|
| 418 |
|
|
assign wbu_stall = wb_stall;
|
| 419 |
|
|
assign wbu_err = wb_err;
|
| 420 |
|
|
|
| 421 |
|
|
// The CPU never halts if it doesn't exist, so set this interrupt to
|
| 422 |
|
|
// zero.
|
| 423 |
|
|
assign zip_cpu_int= 1'b0;
|
| 424 |
|
|
`endif // ZIPCPU
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
//
|
| 428 |
|
|
// Peripheral select lines.
|
| 429 |
|
|
//
|
| 430 |
|
|
// These lines will be true during any wishbone cycle whose address
|
| 431 |
|
|
// line selects the given I/O peripheral. The none_sel and many_sel
|
| 432 |
|
|
// lines are used to detect problems, such as when no device is
|
| 433 |
|
|
// selected or many devices are selected. Such problems will lead to
|
| 434 |
|
|
// bus errors (below).
|
| 435 |
|
|
//
|
| 436 |
50 |
dgisselq |
wire io_sel, scop_sel, rtc_sel, oled_sel, uart_sel, gpsu_sel,
|
| 437 |
|
|
sdcard_sel, gps_sel, netp_sel, mio_sel, cfg_sel,
|
| 438 |
|
|
ram_sel, flash_sel, flctl_sel, mem_sel, netb_sel,
|
| 439 |
3 |
dgisselq |
none_sel, many_sel;
|
| 440 |
|
|
|
| 441 |
50 |
dgisselq |
wire idle_n;
|
| 442 |
|
|
`ifdef ZERO_ON_IDLE
|
| 443 |
|
|
assign idle_n = wb_stb;
|
| 444 |
|
|
`else
|
| 445 |
|
|
assign idle_n = 1'b1;
|
| 446 |
|
|
`endif
|
| 447 |
3 |
dgisselq |
wire [4:0] skipaddr;
|
| 448 |
|
|
assign skipaddr = { wb_addr[26], wb_addr[22], wb_addr[15], wb_addr[11],
|
| 449 |
|
|
~wb_addr[8] };
|
| 450 |
50 |
dgisselq |
assign ram_sel = (idle_n)&&(skipaddr[4]);
|
| 451 |
|
|
assign flash_sel = (idle_n)&&(skipaddr[4:3]==2'b01);
|
| 452 |
|
|
assign mem_sel = (idle_n)&&(skipaddr[4:2]==3'b001);
|
| 453 |
|
|
assign netb_sel = (idle_n)&&(skipaddr[4:1]==4'b0001);
|
| 454 |
|
|
assign io_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b00_0);
|
| 455 |
|
|
assign scop_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b00_100);
|
| 456 |
|
|
assign rtc_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1010);
|
| 457 |
|
|
assign oled_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1011);
|
| 458 |
|
|
assign uart_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1100);
|
| 459 |
|
|
assign gpsu_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1101);
|
| 460 |
|
|
assign sdcard_sel= (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1110);
|
| 461 |
|
|
//assign unused_ = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1111);
|
| 462 |
|
|
assign gps_sel = (idle_n)&&(~|skipaddr)&&((wb_addr[7:2]==6'b01_0000)
|
| 463 |
|
|
||(wb_addr[7:3]==5'b01_001));
|
| 464 |
|
|
assign netp_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b01_010);
|
| 465 |
|
|
assign mio_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b01_1);
|
| 466 |
|
|
assign flctl_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_0);
|
| 467 |
|
|
assign cfg_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_1);
|
| 468 |
3 |
dgisselq |
|
| 469 |
|
|
wire skiperr;
|
| 470 |
50 |
dgisselq |
assign skiperr = (idle_n)&&((|wb_addr[(ZA-1):27])
|
| 471 |
3 |
dgisselq |
||(~skipaddr[4])&&(|wb_addr[25:23])
|
| 472 |
|
|
||(skipaddr[4:3]==2'b00)&&(|wb_addr[21:16])
|
| 473 |
|
|
||(skipaddr[4:2]==3'b000)&&(|wb_addr[14:12])
|
| 474 |
50 |
dgisselq |
||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9])
|
| 475 |
|
|
||(skipaddr[4:0]==5'b00001));
|
| 476 |
3 |
dgisselq |
|
| 477 |
|
|
|
| 478 |
|
|
//
|
| 479 |
|
|
// Peripheral acknowledgement lines
|
| 480 |
|
|
//
|
| 481 |
|
|
// These are only a touch more confusing, since the flash device will
|
| 482 |
|
|
// ACK for both flctl_sel (the control line select), as well as the
|
| 483 |
|
|
// flash_sel (the memory line select). Hence we have one fewer ack
|
| 484 |
|
|
// line.
|
| 485 |
50 |
dgisselq |
wire io_ack, rtc_ack, oled_ack, uart_ack, gpsu_ack, sdcard_ack,
|
| 486 |
|
|
gps_ack, net_ack, mio_ack, cfg_ack,
|
| 487 |
3 |
dgisselq |
mem_ack, flash_ack, ram_ack;
|
| 488 |
50 |
dgisselq |
|
| 489 |
3 |
dgisselq |
reg many_ack, slow_many_ack;
|
| 490 |
|
|
reg slow_ack, scop_ack;
|
| 491 |
30 |
dgisselq |
wire [4:0] ack_list;
|
| 492 |
|
|
assign ack_list = { ram_ack, flash_ack, mem_ack, net_ack, slow_ack };
|
| 493 |
3 |
dgisselq |
initial many_ack = 1'b0;
|
| 494 |
|
|
always @(posedge i_clk)
|
| 495 |
30 |
dgisselq |
many_ack <= ((ack_list != 5'h10)
|
| 496 |
|
|
&&(ack_list != 5'h8)
|
| 497 |
|
|
&&(ack_list != 5'h4)
|
| 498 |
|
|
&&(ack_list != 5'h2)
|
| 499 |
|
|
&&(ack_list != 5'h1)
|
| 500 |
|
|
&&(ack_list != 5'h0));
|
| 501 |
50 |
dgisselq |
wire [9:0] slow_ack_list;
|
| 502 |
|
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack, uart_ack, gpsu_ack,
|
| 503 |
3 |
dgisselq |
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
|
| 504 |
|
|
initial slow_many_ack = 1'b0;
|
| 505 |
|
|
always @(posedge i_clk)
|
| 506 |
50 |
dgisselq |
slow_many_ack <= ((slow_ack_list != 10'h200)
|
| 507 |
|
|
&&(slow_ack_list != 10'h100)
|
| 508 |
|
|
&&(slow_ack_list != 10'h080)
|
| 509 |
|
|
&&(slow_ack_list != 10'h040)
|
| 510 |
|
|
&&(slow_ack_list != 10'h020)
|
| 511 |
|
|
&&(slow_ack_list != 10'h010)
|
| 512 |
|
|
&&(slow_ack_list != 10'h008)
|
| 513 |
|
|
&&(slow_ack_list != 10'h004)
|
| 514 |
|
|
&&(slow_ack_list != 10'h002)
|
| 515 |
|
|
&&(slow_ack_list != 10'h001)
|
| 516 |
|
|
&&(slow_ack_list != 10'h000));
|
| 517 |
3 |
dgisselq |
|
| 518 |
|
|
always @(posedge i_clk)
|
| 519 |
25 |
dgisselq |
wb_ack <= (wb_cyc)&&(|ack_list);
|
| 520 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 521 |
25 |
dgisselq |
slow_ack <= (wb_cyc)&&(|slow_ack_list);
|
| 522 |
3 |
dgisselq |
|
| 523 |
|
|
//
|
| 524 |
|
|
// Peripheral data lines
|
| 525 |
|
|
//
|
| 526 |
50 |
dgisselq |
wire [31:0] io_data, rtc_data, oled_data, uart_data, gpsu_data,
|
| 527 |
|
|
sdcard_data,
|
| 528 |
30 |
dgisselq |
net_data, gps_data, mio_data, cfg_data,
|
| 529 |
3 |
dgisselq |
mem_data, flash_data, ram_data;
|
| 530 |
|
|
reg [31:0] slow_data, scop_data;
|
| 531 |
|
|
|
| 532 |
50 |
dgisselq |
// 4 control lines, 5x32 data lines ...
|
| 533 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 534 |
|
|
if ((ram_ack)||(flash_ack))
|
| 535 |
|
|
wb_idata <= (ram_ack)?ram_data:flash_data;
|
| 536 |
30 |
dgisselq |
else if ((mem_ack)||(net_ack))
|
| 537 |
|
|
wb_idata <= (mem_ack)?mem_data:net_data;
|
| 538 |
3 |
dgisselq |
else
|
| 539 |
30 |
dgisselq |
wb_idata <= slow_data;
|
| 540 |
3 |
dgisselq |
|
| 541 |
50 |
dgisselq |
// 9 control lines, 10x32 data lines
|
| 542 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 543 |
|
|
if ((cfg_ack)||(mio_ack))
|
| 544 |
|
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
| 545 |
50 |
dgisselq |
else if ((uart_ack)||(gpsu_ack))
|
| 546 |
|
|
slow_data <= (uart_ack)?uart_data : gpsu_data;
|
| 547 |
3 |
dgisselq |
else if ((sdcard_ack)||(rtc_ack))
|
| 548 |
|
|
slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
|
| 549 |
|
|
else if ((scop_ack)|(oled_ack))
|
| 550 |
|
|
slow_data <= (scop_ack)?scop_data:oled_data;
|
| 551 |
|
|
else
|
| 552 |
25 |
dgisselq |
slow_data <= (gps_ack) ? gps_data : io_data;
|
| 553 |
3 |
dgisselq |
|
| 554 |
|
|
//
|
| 555 |
|
|
// Peripheral stall lines
|
| 556 |
|
|
//
|
| 557 |
|
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
| 558 |
|
|
// *must* be done via combinatorial logic.
|
| 559 |
|
|
//
|
| 560 |
|
|
wire io_stall, scop_stall, oled_stall,
|
| 561 |
50 |
dgisselq |
rtc_stall, sdcard_stall, uart_stall, gpsu_stall,
|
| 562 |
30 |
dgisselq |
net_stall, gps_stall, mio_stall, cfg_stall, netb_stall,
|
| 563 |
3 |
dgisselq |
mem_stall, flash_stall, ram_stall,
|
| 564 |
|
|
many_stall;
|
| 565 |
|
|
assign wb_stall = (wb_cyc)&&(
|
| 566 |
|
|
((io_sel)&&(io_stall)) // Never stalls
|
| 567 |
|
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
| 568 |
|
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
| 569 |
50 |
dgisselq |
||((oled_sel)&&(oled_stall)) // Never stalls
|
| 570 |
|
|
||((uart_sel)&&(uart_stall)) // Never stalls
|
| 571 |
|
|
||((gpsu_sel)&&(gpsu_stall)) // Never stalls
|
| 572 |
3 |
dgisselq |
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
| 573 |
30 |
dgisselq |
||((netp_sel)&&(net_stall)) // Never stalls
|
| 574 |
3 |
dgisselq |
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
| 575 |
|
|
||((mio_sel)&&(mio_stall))
|
| 576 |
|
|
||((cfg_sel)&&(cfg_stall))
|
| 577 |
30 |
dgisselq |
||((netb_sel)&&(net_stall)) // Never stalls
|
| 578 |
3 |
dgisselq |
||((mem_sel)&&(mem_stall)) // Never stalls
|
| 579 |
|
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
| 580 |
|
|
||((ram_sel)&&(ram_stall)));
|
| 581 |
|
|
|
| 582 |
|
|
|
| 583 |
|
|
//
|
| 584 |
|
|
// Bus Error calculation(s)
|
| 585 |
|
|
//
|
| 586 |
|
|
|
| 587 |
|
|
// Selecting nothing is only an error if the strobe line is high as well
|
| 588 |
|
|
// as the cycle line. However, this is captured within the wb_err
|
| 589 |
|
|
// logic itself, so we can ignore it for a line or two.
|
| 590 |
|
|
assign none_sel = ( //(skiperr)||
|
| 591 |
|
|
(~|{ io_sel, scop_sel, flctl_sel, rtc_sel,
|
| 592 |
|
|
sdcard_sel, netp_sel, gps_sel,
|
| 593 |
|
|
oled_sel,
|
| 594 |
|
|
mio_sel, cfg_sel, netb_sel, mem_sel,
|
| 595 |
|
|
flash_sel,ram_sel }));
|
| 596 |
|
|
//
|
| 597 |
|
|
// Selecting multiple devices at once is a design flaw that should
|
| 598 |
|
|
// never happen. Hence, if this logic won't build, we won't include
|
| 599 |
|
|
// it. Still, having this logic in place has saved my tush more than
|
| 600 |
|
|
// once.
|
| 601 |
|
|
//
|
| 602 |
50 |
dgisselq |
reg [(ZA-1):0] sel_addr;
|
| 603 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 604 |
|
|
sel_addr <= wb_addr;
|
| 605 |
|
|
|
| 606 |
|
|
reg many_sel_a, many_sel_b, single_sel_a, single_sel_b, last_stb;
|
| 607 |
|
|
always @(posedge i_clk)
|
| 608 |
|
|
begin
|
| 609 |
|
|
last_stb <= wb_stb;
|
| 610 |
|
|
|
| 611 |
|
|
single_sel_a <= (wb_stb)&&((ram_sel)|(flash_sel)
|
| 612 |
50 |
dgisselq |
|(mem_sel)|(netb_sel)|(cfg_sel)
|
| 613 |
|
|
|(uart_sel)|(gpsu_sel));
|
| 614 |
3 |
dgisselq |
many_sel_a <= 1'b0;
|
| 615 |
50 |
dgisselq |
if ((ram_sel)&&((flash_sel)||(mem_sel)||(netb_sel)||(cfg_sel)
|
| 616 |
|
|
||(uart_sel)||(gpsu_sel)))
|
| 617 |
3 |
dgisselq |
many_sel_a <= 1'b1;
|
| 618 |
50 |
dgisselq |
else if ((flash_sel)&&((mem_sel)||(netb_sel)||(cfg_sel)
|
| 619 |
|
|
||(uart_sel)||(gpsu_sel)))
|
| 620 |
3 |
dgisselq |
many_sel_a <= 1'b1;
|
| 621 |
50 |
dgisselq |
else if ((mem_sel)&&((netb_sel)||(cfg_sel)
|
| 622 |
|
|
||(uart_sel)||(gpsu_sel)))
|
| 623 |
3 |
dgisselq |
many_sel_a <= 1'b1;
|
| 624 |
50 |
dgisselq |
else if ((netb_sel)&&((cfg_sel)||(uart_sel)||(gpsu_sel)))
|
| 625 |
3 |
dgisselq |
many_sel_a <= 1'b1;
|
| 626 |
50 |
dgisselq |
else if ((cfg_sel)&&((uart_sel)||(gpsu_sel)))
|
| 627 |
|
|
many_sel_a <= 1'b1;
|
| 628 |
|
|
else if ((uart_sel)&&(gpsu_sel))
|
| 629 |
|
|
many_sel_a <= 1'b1;
|
| 630 |
3 |
dgisselq |
|
| 631 |
|
|
single_sel_b <= (wb_stb)&&((mio_sel)||(gps_sel)||(netp_sel)
|
| 632 |
|
|
||(sdcard_sel)||(rtc_sel)||(flctl_sel)
|
| 633 |
|
|
||(oled_sel)||(scop_sel)||(io_sel));
|
| 634 |
|
|
many_sel_b <= 1'b0;
|
| 635 |
|
|
if ((mio_sel)&&((gps_sel)||(netp_sel)||(sdcard_sel)||(rtc_sel)
|
| 636 |
|
|
||(flctl_sel)||(scop_sel)||(oled_sel)||(io_sel)))
|
| 637 |
|
|
many_sel_b <= 1'b1;
|
| 638 |
|
|
else if ((gps_sel)&&((netp_sel)||(sdcard_sel)||(rtc_sel)
|
| 639 |
|
|
||(flctl_sel)||(scop_sel)||(oled_sel)||(io_sel)))
|
| 640 |
|
|
many_sel_b <= 1'b1;
|
| 641 |
|
|
else if ((netp_sel)&&((sdcard_sel)||(rtc_sel)
|
| 642 |
|
|
||(flctl_sel)||(scop_sel)||(oled_sel)||(io_sel)))
|
| 643 |
|
|
many_sel_b <= 1'b1;
|
| 644 |
|
|
else if ((sdcard_sel)&&((rtc_sel)
|
| 645 |
|
|
||(flctl_sel)||(scop_sel)||(oled_sel)||(io_sel)))
|
| 646 |
|
|
many_sel_b <= 1'b1;
|
| 647 |
|
|
else if ((rtc_sel)&&((flctl_sel)||(scop_sel)||(oled_sel)||(io_sel)))
|
| 648 |
|
|
many_sel_b <= 1'b1;
|
| 649 |
|
|
else if ((flctl_sel)&&((scop_sel)||(oled_sel)||(io_sel)))
|
| 650 |
|
|
many_sel_b <= 1'b1;
|
| 651 |
|
|
else if ((scop_sel)&&((oled_sel)||(io_sel)))
|
| 652 |
|
|
many_sel_b <= 1'b1;
|
| 653 |
|
|
else if ((oled_sel)&&(io_sel))
|
| 654 |
|
|
many_sel_b <= 1'b1;
|
| 655 |
|
|
end
|
| 656 |
|
|
|
| 657 |
|
|
wire sel_err; // 5 inputs
|
| 658 |
50 |
dgisselq |
assign sel_err = ( (last_stb)&&(!single_sel_a)&&(!single_sel_b))
|
| 659 |
3 |
dgisselq |
||((single_sel_a)&&(single_sel_b))
|
| 660 |
|
|
||((single_sel_a)&&(many_sel_a))
|
| 661 |
|
|
||((single_sel_b)&&(many_sel_b));
|
| 662 |
25 |
dgisselq |
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack||ram_err);
|
| 663 |
3 |
dgisselq |
|
| 664 |
|
|
|
| 665 |
|
|
// Finally, if we ever encounter a bus error, knowing the address of
|
| 666 |
|
|
// the error will be important to figuring out how to fix it. Hence,
|
| 667 |
|
|
// we grab it here. Be aware, however, that this might not truly be
|
| 668 |
|
|
// the address that caused an error: in the case of none_sel it will
|
| 669 |
|
|
// be, but if many_ack or slow_many_ack are true then we might just be
|
| 670 |
|
|
// looking at an address on the bus that was nearby the one requested.
|
| 671 |
50 |
dgisselq |
reg [(ZA-1):0] r_bus_err_addr;
|
| 672 |
|
|
initial r_bus_err_addr = 0;
|
| 673 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 674 |
|
|
if (wb_err)
|
| 675 |
50 |
dgisselq |
r_bus_err_addr <= sel_addr;
|
| 676 |
|
|
wire [31:0] bus_err_addr;
|
| 677 |
|
|
assign bus_err_addr[(ZA+1):0] = { r_bus_err_addr, 2'b00 };
|
| 678 |
|
|
generate if (ZA < 30)
|
| 679 |
|
|
assign bus_err_addr[31:(ZA+2)] = 0;
|
| 680 |
|
|
endgenerate
|
| 681 |
3 |
dgisselq |
|
| 682 |
|
|
//
|
| 683 |
|
|
// I/O peripheral
|
| 684 |
|
|
//
|
| 685 |
|
|
// The I/O processor, herein called an fastio. This is a unique
|
| 686 |
|
|
// set of peripherals--these are all of the peripherals that can answer
|
| 687 |
50 |
dgisselq |
// in a single clock--or, rather, they are the peripherals that can
|
| 688 |
3 |
dgisselq |
// answer the bus before their clock. Hence, the fastio simply consists
|
| 689 |
|
|
// of a mux that selects between various peripheral responses. Further,
|
| 690 |
|
|
// these peripherals are not allowed to stall the bus.
|
| 691 |
|
|
//
|
| 692 |
|
|
// There is no option for turning these off--they will always be on.
|
| 693 |
50 |
dgisselq |
wire [11:0] master_ints;
|
| 694 |
|
|
assign master_ints = { zip_cpu_int,
|
| 695 |
|
|
gpsrx_int, auxtx_int, auxrx_int,
|
| 696 |
|
|
oled_int, rtc_int, sdcard_int,
|
| 697 |
3 |
dgisselq |
enet_tx_int, enet_rx_int,
|
| 698 |
|
|
scop_int, flash_int, rtc_pps };
|
| 699 |
50 |
dgisselq |
wire [2:0] board_ints;
|
| 700 |
3 |
dgisselq |
wire [3:0] w_led;
|
| 701 |
|
|
wire rtc_ppd;
|
| 702 |
|
|
fastio #(
|
| 703 |
50 |
dgisselq |
.EXTRACLOCK(0), .NGPI(NGPI), .NGPO(NGPO)
|
| 704 |
3 |
dgisselq |
) runio(i_clk, i_sw, i_btn,
|
| 705 |
|
|
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
| 706 |
50 |
dgisselq |
i_gpio, o_gpio,
|
| 707 |
3 |
dgisselq |
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
| 708 |
|
|
wb_data, io_ack, io_stall, io_data,
|
| 709 |
|
|
rtc_ppd,
|
| 710 |
49 |
dgisselq |
bus_err_addr, gps_now[63:32], gps_step[47:16],
|
| 711 |
50 |
dgisselq |
master_ints, w_bus_interrupt,
|
| 712 |
3 |
dgisselq |
board_ints);
|
| 713 |
50 |
dgisselq |
assign { gpio_int, sw_int, btn_int } = board_ints;
|
| 714 |
3 |
dgisselq |
|
| 715 |
|
|
assign o_led = w_led;
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
//
|
| 719 |
|
|
//
|
| 720 |
|
|
// Real Time Clock (RTC) device level access
|
| 721 |
|
|
//
|
| 722 |
|
|
//
|
| 723 |
|
|
wire gps_tracking, ck_pps;
|
| 724 |
|
|
wire [63:0] gps_step;
|
| 725 |
|
|
`ifdef RTC_ACCESS
|
| 726 |
25 |
dgisselq |
rtcgps
|
| 727 |
|
|
// #(32'h15798f) // 2^48 / 200MHz
|
| 728 |
|
|
// #(32'h1a6e3a) // 2^48 / 162.5 MHz
|
| 729 |
|
|
#(32'h34dc74) // 2^48 / 81.25MHz
|
| 730 |
|
|
// #(32'h35afe6) // 2^48 / 80.0 MHz
|
| 731 |
3 |
dgisselq |
thertc(i_clk,
|
| 732 |
|
|
wb_cyc, (wb_stb)&&(rtc_sel), wb_we,
|
| 733 |
|
|
wb_addr[1:0], wb_data,
|
| 734 |
|
|
rtc_data, rtc_int, rtc_ppd,
|
| 735 |
|
|
gps_tracking, ck_pps, gps_step[47:16], rtc_pps);
|
| 736 |
|
|
`else
|
| 737 |
|
|
assign rtc_data = 32'h00;
|
| 738 |
|
|
assign rtc_int = 1'b0;
|
| 739 |
|
|
assign rtc_pps = 1'b0;
|
| 740 |
|
|
assign rtc_ppd = 1'b0;
|
| 741 |
|
|
`endif
|
| 742 |
|
|
reg r_rtc_ack;
|
| 743 |
|
|
initial r_rtc_ack = 1'b0;
|
| 744 |
|
|
always @(posedge i_clk)
|
| 745 |
|
|
r_rtc_ack <= (wb_stb)&&(rtc_sel);
|
| 746 |
|
|
assign rtc_ack = r_rtc_ack;
|
| 747 |
|
|
assign rtc_stall = 1'b0;
|
| 748 |
|
|
|
| 749 |
|
|
//
|
| 750 |
|
|
//
|
| 751 |
50 |
dgisselq |
// Auxilliary UART (console port)
|
| 752 |
|
|
//
|
| 753 |
|
|
//
|
| 754 |
|
|
wbuart #(31'd705) // 115200 Baud, 8N1, from 81.25M
|
| 755 |
|
|
console(i_clk, 1'b0,
|
| 756 |
|
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we, wb_addr[1:0], wb_data,
|
| 757 |
|
|
uart_ack, uart_stall, uart_data,
|
| 758 |
|
|
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n,
|
| 759 |
|
|
auxrx_int, auxtx_int, auxrxf_int, auxtxf_int);
|
| 760 |
|
|
|
| 761 |
|
|
//
|
| 762 |
|
|
//
|
| 763 |
|
|
// GPS Data UART
|
| 764 |
|
|
//
|
| 765 |
|
|
//
|
| 766 |
|
|
wire gps_rts_n_ignored;
|
| 767 |
|
|
wbuart #(.INITIAL_SETUP(31'd8464), // 9600 Baud, 8N1
|
| 768 |
|
|
.HARDWARE_FLOW_CONTROL_PRESENT(1'b0))
|
| 769 |
|
|
gpsdata(i_clk, 1'b0,
|
| 770 |
|
|
wb_cyc, (wb_stb)&&(gpsu_sel), wb_we, wb_addr[1:0], wb_data,
|
| 771 |
|
|
gpsu_ack, gpsu_stall, gpsu_data,
|
| 772 |
|
|
i_gps_rx, o_gps_tx, 1'b0, gps_rts_n_ignored,
|
| 773 |
|
|
gpsrx_int, gpstx_int, gpsrxf_int, gpstxf_int);
|
| 774 |
|
|
|
| 775 |
|
|
//
|
| 776 |
|
|
//
|
| 777 |
3 |
dgisselq |
// SDCard device level access
|
| 778 |
|
|
//
|
| 779 |
|
|
//
|
| 780 |
|
|
`ifdef SDCARD_ACCESS
|
| 781 |
|
|
wire [31:0] sd_dbg;
|
| 782 |
|
|
// SPI mapping
|
| 783 |
|
|
wire w_sd_cs_n, w_sd_mosi, w_sd_miso;
|
| 784 |
|
|
|
| 785 |
|
|
sdspi sdctrl(i_clk,
|
| 786 |
|
|
wb_cyc, (wb_stb)&&(sdcard_sel), wb_we,
|
| 787 |
|
|
wb_addr[1:0], wb_data,
|
| 788 |
|
|
sdcard_ack, sdcard_stall, sdcard_data,
|
| 789 |
50 |
dgisselq |
w_sd_cs_n, o_sd_sck, w_sd_mosi, w_sd_miso,
|
| 790 |
3 |
dgisselq |
sdcard_int, 1'b1, sd_dbg);
|
| 791 |
|
|
assign w_sd_miso = i_sd_data[0];
|
| 792 |
|
|
assign o_sd_data = { w_sd_cs_n, 3'b111 };
|
| 793 |
|
|
assign o_sd_cmd = w_sd_mosi;
|
| 794 |
|
|
`else
|
| 795 |
|
|
reg r_sdcard_ack;
|
| 796 |
|
|
always @(posedge i_clk)
|
| 797 |
|
|
r_sdcard_ack <= (wb_stb)&&(sdcard_sel);
|
| 798 |
|
|
assign sdcard_ack = r_sdcard_ack;
|
| 799 |
|
|
|
| 800 |
|
|
assign sdcard_data = 32'h00;
|
| 801 |
|
|
assign sdcard_stall= 1'b0;
|
| 802 |
|
|
assign sdcard_int = 1'b0;
|
| 803 |
|
|
`endif
|
| 804 |
|
|
|
| 805 |
|
|
//
|
| 806 |
|
|
//
|
| 807 |
|
|
// OLEDrgb device control
|
| 808 |
|
|
//
|
| 809 |
|
|
//
|
| 810 |
|
|
`ifdef OLEDRGB_ACCESS
|
| 811 |
27 |
dgisselq |
wboled
|
| 812 |
30 |
dgisselq |
#( .CBITS(4))// Div ck by 2^4=16, words take 200ns@81.25MHz
|
| 813 |
27 |
dgisselq |
rgbctrl(i_clk,
|
| 814 |
3 |
dgisselq |
wb_cyc, (wb_stb)&&(oled_sel), wb_we,
|
| 815 |
|
|
wb_addr[1:0], wb_data,
|
| 816 |
|
|
oled_ack, oled_stall, oled_data,
|
| 817 |
|
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
| 818 |
|
|
{ o_oled_reset_n, o_oled_vccen, o_oled_pmoden },
|
| 819 |
|
|
oled_int);
|
| 820 |
|
|
`else
|
| 821 |
|
|
assign o_oled_cs_n = 1'b1;
|
| 822 |
|
|
assign o_oled_sck = 1'b1;
|
| 823 |
|
|
assign o_oled_mosi = 1'b1;
|
| 824 |
|
|
assign o_oled_dcn = 1'b1;
|
| 825 |
|
|
assign o_oled_reset_n = 1'b0;
|
| 826 |
|
|
assign o_oled_vccen = 1'b0;
|
| 827 |
|
|
assign o_oled_pmoden = 1'b0;
|
| 828 |
|
|
|
| 829 |
|
|
reg r_oled_ack;
|
| 830 |
|
|
always @(posedge i_clk)
|
| 831 |
|
|
r_oled_ack <= (wb_stb)&&(oled_sel);
|
| 832 |
|
|
assign oled_ack = r_oled_ack;
|
| 833 |
|
|
|
| 834 |
|
|
assign oled_data = 32'h00;
|
| 835 |
|
|
assign oled_stall= 1'b0;
|
| 836 |
|
|
assign oled_int = 1'b0;
|
| 837 |
|
|
`endif
|
| 838 |
|
|
|
| 839 |
|
|
//
|
| 840 |
|
|
//
|
| 841 |
|
|
// GPS CLOCK CONTROLS, BOTH THE TEST BENCH AND THE CLOCK ITSELF
|
| 842 |
|
|
//
|
| 843 |
|
|
//
|
| 844 |
|
|
wire [63:0] gps_now, gps_err;
|
| 845 |
|
|
wire [31:0] gck_data, gtb_data;
|
| 846 |
|
|
wire gck_ack, gck_stall, gtb_ack, gtb_stall;
|
| 847 |
|
|
`ifdef GPS_CLOCK
|
| 848 |
|
|
//
|
| 849 |
|
|
// GPS CLOCK SCHOOL TESTING
|
| 850 |
|
|
//
|
| 851 |
|
|
wire gps_pps, tb_pps, gps_locked;
|
| 852 |
|
|
wire [1:0] gps_dbg_tick;
|
| 853 |
|
|
|
| 854 |
|
|
gpsclock_tb ppscktb(i_clk, ck_pps, tb_pps,
|
| 855 |
50 |
dgisselq |
(wb_stb)&&(gps_sel)&&(wb_addr[3]),
|
| 856 |
3 |
dgisselq |
wb_we, wb_addr[2:0],
|
| 857 |
|
|
wb_data, gtb_ack, gtb_stall, gtb_data,
|
| 858 |
|
|
gps_err, gps_now, gps_step);
|
| 859 |
|
|
`ifdef GPSTB
|
| 860 |
|
|
assign gps_pps = tb_pps; // Let the truth come from our test bench
|
| 861 |
|
|
`else
|
| 862 |
|
|
assign gps_pps = i_gps_pps;
|
| 863 |
|
|
`endif
|
| 864 |
|
|
wire gps_led;
|
| 865 |
|
|
|
| 866 |
|
|
//
|
| 867 |
|
|
// GPS CLOCK CONTROL
|
| 868 |
|
|
//
|
| 869 |
25 |
dgisselq |
gpsclock #(
|
| 870 |
|
|
.DEFAULT_STEP(32'h834d_c736)
|
| 871 |
|
|
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
| 872 |
50 |
dgisselq |
(wb_stb)&&(gps_sel)&&(!wb_addr[3]),
|
| 873 |
3 |
dgisselq |
wb_we, wb_addr[1:0],
|
| 874 |
|
|
wb_data, gck_ack, gck_stall, gck_data,
|
| 875 |
|
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
| 876 |
|
|
gps_dbg_tick);
|
| 877 |
|
|
`else
|
| 878 |
|
|
|
| 879 |
|
|
assign gps_err = 64'h0;
|
| 880 |
|
|
assign gps_now = 64'h0;
|
| 881 |
|
|
assign gck_data = 32'h0;
|
| 882 |
|
|
assign gtb_data = 32'h0;
|
| 883 |
|
|
assign gtb_stall = 1'b0;
|
| 884 |
|
|
assign gck_stall = 1'b0;
|
| 885 |
|
|
assign ck_pps = 1'b0;
|
| 886 |
|
|
|
| 887 |
|
|
assign gps_tracking = 1'b0;
|
| 888 |
|
|
// Appropriate step for a 200MHz clock
|
| 889 |
|
|
assign gps_step = { 16'h00, 32'h015798e, 16'h00 };
|
| 890 |
|
|
|
| 891 |
|
|
reg r_gck_ack;
|
| 892 |
|
|
always @(posedge i_clk)
|
| 893 |
|
|
r_gck_ack <= (wb_stb)&&(gps_sel);
|
| 894 |
|
|
assign gck_ack = r_gck_ack;
|
| 895 |
|
|
assign gtb_ack = r_gck_ack;
|
| 896 |
|
|
|
| 897 |
|
|
`endif
|
| 898 |
|
|
|
| 899 |
|
|
assign gps_ack = (gck_ack | gtb_ack);
|
| 900 |
|
|
assign gps_stall = (gck_stall | gtb_stall);
|
| 901 |
|
|
assign gps_data = (gck_ack) ? gck_data : gtb_data;
|
| 902 |
|
|
|
| 903 |
|
|
|
| 904 |
|
|
//
|
| 905 |
|
|
// ETHERNET DEVICE ACCESS
|
| 906 |
|
|
//
|
| 907 |
|
|
`ifdef ETHERNET_ACCESS
|
| 908 |
30 |
dgisselq |
`ifdef ENET_SCOPE
|
| 909 |
|
|
wire [31:0] txnet_data;
|
| 910 |
|
|
`endif
|
| 911 |
3 |
dgisselq |
|
| 912 |
30 |
dgisselq |
enetpackets #(12)
|
| 913 |
|
|
netctrl(i_clk, i_rst, wb_cyc,(wb_stb)&&((netp_sel)||(netb_sel)),
|
| 914 |
50 |
dgisselq |
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data, wb_sel,
|
| 915 |
30 |
dgisselq |
net_ack, net_stall, net_data,
|
| 916 |
|
|
o_net_reset_n,
|
| 917 |
|
|
i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd,
|
| 918 |
|
|
i_net_rxerr,
|
| 919 |
|
|
i_net_tx_clk, o_net_tx_en, o_net_txd,
|
| 920 |
|
|
enet_rx_int, enet_tx_int
|
| 921 |
|
|
`ifdef ENET_SCOPE
|
| 922 |
|
|
, txnet_data
|
| 923 |
|
|
`endif
|
| 924 |
|
|
);
|
| 925 |
3 |
dgisselq |
|
| 926 |
30 |
dgisselq |
wire [31:0] mdio_debug;
|
| 927 |
25 |
dgisselq |
enetctrl #(2)
|
| 928 |
30 |
dgisselq |
mdio(i_clk, i_rst, wb_cyc, (wb_stb)&&(mio_sel), wb_we,
|
| 929 |
|
|
wb_addr[4:0], wb_data[15:0],
|
| 930 |
|
|
mio_ack, mio_stall, mio_data,
|
| 931 |
|
|
o_mdclk, o_mdio, i_mdio, o_mdwe,
|
| 932 |
|
|
mdio_debug);
|
| 933 |
3 |
dgisselq |
`else
|
| 934 |
30 |
dgisselq |
reg r_mio_ack;
|
| 935 |
3 |
dgisselq |
always @(posedge i_clk)
|
| 936 |
|
|
r_mio_ack <= (wb_stb)&&(mio_sel);
|
| 937 |
|
|
assign mio_ack = r_mio_ack;
|
| 938 |
|
|
|
| 939 |
|
|
assign mio_data = 32'h00;
|
| 940 |
|
|
assign mio_stall = 1'b0;
|
| 941 |
|
|
assign enet_rx_int = 1'b0;
|
| 942 |
|
|
assign enet_tx_int = 1'b0;
|
| 943 |
|
|
|
| 944 |
|
|
//
|
| 945 |
50 |
dgisselq |
// 8kW memory, 4kW for each of transmit and receive. (Max pkt length
|
| 946 |
3 |
dgisselq |
// is 512W, so this allows for two 512W in memory.) Since we don't
|
| 947 |
|
|
// really have ethernet without ETHERNET_ACCESS defined, this just
|
| 948 |
50 |
dgisselq |
// consumes resources for us so we have an idea of what might be
|
| 949 |
3 |
dgisselq |
// available when we do have ETHERNET_ACCESS defined.
|
| 950 |
|
|
//
|
| 951 |
50 |
dgisselq |
memdev #(13) enet_buffers(i_clk, wb_cyc,
|
| 952 |
|
|
(wb_stb)&&((netb_sel)||(netp_sel)), wb_we,
|
| 953 |
|
|
wb_addr[10:0], wb_data, wb_sel, net_ack, net_stall, net_data);
|
| 954 |
3 |
dgisselq |
assign o_mdclk = 1'b1;
|
| 955 |
|
|
assign o_mdio = 1'b1;
|
| 956 |
|
|
assign o_mdwe = 1'b1;
|
| 957 |
|
|
`endif
|
| 958 |
|
|
|
| 959 |
|
|
|
| 960 |
|
|
//
|
| 961 |
|
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
| 962 |
|
|
//
|
| 963 |
|
|
`ifdef ICAPE_ACCESS
|
| 964 |
25 |
dgisselq |
wire [31:0] cfg_debug;
|
| 965 |
|
|
wbicapetwo #(.LGDIV(1)) // Divide the clock by two
|
| 966 |
|
|
fpga_cfg(i_clk, wb_cyc,(cfg_sel)&&(wb_stb), wb_we,
|
| 967 |
3 |
dgisselq |
wb_addr[4:0], wb_data,
|
| 968 |
25 |
dgisselq |
cfg_ack, cfg_stall, cfg_data, cfg_debug);
|
| 969 |
3 |
dgisselq |
`else
|
| 970 |
|
|
reg r_cfg_ack;
|
| 971 |
|
|
always @(posedge i_clk)
|
| 972 |
|
|
r_cfg_ack <= (cfg_sel)&&(wb_stb);
|
| 973 |
|
|
assign cfg_ack = r_cfg_ack;
|
| 974 |
|
|
assign cfg_stall = 1'b0;
|
| 975 |
|
|
assign cfg_data = 32'h00;
|
| 976 |
|
|
`endif
|
| 977 |
|
|
|
| 978 |
|
|
//
|
| 979 |
|
|
// RAM MEMORY ACCESS
|
| 980 |
|
|
//
|
| 981 |
|
|
// There is no option to turn this off--this RAM must always be
|
| 982 |
|
|
// present in the design.
|
| 983 |
50 |
dgisselq |
memdev #(.LGMEMSZ(17),
|
| 984 |
25 |
dgisselq |
.EXTRACLOCK(0)) // 32kW, or 128kB, 15 address lines
|
| 985 |
3 |
dgisselq |
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
| 986 |
50 |
dgisselq |
wb_data, wb_sel, mem_ack, mem_stall, mem_data);
|
| 987 |
3 |
dgisselq |
|
| 988 |
|
|
//
|
| 989 |
|
|
// FLASH MEMORY ACCESS
|
| 990 |
|
|
//
|
| 991 |
|
|
`ifdef FLASH_ACCESS
|
| 992 |
30 |
dgisselq |
// `ifdef FLASH_SCOPE
|
| 993 |
3 |
dgisselq |
wire [31:0] flash_debug;
|
| 994 |
30 |
dgisselq |
// `endif
|
| 995 |
3 |
dgisselq |
wire w_ignore_cmd_accepted;
|
| 996 |
|
|
eqspiflash flashmem(i_clk, i_rst,
|
| 997 |
|
|
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
|
| 998 |
|
|
wb_addr[21:0], wb_data,
|
| 999 |
|
|
flash_ack, flash_stall, flash_data,
|
| 1000 |
|
|
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
|
| 1001 |
|
|
flash_int, w_ignore_cmd_accepted
|
| 1002 |
30 |
dgisselq |
// `ifdef FLASH_SCOPE
|
| 1003 |
3 |
dgisselq |
, flash_debug
|
| 1004 |
30 |
dgisselq |
// `endif
|
| 1005 |
3 |
dgisselq |
);
|
| 1006 |
|
|
`else
|
| 1007 |
|
|
assign o_qspi_sck = 1'b1;
|
| 1008 |
|
|
assign o_qspi_cs_n= 1'b1;
|
| 1009 |
|
|
assign o_qspi_mod = 2'b01;
|
| 1010 |
|
|
assign o_qspi_dat = 4'h0;
|
| 1011 |
|
|
assign flash_data = 32'h00;
|
| 1012 |
|
|
assign flash_stall = 1'b0;
|
| 1013 |
|
|
assign flash_int = 1'b0;
|
| 1014 |
|
|
|
| 1015 |
|
|
reg r_flash_ack;
|
| 1016 |
|
|
always @(posedge i_clk)
|
| 1017 |
|
|
r_flash_ack <= (wb_stb)&&(flash_sel);
|
| 1018 |
|
|
assign flash_ack = r_flash_ack;
|
| 1019 |
|
|
`endif
|
| 1020 |
|
|
|
| 1021 |
|
|
|
| 1022 |
|
|
//
|
| 1023 |
|
|
//
|
| 1024 |
|
|
// DDR3-SDRAM
|
| 1025 |
|
|
//
|
| 1026 |
|
|
//
|
| 1027 |
|
|
`ifdef SDRAM_ACCESS
|
| 1028 |
50 |
dgisselq |
/*
|
| 1029 |
|
|
wire [31:0] i_ram_dbg;
|
| 1030 |
|
|
assign i_ram_dbg = 0;
|
| 1031 |
|
|
wire [1:0] o_ddr_dqs;
|
| 1032 |
|
|
wbddrsdram rami(i_clk,
|
| 1033 |
|
|
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
| 1034 |
|
|
wb_sel, ram_ack, ram_stall, ram_data,
|
| 1035 |
|
|
o_ddr_reset_n, o_ddr_cke,
|
| 1036 |
|
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
| 1037 |
|
|
o_ddr_dqs,
|
| 1038 |
|
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
| 1039 |
|
|
*/
|
| 1040 |
25 |
dgisselq |
assign o_ram_cyc = wb_cyc;
|
| 1041 |
|
|
assign o_ram_stb = (wb_stb)&&(ram_sel);
|
| 1042 |
|
|
assign o_ram_we = wb_we;
|
| 1043 |
|
|
assign o_ram_addr = wb_addr[25:0];
|
| 1044 |
|
|
assign o_ram_wdata = wb_data;
|
| 1045 |
50 |
dgisselq |
assign o_ram_sel = wb_sel;
|
| 1046 |
25 |
dgisselq |
assign ram_ack = i_ram_ack;
|
| 1047 |
|
|
assign ram_stall = i_ram_stall;
|
| 1048 |
|
|
assign ram_data = i_ram_rdata;
|
| 1049 |
|
|
assign ram_err = i_ram_err;
|
| 1050 |
|
|
/*
|
| 1051 |
|
|
migsdram rami(i_clk, i_memref_clk_200mhz, i_rst,
|
| 1052 |
3 |
dgisselq |
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
| 1053 |
25 |
dgisselq |
4'hf,
|
| 1054 |
|
|
ram_ack, ram_stall, ram_data, ram_err,
|
| 1055 |
|
|
//
|
| 1056 |
|
|
o_ddr_ck_p, o_ddr_ck_n,
|
| 1057 |
3 |
dgisselq |
o_ddr_reset_n, o_ddr_cke,
|
| 1058 |
|
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
| 1059 |
25 |
dgisselq |
o_ddr_ba, o_ddr_addr,
|
| 1060 |
|
|
o_ddr_odt, o_ddr_dm,
|
| 1061 |
|
|
io_ddr_dqs_p, io_ddr_dqs_n,
|
| 1062 |
|
|
io_ddr_data,
|
| 1063 |
|
|
ram_ready
|
| 1064 |
|
|
);
|
| 1065 |
|
|
*/
|
| 1066 |
3 |
dgisselq |
`else
|
| 1067 |
|
|
assign ram_data = 32'h00;
|
| 1068 |
|
|
assign ram_stall = 1'b0;
|
| 1069 |
|
|
reg r_ram_ack;
|
| 1070 |
|
|
always @(posedge i_clk)
|
| 1071 |
|
|
r_ram_ack <= (wb_stb)&&(ram_sel);
|
| 1072 |
|
|
assign ram_ack = r_ram_ack;
|
| 1073 |
|
|
|
| 1074 |
|
|
// And idle the DDR3 SDRAM
|
| 1075 |
|
|
assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
|
| 1076 |
|
|
assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
|
| 1077 |
|
|
// DQS
|
| 1078 |
50 |
dgisselq |
assign o_ddr_dqs = 2'b11; // Leave DQS pins in high impedence
|
| 1079 |
3 |
dgisselq |
// DDR3 control wires (not enabled if CKE=0)
|
| 1080 |
|
|
assign o_ddr_cs_n = 1'b0; // NOOP command
|
| 1081 |
|
|
assign o_ddr_ras_n = 1'b1;
|
| 1082 |
|
|
assign o_ddr_cas_n = 1'b1;
|
| 1083 |
|
|
assign o_ddr_we_n = 1'b1;
|
| 1084 |
|
|
// (Unused) data wires
|
| 1085 |
|
|
assign o_ddr_addr = 14'h00;
|
| 1086 |
|
|
assign o_ddr_ba = 3'h0;
|
| 1087 |
50 |
dgisselq |
assign o_ddr_data = 16'h00;
|
| 1088 |
3 |
dgisselq |
`endif
|
| 1089 |
|
|
|
| 1090 |
|
|
|
| 1091 |
|
|
//
|
| 1092 |
|
|
//
|
| 1093 |
|
|
// WISHBONE SCOPES
|
| 1094 |
|
|
//
|
| 1095 |
|
|
//
|
| 1096 |
|
|
//
|
| 1097 |
|
|
//
|
| 1098 |
|
|
wire [31:0] scop_a_data;
|
| 1099 |
|
|
wire scop_a_ack, scop_a_stall, scop_a_interrupt;
|
| 1100 |
|
|
`ifdef CPU_SCOPE
|
| 1101 |
|
|
wire [31:0] scop_cpu_data;
|
| 1102 |
|
|
wire scop_cpu_ack, scop_cpu_stall, scop_cpu_interrupt;
|
| 1103 |
|
|
wire scop_cpu_trigger;
|
| 1104 |
30 |
dgisselq |
assign scop_cpu_trigger = (zip_scope_data[31]);
|
| 1105 |
|
|
wbscope #( .LGMEM(5'd13),
|
| 1106 |
|
|
.DEFAULT_HOLDOFF(32))
|
| 1107 |
|
|
cpuscope(i_clk, 1'b1,(scop_cpu_trigger),zip_scope_data,
|
| 1108 |
|
|
// Wishbone interface
|
| 1109 |
|
|
i_clk, wb_cyc,
|
| 1110 |
|
|
((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
| 1111 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1112 |
|
|
scop_cpu_ack, scop_cpu_stall, scop_cpu_data,
|
| 1113 |
|
|
scop_cpu_interrupt);
|
| 1114 |
3 |
dgisselq |
|
| 1115 |
|
|
assign scop_a_data = scop_cpu_data;
|
| 1116 |
|
|
assign scop_a_ack = scop_cpu_ack;
|
| 1117 |
|
|
assign scop_a_stall = scop_cpu_stall;
|
| 1118 |
|
|
assign scop_a_interrupt = scop_cpu_interrupt;
|
| 1119 |
|
|
`else
|
| 1120 |
|
|
`ifdef FLASH_SCOPE
|
| 1121 |
|
|
wire [31:0] scop_flash_data;
|
| 1122 |
|
|
wire scop_flash_ack, scop_flash_stall, scop_flash_interrupt;
|
| 1123 |
|
|
wire scop_flash_trigger;
|
| 1124 |
|
|
assign scop_flash_trigger = (wb_stb)&&((flash_sel)||(flctl_sel));
|
| 1125 |
30 |
dgisselq |
wbscope #(5'd11) flashscope(i_clk, 1'b1,
|
| 1126 |
3 |
dgisselq |
(scop_flash_trigger), flash_debug,
|
| 1127 |
|
|
// Wishbone interface
|
| 1128 |
25 |
dgisselq |
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b00)),
|
| 1129 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1130 |
3 |
dgisselq |
scop_flash_ack, scop_flash_stall, scop_flash_data,
|
| 1131 |
|
|
scop_flash_interrupt);
|
| 1132 |
|
|
|
| 1133 |
|
|
assign scop_a_data = scop_flash_data;
|
| 1134 |
|
|
assign scop_a_ack = scop_flash_ack;
|
| 1135 |
|
|
assign scop_a_stall = scop_flash_stall;
|
| 1136 |
|
|
assign scop_a_interrupt = scop_flash_interrupt;
|
| 1137 |
|
|
`else
|
| 1138 |
|
|
reg r_scop_a_ack;
|
| 1139 |
|
|
always @(posedge i_clk)
|
| 1140 |
|
|
r_scop_a_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b00);
|
| 1141 |
|
|
assign scop_a_data = 32'h00;
|
| 1142 |
|
|
assign scop_a_ack = r_scop_a_ack;
|
| 1143 |
|
|
assign scop_a_stall = 1'b0;
|
| 1144 |
|
|
assign scop_a_interrupt = 1'b0;
|
| 1145 |
|
|
`endif
|
| 1146 |
|
|
`endif
|
| 1147 |
|
|
|
| 1148 |
|
|
wire [31:0] scop_b_data;
|
| 1149 |
|
|
wire scop_b_ack, scop_b_stall, scop_b_interrupt;
|
| 1150 |
|
|
`ifdef GPS_SCOPE
|
| 1151 |
|
|
reg [18:0] r_gps_debug;
|
| 1152 |
|
|
wire [31:0] scop_gps_data;
|
| 1153 |
|
|
wire scop_gps_ack, scop_gps_stall, scop_gps_interrupt;
|
| 1154 |
|
|
always @(posedge i_clk)
|
| 1155 |
|
|
r_gps_debug <= {
|
| 1156 |
|
|
gps_dbg_tick, gps_tracking, gps_locked,
|
| 1157 |
|
|
gpu_data[7:0],
|
| 1158 |
|
|
// (wb_cyc)&&(wb_stb)&&(io_sel),
|
| 1159 |
|
|
(wb_stb)&&(io_sel)&&(wb_addr[4:3]==2'b11)&&(wb_we),
|
| 1160 |
|
|
(wb_stb)&&(gps_sel)&&(wb_addr[3:2]==2'b01),
|
| 1161 |
|
|
gpu_int,
|
| 1162 |
|
|
i_gps_rx, rtc_pps, ck_pps, i_gps_pps };
|
| 1163 |
|
|
wbscopc #(5'd13,19,32,1) gpsscope(i_clk, 1'b1, ck_pps, r_gps_debug,
|
| 1164 |
|
|
// Wishbone interface
|
| 1165 |
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
| 1166 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1167 |
|
|
scop_gps_ack, scop_gps_stall, scop_gps_data,
|
| 1168 |
|
|
scop_gps_interrupt);
|
| 1169 |
25 |
dgisselq |
|
| 1170 |
|
|
assign scop_b_ack = scop_gps_ack;
|
| 1171 |
|
|
assign scop_b_stall = scop_gps_stall;
|
| 1172 |
|
|
assign scop_b_data = scop_gps_data;
|
| 1173 |
|
|
assign scop_b_interrupt = scop_gps_interrupt;
|
| 1174 |
3 |
dgisselq |
`else
|
| 1175 |
25 |
dgisselq |
`ifdef CFG_SCOPE
|
| 1176 |
|
|
wire [31:0] scop_cfg_data;
|
| 1177 |
|
|
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
|
| 1178 |
|
|
wire [31:0] cfg_debug_2;
|
| 1179 |
|
|
assign cfg_debug_2 = {
|
| 1180 |
|
|
wb_ack, cfg_debug[30:17], slow_ack,
|
| 1181 |
|
|
slow_data[7:0], wb_data[7:0]
|
| 1182 |
|
|
};
|
| 1183 |
|
|
wbscope #(5'd8,32,1) cfgscope(i_clk, 1'b1, (cfg_sel)&&(wb_stb),
|
| 1184 |
|
|
cfg_debug_2,
|
| 1185 |
|
|
// Wishbone interface
|
| 1186 |
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
| 1187 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1188 |
|
|
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
|
| 1189 |
|
|
scop_cfg_interrupt);
|
| 1190 |
|
|
|
| 1191 |
|
|
assign scop_b_data = scop_cfg_data;
|
| 1192 |
|
|
assign scop_b_stall = scop_cfg_stall;
|
| 1193 |
|
|
assign scop_b_ack = scop_cfg_ack;
|
| 1194 |
|
|
assign scop_b_interrupt = scop_cfg_interrupt;
|
| 1195 |
|
|
`else
|
| 1196 |
30 |
dgisselq |
`ifdef WBU_SCOPE
|
| 1197 |
|
|
wire [31:0] scop_wbu_data;
|
| 1198 |
|
|
wire scop_wbu_ack, scop_wbu_stall, scop_wbu_interrupt;
|
| 1199 |
|
|
wbscope #(5'd10,32,1) wbuscope(i_clk, 1'b1, (flash_sel)&&(wb_stb),
|
| 1200 |
|
|
wbu_debug,
|
| 1201 |
|
|
// Wishbone interface
|
| 1202 |
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
|
| 1203 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1204 |
|
|
scop_wbu_ack, scop_wbu_stall, scop_wbu_data,
|
| 1205 |
|
|
scop_wbu_interrupt);
|
| 1206 |
|
|
|
| 1207 |
|
|
assign scop_b_data = scop_wbu_data;
|
| 1208 |
|
|
assign scop_b_stall = scop_wbu_stall;
|
| 1209 |
|
|
assign scop_b_ack = scop_wbu_ack;
|
| 1210 |
|
|
assign scop_b_interrupt = scop_wbu_interrupt;
|
| 1211 |
|
|
`else
|
| 1212 |
3 |
dgisselq |
assign scop_b_data = 32'h00;
|
| 1213 |
|
|
assign scop_b_stall = 1'b0;
|
| 1214 |
|
|
assign scop_b_interrupt = 1'b0;
|
| 1215 |
|
|
|
| 1216 |
|
|
reg r_scop_b_ack;
|
| 1217 |
|
|
always @(posedge i_clk)
|
| 1218 |
|
|
r_scop_b_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b01);
|
| 1219 |
|
|
assign scop_b_ack = r_scop_b_ack;
|
| 1220 |
|
|
`endif
|
| 1221 |
25 |
dgisselq |
`endif
|
| 1222 |
30 |
dgisselq |
`endif
|
| 1223 |
3 |
dgisselq |
|
| 1224 |
|
|
//
|
| 1225 |
|
|
// SCOPE C
|
| 1226 |
|
|
//
|
| 1227 |
|
|
wire [31:0] scop_c_data;
|
| 1228 |
|
|
wire scop_c_ack, scop_c_stall, scop_c_interrupt;
|
| 1229 |
|
|
//
|
| 1230 |
25 |
dgisselq |
`ifdef SDRAM_SCOPE
|
| 1231 |
|
|
wire [31:0] scop_sdram_data;
|
| 1232 |
|
|
wire scop_sdram_ack, scop_sdram_stall, scop_sdram_interrupt;
|
| 1233 |
|
|
wire sdram_trigger;
|
| 1234 |
|
|
wire [31:0] sdram_debug;
|
| 1235 |
|
|
assign sdram_trigger = (ram_sel)&&(wb_stb);
|
| 1236 |
|
|
assign sdram_debug= i_ram_dbg;
|
| 1237 |
|
|
|
| 1238 |
32 |
dgisselq |
wbscope #(5'd9,32,1)
|
| 1239 |
|
|
ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
|
| 1240 |
|
|
// Wishbone interface
|
| 1241 |
|
|
i_clk, wb_cyc,
|
| 1242 |
|
|
((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
|
| 1243 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1244 |
25 |
dgisselq |
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
|
| 1245 |
32 |
dgisselq |
scop_sdram_interrupt);
|
| 1246 |
25 |
dgisselq |
|
| 1247 |
|
|
assign scop_c_ack = scop_sdram_ack;
|
| 1248 |
|
|
assign scop_c_stall = scop_sdram_stall;
|
| 1249 |
|
|
assign scop_c_data = scop_sdram_data;
|
| 1250 |
|
|
assign scop_c_interrupt = scop_sdram_interrupt;
|
| 1251 |
|
|
`else
|
| 1252 |
3 |
dgisselq |
assign scop_c_data = 32'h00;
|
| 1253 |
|
|
assign scop_c_stall = 1'b0;
|
| 1254 |
|
|
assign scop_c_interrupt = 1'b0;
|
| 1255 |
|
|
|
| 1256 |
|
|
reg r_scop_c_ack;
|
| 1257 |
|
|
always @(posedge i_clk)
|
| 1258 |
|
|
r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
|
| 1259 |
|
|
assign scop_c_ack = r_scop_c_ack;
|
| 1260 |
25 |
dgisselq |
`endif
|
| 1261 |
3 |
dgisselq |
|
| 1262 |
|
|
//
|
| 1263 |
|
|
// SCOPE D
|
| 1264 |
|
|
//
|
| 1265 |
|
|
wire [31:0] scop_d_data;
|
| 1266 |
|
|
wire scop_d_ack, scop_d_stall, scop_d_interrupt;
|
| 1267 |
|
|
//
|
| 1268 |
30 |
dgisselq |
`ifdef ENET_SCOPE
|
| 1269 |
|
|
wire [31:0] scop_net_data;
|
| 1270 |
|
|
wire scop_net_ack, scop_net_stall, scop_net_interrupt;
|
| 1271 |
|
|
|
| 1272 |
|
|
/*
|
| 1273 |
|
|
wbscope #(5'd8,32,1)
|
| 1274 |
|
|
net_scope(i_clk, 1'b1, !mdio_debug[1], mdio_debug,
|
| 1275 |
|
|
// Wishbone interface
|
| 1276 |
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)),
|
| 1277 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1278 |
|
|
scop_net_ack, scop_net_stall, scop_net_data,
|
| 1279 |
|
|
scop_net_interrupt);
|
| 1280 |
|
|
*/
|
| 1281 |
|
|
|
| 1282 |
|
|
// 5'd8 is sufficient for small packets, and indeed the minimum for
|
| 1283 |
|
|
// watching any packets--as the minimum packet size is 64 bytes, or
|
| 1284 |
|
|
// 128 nibbles.
|
| 1285 |
|
|
wbscope #(5'd9,32,0)
|
| 1286 |
|
|
net_scope(i_net_rx_clk, 1'b1, txnet_data[31], txnet_data,
|
| 1287 |
|
|
// Wishbone interface
|
| 1288 |
|
|
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)),
|
| 1289 |
|
|
wb_we, wb_addr[0], wb_data,
|
| 1290 |
|
|
scop_net_ack, scop_net_stall, scop_net_data,
|
| 1291 |
|
|
scop_net_interrupt);
|
| 1292 |
|
|
|
| 1293 |
|
|
assign scop_d_ack = scop_net_ack;
|
| 1294 |
|
|
assign scop_d_stall = scop_net_stall;
|
| 1295 |
|
|
assign scop_d_data = scop_net_data;
|
| 1296 |
|
|
assign scop_d_interrupt = scop_net_interrupt;
|
| 1297 |
|
|
`else
|
| 1298 |
3 |
dgisselq |
assign scop_d_data = 32'h00;
|
| 1299 |
|
|
assign scop_d_stall = 1'b0;
|
| 1300 |
|
|
assign scop_d_interrupt = 1'b0;
|
| 1301 |
|
|
|
| 1302 |
|
|
reg r_scop_d_ack;
|
| 1303 |
|
|
always @(posedge i_clk)
|
| 1304 |
|
|
r_scop_d_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b11);
|
| 1305 |
|
|
assign scop_d_ack = r_scop_d_ack;
|
| 1306 |
30 |
dgisselq |
`endif
|
| 1307 |
3 |
dgisselq |
|
| 1308 |
25 |
dgisselq |
reg all_scope_interrupts;
|
| 1309 |
|
|
always @(posedge i_clk)
|
| 1310 |
|
|
all_scope_interrupts <= (scop_a_interrupt)
|
| 1311 |
|
|
|| (scop_b_interrupt)
|
| 1312 |
|
|
|| (scop_c_interrupt)
|
| 1313 |
|
|
|| (scop_d_interrupt);
|
| 1314 |
|
|
assign scop_int = all_scope_interrupts;
|
| 1315 |
|
|
|
| 1316 |
|
|
// Scopes don't stall, so this line is more formality than anything
|
| 1317 |
|
|
// else.
|
| 1318 |
3 |
dgisselq |
assign scop_stall = ((wb_addr[2:1]==2'b0)?scop_a_stall
|
| 1319 |
|
|
: ((wb_addr[2:1]==2'b01)?scop_b_stall
|
| 1320 |
25 |
dgisselq |
: ((wb_addr[2:1]==2'b10)?scop_c_stall
|
| 1321 |
3 |
dgisselq |
: scop_d_stall))); // Will always be 1'b0;
|
| 1322 |
|
|
initial scop_ack = 1'b0;
|
| 1323 |
|
|
always @(posedge i_clk)
|
| 1324 |
|
|
scop_ack <= scop_a_ack | scop_b_ack | scop_c_ack | scop_d_ack;
|
| 1325 |
|
|
always @(posedge i_clk)
|
| 1326 |
|
|
if (scop_a_ack)
|
| 1327 |
|
|
scop_data <= scop_a_data;
|
| 1328 |
|
|
else if (scop_b_ack)
|
| 1329 |
|
|
scop_data <= scop_b_data;
|
| 1330 |
|
|
else if (scop_c_ack)
|
| 1331 |
|
|
scop_data <= scop_c_data;
|
| 1332 |
|
|
else // if (scop_d_ack)
|
| 1333 |
|
|
scop_data <= scop_d_data;
|
| 1334 |
|
|
|
| 1335 |
|
|
endmodule
|
