OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [cpu/] [pipefetch.v] - Blame information for rev 50

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    pipefetch.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
8
//              with no stalls, can be quite a chore.  Worse, the Wishbone
9
//              takes a couple of cycles just to read one instruction from
10
//              the bus.  However, if we use pipeline accesses to the Wishbone
11
//              bus, then we can read more and faster.  Further, if we cache
12
//              these results so that we have them before we need them, then
13
//              we have a chance of keeping our CPU from stalling.  Those are
14
//              the purposes of this instruction fetch module: 1) Pipeline
15
//              wishbone accesses, and 2) an instruction cache.
16
//
17
//      20150919 -- Fixed a nasty race condition whereby the pipefetch routine
18
//              would produce either the same instruction twice, or skip
19
//              an instruction.  This condition was dependent on the CPU stall
20
//              condition, and would only take place if the pipeline wasn't 
21
//              completely full throughout the stall.
22
//
23
//              Interface support was also added for trapping on illegal
24
//              instructions (i.e., instruction fetches that cause bus errors),
25
//              however the internal interface has not caught up to supporting
26
//              these exceptions yet.
27
//
28
// Creator:     Dan Gisselquist, Ph.D.
29
//              Gisselquist Technology, LLC
30
//
31
////////////////////////////////////////////////////////////////////////////////
32
//
33 50 dgisselq
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
34 3 dgisselq
//
35
// This program is free software (firmware): you can redistribute it and/or
36
// modify it under the terms of  the GNU General Public License as published
37
// by the Free Software Foundation, either version 3 of the License, or (at
38
// your option) any later version.
39
//
40
// This program is distributed in the hope that it will be useful, but WITHOUT
41
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
42
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
43
// for more details.
44
//
45 50 dgisselq
// You should have received a copy of the GNU General Public License along
46
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
47
// target there if the PDF file isn't present.)  If not, see
48
// <http://www.gnu.org/licenses/> for a copy.
49
//
50 3 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
51
//              http://www.gnu.org/licenses/gpl.html
52
//
53
//
54
////////////////////////////////////////////////////////////////////////////////
55
//
56 50 dgisselq
//
57 3 dgisselq
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
58
                        o_i, o_pc, o_v,
59
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
60
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
61
                        o_illegal);
62
        parameter       RESET_ADDRESS=32'h0010_0000,
63
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
64
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
65
        input                           i_clk, i_rst, i_new_pc,
66
                                        i_clear_cache, i_stall_n;
67
        input           [(AW-1):0]       i_pc;
68
        output  reg     [(BUSW-1):0]     o_i;
69
        output  reg     [(AW-1):0]       o_pc;
70
        output  wire                    o_v;
71
        //
72
        output  reg             o_wb_cyc, o_wb_stb;
73
        output  wire            o_wb_we;
74
        output  reg     [(AW-1):0]       o_wb_addr;
75
        output  wire    [(BUSW-1):0]     o_wb_data;
76
        //
77
        input                   i_wb_ack, i_wb_stall, i_wb_err;
78
        input           [(BUSW-1):0]     i_wb_data;
79
        //
80
        // Is the (data) memory unit also requesting access to the bus?
81
        input                           i_wb_request;
82
        output  wire                    o_illegal;
83
 
84
        // Fixed bus outputs: we read from the bus only, never write.
85
        // Thus the output data is ... irrelevant and don't care.  We set it
86
        // to zero just to set it to something.
87
        assign  o_wb_we = 1'b0;
88
        assign  o_wb_data = 0;
89
 
90
        reg     [(AW-1):0]               r_cache_base;
91
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
92
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
93
 
94
        wire    [(LGCACHELEN-1):0]       w_cache_offset;
95
        reg     [1:0]                    r_cache_offset;
96
 
97
        reg                     r_addr_set;
98
        reg     [(AW-1):0]       r_addr;
99
 
100
        wire    [(AW-1):0]       bus_nvalid;
101
        assign  bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
102
 
103
        // What are some of the conditions for which we need to restart the
104
        // cache?
105
        wire    w_pc_out_of_bounds;
106
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
107
                                        ||(i_pc < r_cache_base)
108
                                        ||(i_pc >= r_cache_base + CACHELEN)
109
                                        ||(i_pc >= r_cache_base + bus_nvalid+5)));
110
        wire    w_ran_off_end_of_cache;
111
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
112
                                        ||(r_addr >= r_cache_base + CACHELEN)
113
                                        ||(r_addr >= r_cache_base + bus_nvalid+5)));
114
        wire    w_running_out_of_cache;
115
        assign  w_running_out_of_cache = (r_addr_set)
116
                        &&(r_addr >= r_cache_base +
117
                                // {{(AW-LGCACHELEN-1),{1'b0}},2'b11,
118
                                //              {(LGCACHELEN-1){1'b0}}})
119
                                // (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
120
                                +(3<<(LGCACHELEN-2)))
121
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
122
 
123
        initial r_cache_base = RESET_ADDRESS;
124
        always @(posedge i_clk)
125
        begin
126
                if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
127
                begin
128
                        o_wb_cyc <= 1'b0;
129
                        o_wb_stb <= 1'b0;
130
                        // r_cache_base <= RESET_ADDRESS;
131
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
132
                //              &&(i_pc >= r_cache_base)
133
                //              &&(i_pc < r_cache_base + bus_nvalid))
134
                // begin
135
                        // The new instruction is in our cache, do nothing
136
                        // with the bus here.
137
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
138
                begin
139
                        // We need to abandon our bus action to start over in
140
                        // a new region, setting up a new cache.  This may
141
                        // happen mid cycle while waiting for a result.  By
142
                        // dropping o_wb_cyc, we state that we are no longer
143
                        // interested in that result--whatever it might be.
144
                        o_wb_cyc <= 1'b0;
145
                        o_wb_stb <= 1'b0;
146
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
147
                begin
148
                        // Restart a bus cycle that was interrupted when the
149
                        // data section wanted access to our bus.
150
                        o_wb_cyc <= 1'b1;
151
                        o_wb_stb <= 1'b1;
152
                        // o_wb_addr <= r_cache_base + bus_nvalid;
153
                end else if ((~o_wb_cyc)&&(
154
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
155
                begin
156
                        // Start a bus transaction
157
                        o_wb_cyc <= 1'b1;
158
                        o_wb_stb <= 1'b1;
159
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
160
                        // r_nvalid <= 0;
161
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
162
                        // w_cache_offset <= 0;
163
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
164
                begin
165
                        // If we're using the last quarter of the cache, then
166
                        // let's start a bus transaction to extend the cache.
167
                        o_wb_cyc <= 1'b1;
168
                        o_wb_stb <= 1'b1;
169
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
170
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
171
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
172
                        // w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));
173
                end else if (o_wb_cyc)
174
                begin
175
                        // This handles everything ... but the case where
176
                        // while reading we need to extend our cache.
177
                        if ((o_wb_stb)&&(~i_wb_stall))
178
                        begin
179
                                // o_wb_addr <= o_wb_addr + 1;
180
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
181
                                        ||(i_wb_request))
182
                                        o_wb_stb <= 1'b0;
183
                        end
184
 
185
                        if (i_wb_ack)
186
                        begin
187
                                // r_nvalid <= r_nvalid + 1;
188
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
189
                                        o_wb_cyc <= 1'b0;
190
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
191
                                o_wb_cyc <= 1'b0;
192
                end
193
        end
194
 
195
 
196
        initial r_nvalid = 0;
197
        always @(posedge i_clk)
198
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
199
                        r_nvalid <= 0;
200
                else if ((~o_wb_cyc)&&(
201
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
202
                        r_nvalid <= 0;
203
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
204
                        r_nvalid[LGCACHELEN:(LGCACHELEN-2)]
205
                                <= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;
206
                                        // i.e.  - (1<<(LGCACHELEN-2));
207
                else if ((o_wb_cyc)&&(i_wb_ack))
208
                        r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;
209
 
210
        always @(posedge i_clk)
211
                if (i_clear_cache)
212
                        r_cache_base <= i_pc;
213
                else if ((~o_wb_cyc)&&(
214
                                (w_pc_out_of_bounds)
215
                                ||(w_ran_off_end_of_cache)))
216
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
217
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
218
                        r_cache_base[(AW-1):(LGCACHELEN-2)]
219
                                <= r_cache_base[(AW-1):(LGCACHELEN-2)]
220
                                        + {{(AW-LGCACHELEN+1){1'b0}},1'b1};
221
                                        // i.e.  + (1<<(LGCACHELEN-2));
222
 
223
        always @(posedge i_clk)
224
                if (i_clear_cache)
225
                        r_cache_offset <= 0;
226
                else if ((~o_wb_cyc)&&(
227
                                (w_pc_out_of_bounds)
228
                                ||(w_ran_off_end_of_cache)))
229
                        r_cache_offset <= 0;
230
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
231
                        r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;
232
        assign  w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };
233
 
234
        always @(posedge i_clk)
235
                if (i_clear_cache)
236
                        o_wb_addr <= i_pc;
237
                else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
238
                begin
239
                        if (i_wb_ack)
240
                                o_wb_addr <= r_cache_base + bus_nvalid+1;
241
                        else
242
                                o_wb_addr <= r_cache_base + bus_nvalid;
243
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
244
                                        ||(w_ran_off_end_of_cache)))
245
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
246
                else if ((o_wb_stb)&&(~i_wb_stall))     // && o_wb_cyc
247
                        o_wb_addr <= o_wb_addr + 1;
248
 
249
        initial r_acks_waiting = 0;
250
        always @(posedge i_clk)
251
                if (~o_wb_cyc)
252
                        r_acks_waiting <= 0;
253
                // o_wb_cyc *must* be true for all following
254
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
255
                        r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
256
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
257
                        r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
258
 
259
        always @(posedge i_clk)
260
                if ((o_wb_cyc)&&(i_wb_ack))
261
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
262
                                        <= i_wb_data;
263
 
264
        initial r_addr_set = 1'b0;
265
        always @(posedge i_clk)
266
                if ((i_rst)||(i_new_pc))
267
                        r_addr_set <= 1'b1;
268
                else if (i_clear_cache)
269
                        r_addr_set <= 1'b0;
270
 
271
        // Now, read from the cache
272
        wire    w_cv;   // Cache valid, address is in the cache
273
        reg     r_cv;
274
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
275
                        &&(r_addr-r_cache_base < bus_nvalid));
276
        always @(posedge i_clk)
277
                r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
278
        assign  o_v = (r_cv)&&(~i_new_pc);
279
 
280
        always @(posedge i_clk)
281
                if (i_new_pc)
282
                        r_addr <= i_pc;
283
                else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
284
                        r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};
285
 
286
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
287
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
288
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;
289
        always @(posedge i_clk)
290
                if ((~o_v)||((i_stall_n)&&(o_v)))
291
                        o_i <= cache[c_rdaddr];
292
        always @(posedge i_clk)
293
                if ((~o_v)||((i_stall_n)&&(o_v)))
294
                        o_pc <= r_addr;
295
 
296
        reg     [(AW-1):0]       ill_address;
297
        initial ill_address = 0;
298
        always @(posedge i_clk)
299
                if ((o_wb_cyc)&&(i_wb_err))
300
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
301
 
302
        assign  o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
303
 
304
 
305
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.