OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [cpu/] [zipcounter.v] - Blame information for rev 50

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 3 dgisselq
//
3
// Filename:    zipcounter.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:
8
//              A very, _very_ simple counter.  It's purpose doesn't really
9
//      include rollover, but it will interrupt on rollover.  It can be set,
10
//      although my design concept is that it can be reset.  It cannot be
11
//      halted.  It will always produce interrupts--whether or not they are 
12
//      handled interrupts is another question--that's up to the interrupt
13
//      controller.
14
//
15
//      My intention is to use this counter for process accounting: I should
16
//      be able to use this to count clock ticks of processor time assigned to
17
//      each task by resetting the counter at the beginning of every task
18
//      interval, and reading the result at the end of the interval.  As long
19
//      as the interval is less than 2^32 clocks, there should be no problem.
20
//      Similarly, this can be used to measure CPU wishbone bus stalls, 
21
//      prefetch stalls, or other CPU stalls (i.e. stalling as part of a JMP
22
//      instruction, or a read from the condition codes following a write).
23
//
24
//
25
// Creator:     Dan Gisselquist, Ph.D.
26
//              Gisselquist Technology, LLC
27
//
28 50 dgisselq
////////////////////////////////////////////////////////////////////////////////
29 3 dgisselq
//
30 50 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
31 3 dgisselq
//
32
// This program is free software (firmware): you can redistribute it and/or
33
// modify it under the terms of  the GNU General Public License as published
34
// by the Free Software Foundation, either version 3 of the License, or (at
35
// your option) any later version.
36
//
37
// This program is distributed in the hope that it will be useful, but WITHOUT
38
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
39
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
40
// for more details.
41
//
42 50 dgisselq
// You should have received a copy of the GNU General Public License along
43
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
44
// target there if the PDF file isn't present.)  If not, see
45
// <http://www.gnu.org/licenses/> for a copy.
46
//
47 3 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
48
//              http://www.gnu.org/licenses/gpl.html
49
//
50
//
51 50 dgisselq
////////////////////////////////////////////////////////////////////////////////
52 3 dgisselq
//
53 50 dgisselq
//
54 3 dgisselq
module  zipcounter(i_clk, i_ce,
55
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
56
                        o_wb_ack, o_wb_stall, o_wb_data,
57
                o_int);
58
        parameter       BW = 32;
59
        input                           i_clk, i_ce;
60
        // Wishbone inputs
61
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
62
        input           [(BW-1):0]       i_wb_data;
63
        // Wishbone outputs
64
        output  reg                     o_wb_ack;
65
        output  wire                    o_wb_stall;
66
        output  reg     [(BW-1):0]       o_wb_data;
67
        // Interrupt line
68
        output  reg                     o_int;
69
 
70
        initial o_int = 0;
71
        initial o_wb_data = 32'h00;
72
        always @(posedge i_clk)
73 32 dgisselq
                if ((i_wb_stb)&&(i_wb_we))
74 3 dgisselq
                        { o_int, o_wb_data } <= { 1'b0, i_wb_data };
75
                else if (i_ce)
76
                        { o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
77
                else
78
                        o_int <= 1'b0;
79
 
80
        initial o_wb_ack = 1'b0;
81
        always @(posedge i_clk)
82 32 dgisselq
                o_wb_ack <= (i_wb_stb);
83 3 dgisselq
        assign  o_wb_stall = 1'b0;
84
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.