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dgisselq |
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zipcpu.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: This is the top level module holding the core of the Zip CPU
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// together. The Zip CPU is designed to be as simple as possible.
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// (actual implementation aside ...) The instruction set is about as
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// RISC as you can get, there are only 16 instruction types supported.
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// Please see the accompanying spec.pdf file for a description of these
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// instructions.
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//
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// All instructions are 32-bits wide. All bus accesses, both address and
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// data, are 32-bits over a wishbone bus.
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//
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// The Zip CPU is fully pipelined with the following pipeline stages:
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//
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// 1. Prefetch, returns the instruction from memory.
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//
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// 2. Instruction Decode
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//
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// 3. Read Operands
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//
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// 4. Apply Instruction
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//
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// 4. Write-back Results
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//
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// Further information about the inner workings of this CPU may be
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// found in the spec.pdf file. (The documentation within this file
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// had become out of date and out of sync with the spec.pdf, so look
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// to the spec.pdf for accurate and up to date information.)
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//
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//
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// In general, the pipelining is controlled by three pieces of logic
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// per stage: _ce, _stall, and _valid. _valid means that the stage
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// holds a valid instruction. _ce means that the instruction from the
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// previous stage is to move into this one, and _stall means that the
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// instruction from the previous stage may not move into this one.
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// The difference between these control signals allows individual stages
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// to propagate instructions independently. In general, the logic works
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// as:
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//
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//
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// assign (n)_ce = (n-1)_valid && (~(n)_stall)
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//
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//
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// always @(posedge i_clk)
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// if ((i_rst)||(clear_pipeline))
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// (n)_valid = 0
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// else if (n)_ce
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// (n)_valid = 1
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// else if (n+1)_ce
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// (n)_valid = 0
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//
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// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
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// || ( (n)_valid && (n+1)_stall );
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//
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// and ...
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//
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// always @(posedge i_clk)
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// if (n)_ce
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// (n)_variable = ... whatever logic for this stage
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//
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// Note that a stage can stall even if no instruction is loaded into
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// it.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// We can either pipeline our fetches, or issue one fetch at a time. Pipelined
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// fetches are more complicated and therefore use more FPGA resources, while
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// single fetches will cause the CPU to stall for about 5 stalls each
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// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2. However, the area cost may be worth it. Consider:
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//
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// Slice LUTs ZipSystem ZipCPU
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// Single Fetching 2521 1734
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// Pipelined fetching 2796 2046
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//
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//
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//
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`define CPU_CC_REG 4'he
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`define CPU_PC_REG 4'hf
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`define CPU_CLRCACHE_BIT 14 // Floating point error flag, set on error
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`define CPU_PHASE_BIT 13 // Floating point error flag, set on error
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`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
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`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
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`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
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`define CPU_TRAP_BIT 9 // User TRAP has taken place
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`define CPU_ILL_BIT 8 // Illegal instruction
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`define CPU_BREAK_BIT 7
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`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT 5
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`define CPU_SLEEP_BIT 4
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// Compile time defines
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//
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`include "cpudefs.v"
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//
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//
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module zipcpu(i_clk, i_rst, i_interrupt,
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// Debug interface
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i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
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o_dbg_stall, o_dbg_reg, o_dbg_cc,
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o_break,
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// CPU interface to the wishbone bus
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o_wb_gbl_cyc, o_wb_gbl_stb,
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o_wb_lcl_cyc, o_wb_lcl_stb,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data,
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i_wb_err,
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// Accounting/CPU usage interface
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o_op_stall, o_pf_stall, o_i_count
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`ifdef DEBUG_SCOPE
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, o_debug
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`endif
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);
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parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
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LGICACHE=6;
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`ifdef OPT_MULTIPLY
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parameter IMPLEMENT_MPY = `OPT_MULTIPLY;
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`else
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parameter IMPLEMENT_MPY = 0;
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`endif
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`ifdef OPT_DIVIDE
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parameter IMPLEMENT_DIVIDE = 1;
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`else
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parameter IMPLEMENT_DIVIDE = 0;
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`endif
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`ifdef OPT_IMPLEMENT_FPU
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parameter IMPLEMENT_FPU = 1,
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`else
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parameter IMPLEMENT_FPU = 0,
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`endif
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IMPLEMENT_LOCK=1;
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`ifdef OPT_EARLY_BRANCHING
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parameter EARLY_BRANCHING = 1;
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`else
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parameter EARLY_BRANCHING = 0;
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`endif
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parameter AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_interrupt;
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// Debug interface -- inputs
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input i_halt, i_clear_pf_cache;
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input [4:0] i_dbg_reg;
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input i_dbg_we;
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input [31:0] i_dbg_data;
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// Debug interface -- outputs
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output wire o_dbg_stall;
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output reg [31:0] o_dbg_reg;
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output reg [3:0] o_dbg_cc;
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output wire o_break;
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// Wishbone interface -- outputs
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output wire o_wb_gbl_cyc, o_wb_gbl_stb;
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output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
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output wire [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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// Wishbone interface -- inputs
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input i_wb_ack, i_wb_stall;
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input [31:0] i_wb_data;
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input i_wb_err;
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// Accounting outputs ... to help us count stalls and usage
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output wire o_op_stall;
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output wire o_pf_stall;
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output wire o_i_count;
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//
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`ifdef DEBUG_SCOPE
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output reg [31:0] o_debug;
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`endif
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// Registers
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//
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// The distributed RAM style comment is necessary on the
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// SPARTAN6 with XST to prevent XST from oversimplifying the register
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// set and in the process ruining everything else. It basically
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// optimizes logic away, to where it no longer works. The logic
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// as described herein will work, this just makes sure XST implements
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// that logic.
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//
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(* ram_style = "distributed" *)
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reg [31:0] regset [0:31];
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// Condition codes
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// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
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reg [3:0] flags, iflags;
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wire [14:0] w_uflags, w_iflags;
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reg trap, break_en, step, gie, sleep, r_halted,
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break_pending;
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wire w_clear_icache;
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`ifdef OPT_ILLEGAL_INSTRUCTION
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reg ill_err_u, ill_err_i;
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`else
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wire ill_err_u, ill_err_i;
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`endif
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reg ubreak;
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reg ibus_err_flag, ubus_err_flag;
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wire idiv_err_flag, udiv_err_flag;
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wire ifpu_err_flag, ufpu_err_flag;
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wire ihalt_phase, uhalt_phase;
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// The master chip enable
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wire master_ce;
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//
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//
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// PIPELINE STAGE #1 :: Prefetch
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// Variable declarations
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//
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reg [(AW-1):0] pf_pc;
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reg new_pc;
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wire clear_pipeline;
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assign clear_pipeline = new_pc;
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wire dcd_stalled;
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wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
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wire [(AW-1):0] pf_addr;
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wire [31:0] pf_data;
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wire [31:0] instruction;
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wire [(AW-1):0] instruction_pc;
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wire pf_valid, instruction_gie, pf_illegal;
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//
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//
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// PIPELINE STAGE #2 :: Instruction Decode
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// Variable declarations
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//
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//
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reg opvalid, opvalid_mem, opvalid_alu;
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reg opvalid_div, opvalid_fpu;
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wire op_stall, dcd_ce, dcd_phase;
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wire [3:0] dcdOp;
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wire [4:0] dcdA, dcdB, dcdR;
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wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
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wire [3:0] dcdF;
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wire dcdR_wr, dcdA_rd, dcdB_rd,
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dcdALU, dcdM, dcdDV, dcdFP,
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dcdF_wr, dcd_gie, dcd_break, dcd_lock,
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dcd_pipe, dcd_ljmp;
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reg r_dcdvalid;
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wire dcdvalid;
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wire [(AW-1):0] dcd_pc;
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wire [31:0] dcdI;
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wire dcd_zI; // true if dcdI == 0
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wire dcdA_stall, dcdB_stall, dcdF_stall;
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wire dcd_illegal;
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wire dcd_early_branch;
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wire [(AW-1):0] dcd_branch_pc;
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//
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//
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// PIPELINE STAGE #3 :: Read Operands
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// Variable declarations
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//
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//
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//
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// Now, let's read our operands
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reg [4:0] alu_reg;
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reg [3:0] opn;
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reg [4:0] opR;
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reg [31:0] r_opA, r_opB;
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reg [(AW-1):0] op_pc;
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wire [31:0] w_opA, w_opB;
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wire [31:0] opA_nowait, opB_nowait, opA, opB;
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reg opR_wr, opR_cc, opF_wr, op_gie;
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wire [14:0] opFl;
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reg [5:0] r_opF;
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wire [7:0] opF;
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wire op_ce, op_phase, op_pipe, op_change_data_ce;
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// Some pipeline control wires
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`ifdef OPT_PIPELINED
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reg opA_alu, opA_mem;
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reg opB_alu, opB_mem;
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`endif
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`ifdef OPT_ILLEGAL_INSTRUCTION
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reg op_illegal;
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`else
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wire op_illegal;
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assign op_illegal = 1'b0;
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`endif
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reg op_break;
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wire op_lock;
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//
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//
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// PIPELINE STAGE #4 :: ALU / Memory
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// Variable declarations
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//
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//
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reg [(AW-1):0] alu_pc;
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reg r_alu_pc_valid, mem_pc_valid;
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wire alu_pc_valid;
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wire alu_phase;
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wire alu_ce, alu_stall;
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wire [31:0] alu_result;
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wire [3:0] alu_flags;
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wire alu_valid, alu_busy;
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wire set_cond;
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reg alu_wr, alF_wr, alu_gie;
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wire alu_illegal_op;
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wire alu_illegal;
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wire mem_ce, mem_stalled;
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|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| 331 |
|
|
wire mem_pipe_stalled;
|
| 332 |
|
|
`endif
|
| 333 |
|
|
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
|
| 334 |
|
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
|
| 335 |
|
|
wire [4:0] mem_wreg;
|
| 336 |
|
|
|
| 337 |
|
|
wire mem_busy, mem_rdbusy;
|
| 338 |
|
|
wire [(AW-1):0] mem_addr;
|
| 339 |
|
|
wire [31:0] mem_data, mem_result;
|
| 340 |
|
|
|
| 341 |
|
|
wire div_ce, div_error, div_busy, div_valid;
|
| 342 |
|
|
wire [31:0] div_result;
|
| 343 |
|
|
wire [3:0] div_flags;
|
| 344 |
|
|
|
| 345 |
|
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
|
| 346 |
|
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
| 347 |
|
|
&&(set_cond);
|
| 348 |
|
|
|
| 349 |
|
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
|
| 350 |
|
|
wire [31:0] fpu_result;
|
| 351 |
|
|
wire [3:0] fpu_flags;
|
| 352 |
|
|
|
| 353 |
|
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
|
| 354 |
|
|
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
|
| 355 |
|
|
&&(set_cond);
|
| 356 |
|
|
|
| 357 |
|
|
wire adf_ce_unconditional;
|
| 358 |
|
|
|
| 359 |
|
|
//
|
| 360 |
|
|
//
|
| 361 |
|
|
// PIPELINE STAGE #5 :: Write-back
|
| 362 |
|
|
// Variable declarations
|
| 363 |
|
|
//
|
| 364 |
|
|
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
|
| 365 |
|
|
wr_write_scc, wr_write_ucc;
|
| 366 |
|
|
wire [4:0] wr_reg_id;
|
| 367 |
|
|
wire [31:0] wr_gpreg_vl, wr_spreg_vl;
|
| 368 |
|
|
wire w_switch_to_interrupt, w_release_from_interrupt;
|
| 369 |
|
|
reg [(AW-1):0] upc, ipc;
|
| 370 |
|
|
|
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
|
|
//
|
| 374 |
|
|
// MASTER: clock enable.
|
| 375 |
|
|
//
|
| 376 |
|
|
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep);
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
//
|
| 380 |
|
|
// PIPELINE STAGE #1 :: Prefetch
|
| 381 |
|
|
// Calculate stall conditions
|
| 382 |
|
|
//
|
| 383 |
|
|
// These are calculated externally, within the prefetch module.
|
| 384 |
|
|
//
|
| 385 |
|
|
|
| 386 |
|
|
//
|
| 387 |
|
|
// PIPELINE STAGE #2 :: Instruction Decode
|
| 388 |
|
|
// Calculate stall conditions
|
| 389 |
|
|
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
|
| 390 |
|
|
|
| 391 |
|
|
`ifdef OPT_PIPELINED
|
| 392 |
|
|
assign dcd_stalled = (dcdvalid)&&(op_stall);
|
| 393 |
|
|
`else
|
| 394 |
|
|
// If not pipelined, there will be no opvalid_ anything, and the
|
| 395 |
|
|
// op_stall will be false, dcdX_stall will be false, thus we can simply
|
| 396 |
|
|
// do a ...
|
| 397 |
|
|
assign dcd_stalled = 1'b0;
|
| 398 |
|
|
`endif
|
| 399 |
|
|
//
|
| 400 |
|
|
// PIPELINE STAGE #3 :: Read Operands
|
| 401 |
|
|
// Calculate stall conditions
|
| 402 |
|
|
wire op_lock_stall;
|
| 403 |
|
|
`ifdef OPT_PIPELINED
|
| 404 |
|
|
reg cc_invalid_for_dcd;
|
| 405 |
|
|
always @(posedge i_clk)
|
| 406 |
|
|
cc_invalid_for_dcd <= (wr_flags_ce)
|
| 407 |
|
|
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
|
| 408 |
|
|
||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG)))
|
| 409 |
|
|
||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG)))
|
| 410 |
|
|
||(mem_busy)||(div_busy)||(fpu_busy);
|
| 411 |
|
|
|
| 412 |
|
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
|
| 413 |
|
|
// Stall if we're stopped, and not allowed to execute
|
| 414 |
|
|
// an instruction
|
| 415 |
|
|
// (~master_ce) // Already captured in alu_stall
|
| 416 |
|
|
//
|
| 417 |
|
|
// Stall if going into the ALU and the ALU is stalled
|
| 418 |
|
|
// i.e. if the memory is busy, or we are single
|
| 419 |
|
|
// stepping. This also includes our stalls for
|
| 420 |
|
|
// op_break and op_lock, so we don't need to
|
| 421 |
|
|
// include those as well here.
|
| 422 |
|
|
// This also includes whether or not the divide or
|
| 423 |
|
|
// floating point units are busy.
|
| 424 |
|
|
(alu_stall)
|
| 425 |
|
|
//
|
| 426 |
|
|
// Stall if we are going into memory with an operation
|
| 427 |
|
|
// that cannot be pipelined, and the memory is
|
| 428 |
|
|
// already busy
|
| 429 |
|
|
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
|
| 430 |
|
|
||(opR_cc)
|
| 431 |
|
|
)
|
| 432 |
|
|
||(dcdvalid)&&(
|
| 433 |
|
|
// Stall if we need to wait for an operand A
|
| 434 |
|
|
// to be ready to read
|
| 435 |
|
|
(dcdA_stall)
|
| 436 |
|
|
// Likewise for B, also includes logic
|
| 437 |
|
|
// regarding immediate offset (register must
|
| 438 |
|
|
// be in register file if we need to add to
|
| 439 |
|
|
// an immediate)
|
| 440 |
|
|
||(dcdB_stall)
|
| 441 |
|
|
// Or if we need to wait on flags to work on the
|
| 442 |
|
|
// CC register
|
| 443 |
|
|
||(dcdF_stall)
|
| 444 |
|
|
);
|
| 445 |
|
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
// BUT ... op_ce is too complex for many of the data operations. So
|
| 449 |
|
|
// let's make their circuit enable code simpler. In particular, if
|
| 450 |
|
|
// op_ doesn't need to be preserved, we can change it all we want
|
| 451 |
|
|
// ... right? The clear_pipeline code, for example, really only needs
|
| 452 |
|
|
// to determine whether opvalid is true.
|
| 453 |
|
|
assign op_change_data_ce = (~op_stall);
|
| 454 |
|
|
`else
|
| 455 |
|
|
assign op_stall = (opvalid)&&(~master_ce);
|
| 456 |
|
|
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
|
| 457 |
|
|
assign op_change_data_ce = 1'b1;
|
| 458 |
|
|
`endif
|
| 459 |
|
|
|
| 460 |
|
|
//
|
| 461 |
|
|
// PIPELINE STAGE #4 :: ALU / Memory
|
| 462 |
|
|
// Calculate stall conditions
|
| 463 |
|
|
//
|
| 464 |
|
|
// 1. Basic stall is if the previous stage is valid and the next is
|
| 465 |
|
|
// busy.
|
| 466 |
|
|
// 2. Also stall if the prior stage is valid and the master clock enable
|
| 467 |
|
|
// is de-selected
|
| 468 |
|
|
// 3. Stall if someone on the other end is writing the CC register,
|
| 469 |
|
|
// since we don't know if it'll put us to sleep or not.
|
| 470 |
|
|
// 4. Last case: Stall if we would otherwise move a break instruction
|
| 471 |
|
|
// through the ALU. Break instructions are not allowed through
|
| 472 |
|
|
// the ALU.
|
| 473 |
|
|
`ifdef OPT_PIPELINED
|
| 474 |
|
|
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
|
| 475 |
|
|
||((opvalid)&&(op_lock)&&(op_lock_stall))
|
| 476 |
|
|
||((opvalid)&&(op_break))
|
| 477 |
|
|
||(wr_reg_ce)&&(wr_write_cc)
|
| 478 |
|
|
||(div_busy)||(fpu_busy);
|
| 479 |
|
|
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
|
| 480 |
|
|
&&(~clear_pipeline);
|
| 481 |
|
|
`else
|
| 482 |
|
|
assign alu_stall = (opvalid_alu)&&((~master_ce)||(op_break));
|
| 483 |
|
|
assign alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall)&&(~clear_pipeline);
|
| 484 |
|
|
`endif
|
| 485 |
|
|
//
|
| 486 |
|
|
|
| 487 |
|
|
//
|
| 488 |
|
|
// Note: if you change the conditions for mem_ce, you must also change
|
| 489 |
|
|
// alu_pc_valid.
|
| 490 |
|
|
//
|
| 491 |
|
|
`ifdef OPT_PIPELINED
|
| 492 |
|
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
|
| 493 |
|
|
&&(~clear_pipeline);
|
| 494 |
|
|
`else
|
| 495 |
|
|
// If we aren't pipelined, then no one will be changing what's in the
|
| 496 |
|
|
// pipeline (i.e. clear_pipeline), while our only instruction goes
|
| 497 |
|
|
// through the ... pipeline.
|
| 498 |
|
|
//
|
| 499 |
|
|
// However, in hind sight this logic didn't work. What happens when
|
| 500 |
|
|
// something gets in the pipeline and then (due to interrupt or some
|
| 501 |
|
|
// such) needs to be voided? Thus we avoid simplification and keep
|
| 502 |
|
|
// what worked here.
|
| 503 |
|
|
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
|
| 504 |
|
|
&&(~clear_pipeline);
|
| 505 |
|
|
`endif
|
| 506 |
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| 507 |
|
|
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
|
| 508 |
|
|
(mem_pipe_stalled)
|
| 509 |
|
|
||((~op_pipe)&&(mem_busy))
|
| 510 |
|
|
||(div_busy)
|
| 511 |
|
|
||(fpu_busy)
|
| 512 |
|
|
// Stall waiting for flags to be valid
|
| 513 |
|
|
// Or waiting for a write to the PC register
|
| 514 |
|
|
// Or CC register, since that can change the
|
| 515 |
|
|
// PC as well
|
| 516 |
|
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
|
| 517 |
|
|
&&((wr_write_pc)||(wr_write_cc)))));
|
| 518 |
|
|
`else
|
| 519 |
|
|
`ifdef OPT_PIPELINED
|
| 520 |
|
|
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
|
| 521 |
|
|
(~master_ce)
|
| 522 |
|
|
// Stall waiting for flags to be valid
|
| 523 |
|
|
// Or waiting for a write to the PC register
|
| 524 |
|
|
// Or CC register, since that can change the
|
| 525 |
|
|
// PC as well
|
| 526 |
|
|
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
|
| 527 |
|
|
`else
|
| 528 |
|
|
assign mem_stalled = (opvalid_mem)&&(~master_ce);
|
| 529 |
|
|
`endif
|
| 530 |
|
|
`endif
|
| 531 |
|
|
|
| 532 |
|
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
|
| 533 |
|
|
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
|
| 534 |
|
|
&&(~opvalid_mem)&&(~mem_rdbusy)
|
| 535 |
|
|
&&((~opvalid_alu)||(~alu_stall))&&(~op_break)
|
| 536 |
|
|
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
|
| 537 |
|
|
|
| 538 |
|
|
//
|
| 539 |
|
|
//
|
| 540 |
|
|
// PIPELINE STAGE #1 :: Prefetch
|
| 541 |
|
|
//
|
| 542 |
|
|
//
|
| 543 |
|
|
`ifdef OPT_SINGLE_FETCH
|
| 544 |
|
|
wire pf_ce;
|
| 545 |
|
|
|
| 546 |
|
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
|
| 547 |
|
|
prefetch #(ADDRESS_WIDTH)
|
| 548 |
|
|
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
|
| 549 |
|
|
instruction, instruction_pc, instruction_gie,
|
| 550 |
|
|
pf_valid, pf_illegal,
|
| 551 |
|
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
| 552 |
|
|
pf_ack, pf_stall, pf_err, i_wb_data);
|
| 553 |
|
|
|
| 554 |
|
|
initial r_dcdvalid = 1'b0;
|
| 555 |
|
|
always @(posedge i_clk)
|
| 556 |
|
|
if ((i_rst)||(clear_pipeline))
|
| 557 |
|
|
r_dcdvalid <= 1'b0;
|
| 558 |
|
|
else if (dcd_ce)
|
| 559 |
|
|
r_dcdvalid <= (pf_valid)||(pf_illegal);
|
| 560 |
|
|
else if (op_ce)
|
| 561 |
|
|
r_dcdvalid <= 1'b0;
|
| 562 |
|
|
assign dcdvalid = r_dcdvalid;
|
| 563 |
|
|
|
| 564 |
|
|
`else // Pipe fetch
|
| 565 |
|
|
|
| 566 |
|
|
`ifdef OPT_TRADITIONAL_PFCACHE
|
| 567 |
|
|
pfcache #(LGICACHE, ADDRESS_WIDTH)
|
| 568 |
|
|
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
| 569 |
|
|
w_clear_icache,
|
| 570 |
|
|
// dcd_pc,
|
| 571 |
|
|
~dcd_stalled,
|
| 572 |
|
|
((dcd_early_branch)&&(~clear_pipeline))
|
| 573 |
|
|
? dcd_branch_pc:pf_pc,
|
| 574 |
|
|
instruction, instruction_pc, pf_valid,
|
| 575 |
|
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
| 576 |
|
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
| 577 |
|
|
pf_illegal);
|
| 578 |
|
|
`else
|
| 579 |
|
|
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
|
| 580 |
|
|
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
|
| 581 |
|
|
w_clear_icache, ~dcd_stalled,
|
| 582 |
|
|
(new_pc)?pf_pc:dcd_branch_pc,
|
| 583 |
|
|
instruction, instruction_pc, pf_valid,
|
| 584 |
|
|
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
|
| 585 |
|
|
pf_ack, pf_stall, pf_err, i_wb_data,
|
| 586 |
|
|
//`ifdef OPT_PRECLEAR_BUS
|
| 587 |
|
|
//((dcd_clear_bus)&&(dcdvalid))
|
| 588 |
|
|
//||((op_clear_bus)&&(opvalid))
|
| 589 |
|
|
//||
|
| 590 |
|
|
//`endif
|
| 591 |
|
|
(mem_cyc_lcl)||(mem_cyc_gbl),
|
| 592 |
|
|
pf_illegal);
|
| 593 |
|
|
`endif
|
| 594 |
|
|
assign instruction_gie = gie;
|
| 595 |
|
|
|
| 596 |
|
|
initial r_dcdvalid = 1'b0;
|
| 597 |
|
|
always @(posedge i_clk)
|
| 598 |
|
|
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
|
| 599 |
|
|
r_dcdvalid <= 1'b0;
|
| 600 |
|
|
else if (dcd_ce)
|
| 601 |
|
|
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch);
|
| 602 |
|
|
else if (op_ce)
|
| 603 |
|
|
r_dcdvalid <= 1'b0;
|
| 604 |
|
|
assign dcdvalid = r_dcdvalid;
|
| 605 |
|
|
`endif
|
| 606 |
|
|
|
| 607 |
|
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
| 608 |
|
|
|
| 609 |
|
|
// If not pipelined, there will be no opvalid_ anything, and the
|
| 610 |
|
|
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
| 611 |
|
|
IMPLEMENT_FPU)
|
| 612 |
|
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
| 613 |
|
|
(~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie,
|
| 614 |
|
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
| 615 |
|
|
dcd_illegal, dcd_pc, dcd_gie,
|
| 616 |
|
|
{ dcdR_cc, dcdR_pc, dcdR },
|
| 617 |
|
|
{ dcdA_cc, dcdA_pc, dcdA },
|
| 618 |
|
|
{ dcdB_cc, dcdB_pc, dcdB },
|
| 619 |
|
|
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
|
| 620 |
|
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
| 621 |
|
|
dcdR_wr,dcdA_rd, dcdB_rd,
|
| 622 |
|
|
dcd_early_branch,
|
| 623 |
|
|
dcd_branch_pc, dcd_ljmp,
|
| 624 |
|
|
dcd_pipe);
|
| 625 |
|
|
`else
|
| 626 |
|
|
idecode_deprecated
|
| 627 |
|
|
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
|
| 628 |
|
|
IMPLEMENT_FPU)
|
| 629 |
|
|
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
|
| 630 |
|
|
dcd_ce, dcd_stalled, instruction, instruction_gie,
|
| 631 |
|
|
instruction_pc, pf_valid, pf_illegal, dcd_phase,
|
| 632 |
|
|
dcd_illegal, dcd_pc, dcd_gie,
|
| 633 |
|
|
{ dcdR_cc, dcdR_pc, dcdR },
|
| 634 |
|
|
{ dcdA_cc, dcdA_pc, dcdA },
|
| 635 |
|
|
{ dcdB_cc, dcdB_pc, dcdB },
|
| 636 |
|
|
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
|
| 637 |
|
|
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
|
| 638 |
|
|
dcdR_wr,dcdA_rd, dcdB_rd,
|
| 639 |
|
|
dcd_early_branch,
|
| 640 |
|
|
dcd_branch_pc,
|
| 641 |
|
|
dcd_pipe);
|
| 642 |
|
|
assign dcd_ljmp = 1'b0;
|
| 643 |
|
|
`endif
|
| 644 |
|
|
|
| 645 |
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| 646 |
|
|
reg r_op_pipe;
|
| 647 |
|
|
|
| 648 |
|
|
initial r_op_pipe = 1'b0;
|
| 649 |
|
|
// To be a pipeable operation, there must be
|
| 650 |
|
|
// two valid adjacent instructions
|
| 651 |
|
|
// Both must be memory instructions
|
| 652 |
|
|
// Both must be writes, or both must be reads
|
| 653 |
|
|
// Both operations must be to the same identical address,
|
| 654 |
|
|
// or at least a single (one) increment above that address
|
| 655 |
|
|
//
|
| 656 |
|
|
// However ... we need to know this before this clock, hence this is
|
| 657 |
|
|
// calculated in the instruction decoder.
|
| 658 |
|
|
always @(posedge i_clk)
|
| 659 |
|
|
if (op_ce)
|
| 660 |
|
|
r_op_pipe <= dcd_pipe;
|
| 661 |
|
|
else if (mem_ce) // Clear us any time an op_ is clocked in
|
| 662 |
|
|
r_op_pipe <= 1'b0;
|
| 663 |
|
|
assign op_pipe = r_op_pipe;
|
| 664 |
|
|
`else
|
| 665 |
|
|
assign op_pipe = 1'b0;
|
| 666 |
|
|
`endif
|
| 667 |
|
|
|
| 668 |
|
|
//
|
| 669 |
|
|
//
|
| 670 |
|
|
// PIPELINE STAGE #3 :: Read Operands (Registers)
|
| 671 |
|
|
//
|
| 672 |
|
|
//
|
| 673 |
|
|
assign w_opA = regset[dcdA];
|
| 674 |
|
|
assign w_opB = regset[dcdB];
|
| 675 |
|
|
|
| 676 |
|
|
wire [8:0] w_cpu_info;
|
| 677 |
|
|
assign w_cpu_info = {
|
| 678 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 679 |
|
|
1'b1,
|
| 680 |
|
|
`else
|
| 681 |
|
|
1'b0,
|
| 682 |
|
|
`endif
|
| 683 |
|
|
`ifdef OPT_MULTIPLY
|
| 684 |
|
|
1'b1,
|
| 685 |
|
|
`else
|
| 686 |
|
|
1'b0,
|
| 687 |
|
|
`endif
|
| 688 |
|
|
`ifdef OPT_DIVIDE
|
| 689 |
|
|
1'b1,
|
| 690 |
|
|
`else
|
| 691 |
|
|
1'b0,
|
| 692 |
|
|
`endif
|
| 693 |
|
|
`ifdef OPT_IMPLEMENT_FPU
|
| 694 |
|
|
1'b1,
|
| 695 |
|
|
`else
|
| 696 |
|
|
1'b0,
|
| 697 |
|
|
`endif
|
| 698 |
|
|
`ifdef OPT_PIPELINED
|
| 699 |
|
|
1'b1,
|
| 700 |
|
|
`else
|
| 701 |
|
|
1'b0,
|
| 702 |
|
|
`endif
|
| 703 |
|
|
`ifdef OPT_TRADITIONAL_CACHE
|
| 704 |
|
|
1'b1,
|
| 705 |
|
|
`else
|
| 706 |
|
|
1'b0,
|
| 707 |
|
|
`endif
|
| 708 |
|
|
`ifdef OPT_EARLY_BRANCHING
|
| 709 |
|
|
1'b1,
|
| 710 |
|
|
`else
|
| 711 |
|
|
1'b0,
|
| 712 |
|
|
`endif
|
| 713 |
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| 714 |
|
|
1'b1,
|
| 715 |
|
|
`else
|
| 716 |
|
|
1'b0,
|
| 717 |
|
|
`endif
|
| 718 |
|
|
`ifdef OPT_VLIW
|
| 719 |
|
|
1'b1
|
| 720 |
|
|
`else
|
| 721 |
|
|
1'b0
|
| 722 |
|
|
`endif
|
| 723 |
|
|
};
|
| 724 |
|
|
|
| 725 |
|
|
wire [31:0] w_pcA_v;
|
| 726 |
|
|
generate
|
| 727 |
|
|
if (AW < 32)
|
| 728 |
|
|
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
|
| 729 |
|
|
else
|
| 730 |
|
|
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
|
| 731 |
|
|
endgenerate
|
| 732 |
|
|
|
| 733 |
|
|
`ifdef OPT_PIPELINED
|
| 734 |
|
|
reg [4:0] opA_id, opB_id;
|
| 735 |
|
|
reg opA_rd, opB_rd;
|
| 736 |
|
|
always @(posedge i_clk)
|
| 737 |
|
|
if (op_ce)
|
| 738 |
|
|
begin
|
| 739 |
|
|
opA_id <= dcdA;
|
| 740 |
|
|
opB_id <= dcdB;
|
| 741 |
|
|
opA_rd <= dcdA_rd;
|
| 742 |
|
|
opB_rd <= dcdB_rd;
|
| 743 |
|
|
end
|
| 744 |
|
|
`endif
|
| 745 |
|
|
|
| 746 |
|
|
always @(posedge i_clk)
|
| 747 |
|
|
if (op_change_data_ce)
|
| 748 |
|
|
begin
|
| 749 |
|
|
if ((wr_reg_ce)&&(wr_reg_id == dcdA))
|
| 750 |
|
|
r_opA <= wr_gpreg_vl;
|
| 751 |
|
|
else if (dcdA_pc)
|
| 752 |
|
|
r_opA <= w_pcA_v;
|
| 753 |
|
|
else if (dcdA_cc)
|
| 754 |
|
|
r_opA <= { w_cpu_info, w_opA[22:15], (dcdA[4])?w_uflags:w_iflags };
|
| 755 |
|
|
else
|
| 756 |
|
|
r_opA <= w_opA;
|
| 757 |
|
|
`ifdef OPT_PIPELINED
|
| 758 |
|
|
end else
|
| 759 |
|
|
begin // We were going to pick these up when they became valid,
|
| 760 |
|
|
// but for some reason we're stuck here as they became
|
| 761 |
|
|
// valid. Pick them up now anyway
|
| 762 |
|
|
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
|
| 763 |
|
|
// r_opA <= wr_gpreg_vl;
|
| 764 |
|
|
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
|
| 765 |
|
|
r_opA <= wr_gpreg_vl;
|
| 766 |
|
|
`endif
|
| 767 |
|
|
end
|
| 768 |
|
|
|
| 769 |
|
|
wire [31:0] w_opBnI, w_pcB_v;
|
| 770 |
|
|
generate
|
| 771 |
|
|
if (AW < 32)
|
| 772 |
|
|
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
|
| 773 |
|
|
else
|
| 774 |
|
|
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
|
| 775 |
|
|
endgenerate
|
| 776 |
|
|
|
| 777 |
|
|
assign w_opBnI = (~dcdB_rd) ? 32'h00
|
| 778 |
|
|
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
|
| 779 |
|
|
: ((dcdB_pc) ? w_pcB_v
|
| 780 |
|
|
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:15], // w_opB[31:14],
|
| 781 |
|
|
(dcdB[4])?w_uflags:w_iflags}
|
| 782 |
|
|
: w_opB)));
|
| 783 |
|
|
|
| 784 |
|
|
always @(posedge i_clk)
|
| 785 |
|
|
if (op_change_data_ce)
|
| 786 |
|
|
r_opB <= w_opBnI + dcdI;
|
| 787 |
|
|
`ifdef OPT_PIPELINED
|
| 788 |
|
|
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
|
| 789 |
|
|
r_opB <= wr_gpreg_vl;
|
| 790 |
|
|
`endif
|
| 791 |
|
|
|
| 792 |
|
|
// The logic here has become more complex than it should be, no thanks
|
| 793 |
|
|
// to Xilinx's Vivado trying to help. The conditions are supposed to
|
| 794 |
|
|
// be two sets of four bits: the top bits specify what bits matter, the
|
| 795 |
|
|
// bottom specify what those top bits must equal. However, two of
|
| 796 |
|
|
// conditions check whether bits are on, and those are the only two
|
| 797 |
|
|
// conditions checking those bits. Therefore, Vivado complains that
|
| 798 |
|
|
// these two bits are redundant. Hence the convoluted expression
|
| 799 |
|
|
// below, arriving at what we finally want in the (now wire net)
|
| 800 |
|
|
// opF.
|
| 801 |
|
|
always @(posedge i_clk)
|
| 802 |
|
|
if (op_ce) // Cannot do op_change_data_ce here since opF depends
|
| 803 |
|
|
// upon being either correct for a valid op, or correct
|
| 804 |
|
|
// for the last valid op
|
| 805 |
|
|
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
|
| 806 |
|
|
case(dcdF[2:0])
|
| 807 |
|
|
3'h0: r_opF <= 6'h00; // Always
|
| 808 |
|
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
| 809 |
|
|
// These were remapped as part of the new instruction
|
| 810 |
|
|
// set in order to make certain that the low order
|
| 811 |
|
|
// two bits contained the most commonly used
|
| 812 |
|
|
// conditions: Always, LT, Z, and NZ.
|
| 813 |
|
|
3'h1: r_opF <= 6'h24; // LT
|
| 814 |
|
|
3'h2: r_opF <= 6'h11; // Z
|
| 815 |
|
|
3'h3: r_opF <= 6'h10; // NE
|
| 816 |
|
|
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
|
| 817 |
|
|
3'h5: r_opF <= 6'h20; // GE (!N)
|
| 818 |
|
|
`else
|
| 819 |
|
|
3'h1: r_opF <= 6'h11; // Z
|
| 820 |
|
|
3'h2: r_opF <= 6'h10; // NE
|
| 821 |
|
|
3'h3: r_opF <= 6'h20; // GE (!N)
|
| 822 |
|
|
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
|
| 823 |
|
|
3'h5: r_opF <= 6'h24; // LT
|
| 824 |
|
|
`endif
|
| 825 |
|
|
3'h6: r_opF <= 6'h02; // C
|
| 826 |
|
|
3'h7: r_opF <= 6'h08; // V
|
| 827 |
|
|
endcase
|
| 828 |
|
|
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
|
| 829 |
|
|
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
|
| 830 |
|
|
|
| 831 |
|
|
wire w_opvalid;
|
| 832 |
|
|
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
|
| 833 |
|
|
initial opvalid = 1'b0;
|
| 834 |
|
|
initial opvalid_alu = 1'b0;
|
| 835 |
|
|
initial opvalid_mem = 1'b0;
|
| 836 |
|
|
initial opvalid_div = 1'b0;
|
| 837 |
|
|
initial opvalid_fpu = 1'b0;
|
| 838 |
|
|
always @(posedge i_clk)
|
| 839 |
|
|
if (i_rst)
|
| 840 |
|
|
begin
|
| 841 |
|
|
opvalid <= 1'b0;
|
| 842 |
|
|
opvalid_alu <= 1'b0;
|
| 843 |
|
|
opvalid_mem <= 1'b0;
|
| 844 |
|
|
opvalid_div <= 1'b0;
|
| 845 |
|
|
opvalid_fpu <= 1'b0;
|
| 846 |
|
|
end else if (op_ce)
|
| 847 |
|
|
begin
|
| 848 |
|
|
// Do we have a valid instruction?
|
| 849 |
|
|
// The decoder may vote to stall one of its
|
| 850 |
|
|
// instructions based upon something we currently
|
| 851 |
|
|
// have in our queue. This instruction must then
|
| 852 |
|
|
// move forward, and get a stall cycle inserted.
|
| 853 |
|
|
// Hence, the test on dcd_stalled here. If we must
|
| 854 |
|
|
// wait until our operands are valid, then we aren't
|
| 855 |
|
|
// valid yet until then.
|
| 856 |
|
|
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid);
|
| 857 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 858 |
|
|
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal));
|
| 859 |
|
|
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
|
| 860 |
|
|
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
|
| 861 |
|
|
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
|
| 862 |
|
|
`else
|
| 863 |
|
|
opvalid_alu <= (dcdALU)&&(w_opvalid);
|
| 864 |
|
|
opvalid_mem <= (dcdM)&&(w_opvalid);
|
| 865 |
|
|
opvalid_div <= (dcdDV)&&(w_opvalid);
|
| 866 |
|
|
opvalid_fpu <= (dcdFP)&&(w_opvalid);
|
| 867 |
|
|
`endif
|
| 868 |
|
|
end else if ((clear_pipeline)||(adf_ce_unconditional)||(mem_ce))
|
| 869 |
|
|
begin
|
| 870 |
|
|
opvalid <= 1'b0;
|
| 871 |
|
|
opvalid_alu <= 1'b0;
|
| 872 |
|
|
opvalid_mem <= 1'b0;
|
| 873 |
|
|
opvalid_div <= 1'b0;
|
| 874 |
|
|
opvalid_fpu <= 1'b0;
|
| 875 |
|
|
end
|
| 876 |
|
|
|
| 877 |
|
|
// Here's part of our debug interface. When we recognize a break
|
| 878 |
|
|
// instruction, we set the op_break flag. That'll prevent this
|
| 879 |
|
|
// instruction from entering the ALU, and cause an interrupt before
|
| 880 |
|
|
// this instruction. Thus, returning to this code will cause the
|
| 881 |
|
|
// break to repeat and continue upon return. To get out of this
|
| 882 |
|
|
// condition, replace the break instruction with what it is supposed
|
| 883 |
|
|
// to be, step through it, and then replace it back. In this fashion,
|
| 884 |
|
|
// a debugger can step through code.
|
| 885 |
|
|
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
|
| 886 |
|
|
initial op_break = 1'b0;
|
| 887 |
|
|
always @(posedge i_clk)
|
| 888 |
|
|
if (i_rst) op_break <= 1'b0;
|
| 889 |
|
|
else if (op_ce) op_break <= (dcd_break); // &&(dcdvalid)
|
| 890 |
|
|
else if ((clear_pipeline)||(~opvalid))
|
| 891 |
|
|
op_break <= 1'b0;
|
| 892 |
|
|
|
| 893 |
|
|
`ifdef OPT_PIPELINED
|
| 894 |
|
|
generate
|
| 895 |
|
|
if (IMPLEMENT_LOCK != 0)
|
| 896 |
|
|
begin
|
| 897 |
|
|
reg r_op_lock, r_op_lock_stall;
|
| 898 |
|
|
|
| 899 |
|
|
initial r_op_lock_stall = 1'b0;
|
| 900 |
|
|
always @(posedge i_clk)
|
| 901 |
|
|
if (i_rst)
|
| 902 |
|
|
r_op_lock_stall <= 1'b0;
|
| 903 |
|
|
else
|
| 904 |
|
|
r_op_lock_stall <= (~opvalid)||(~op_lock)
|
| 905 |
|
|
||(~dcdvalid)||(~pf_valid);
|
| 906 |
|
|
|
| 907 |
|
|
assign op_lock_stall = r_op_lock_stall;
|
| 908 |
|
|
|
| 909 |
|
|
initial r_op_lock = 1'b0;
|
| 910 |
|
|
always @(posedge i_clk)
|
| 911 |
|
|
if ((i_rst)||(clear_pipeline))
|
| 912 |
|
|
r_op_lock <= 1'b0;
|
| 913 |
|
|
else if (op_ce)
|
| 914 |
|
|
r_op_lock <= (dcd_lock)&&(~clear_pipeline);
|
| 915 |
|
|
assign op_lock = r_op_lock;
|
| 916 |
|
|
|
| 917 |
|
|
end else begin
|
| 918 |
|
|
assign op_lock_stall = 1'b0;
|
| 919 |
|
|
assign op_lock = 1'b0;
|
| 920 |
|
|
end endgenerate
|
| 921 |
|
|
|
| 922 |
|
|
`else
|
| 923 |
|
|
assign op_lock_stall = 1'b0;
|
| 924 |
|
|
assign op_lock = 1'b0;
|
| 925 |
|
|
`endif
|
| 926 |
|
|
|
| 927 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 928 |
|
|
initial op_illegal = 1'b0;
|
| 929 |
|
|
always @(posedge i_clk)
|
| 930 |
|
|
if ((i_rst)||(clear_pipeline))
|
| 931 |
|
|
op_illegal <= 1'b0;
|
| 932 |
|
|
else if(op_ce)
|
| 933 |
|
|
`ifdef OPT_PIPELINED
|
| 934 |
|
|
op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
|
| 935 |
|
|
`else
|
| 936 |
|
|
op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock));
|
| 937 |
|
|
`endif
|
| 938 |
|
|
`endif
|
| 939 |
|
|
else if(alu_ce)
|
| 940 |
|
|
op_illegal <= 1'b0;
|
| 941 |
|
|
|
| 942 |
|
|
// No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
|
| 943 |
|
|
// set, dcd_early_branch will simply be a wire connected to zero and
|
| 944 |
|
|
// this logic should just optimize.
|
| 945 |
|
|
always @(posedge i_clk)
|
| 946 |
|
|
if (op_ce)
|
| 947 |
|
|
begin
|
| 948 |
|
|
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
|
| 949 |
|
|
&&(~dcd_early_branch)&&(~dcd_illegal);
|
| 950 |
|
|
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
|
| 951 |
|
|
end
|
| 952 |
|
|
|
| 953 |
|
|
always @(posedge i_clk)
|
| 954 |
|
|
if (op_change_data_ce)
|
| 955 |
|
|
begin
|
| 956 |
|
|
opn <= dcdOp; // Which ALU operation?
|
| 957 |
|
|
// opM <= dcdM; // Is this a memory operation?
|
| 958 |
|
|
// What register will these results be written into?
|
| 959 |
|
|
opR <= dcdR;
|
| 960 |
|
|
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
|
| 961 |
|
|
// User level (1), vs supervisor (0)/interrupts disabled
|
| 962 |
|
|
op_gie <= dcd_gie;
|
| 963 |
|
|
|
| 964 |
|
|
|
| 965 |
|
|
//
|
| 966 |
|
|
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
|
| 967 |
|
|
end
|
| 968 |
|
|
assign opFl = (op_gie)?(w_uflags):(w_iflags);
|
| 969 |
|
|
|
| 970 |
|
|
`ifdef OPT_VLIW
|
| 971 |
|
|
reg r_op_phase;
|
| 972 |
|
|
initial r_op_phase = 1'b0;
|
| 973 |
|
|
always @(posedge i_clk)
|
| 974 |
|
|
if ((i_rst)||(clear_pipeline))
|
| 975 |
|
|
r_op_phase <= 1'b0;
|
| 976 |
|
|
else if (op_change_data_ce)
|
| 977 |
|
|
r_op_phase <= dcd_phase;
|
| 978 |
|
|
assign op_phase = r_op_phase;
|
| 979 |
|
|
`else
|
| 980 |
|
|
assign op_phase = 1'b0;
|
| 981 |
|
|
`endif
|
| 982 |
|
|
|
| 983 |
|
|
// This is tricky. First, the PC and Flags registers aren't kept in
|
| 984 |
|
|
// register set but in special registers of their own. So step one
|
| 985 |
|
|
// is to select the right register. Step to is to replace that
|
| 986 |
|
|
// register with the results of an ALU or memory operation, if such
|
| 987 |
|
|
// results are now available. Otherwise, we'd need to insert a wait
|
| 988 |
|
|
// state of some type.
|
| 989 |
|
|
//
|
| 990 |
|
|
// The alternative approach would be to define some sort of
|
| 991 |
|
|
// op_stall wire, which would stall any upstream stage.
|
| 992 |
|
|
// We'll create a flag here to start our coordination. Once we
|
| 993 |
|
|
// define this flag to something other than just plain zero, then
|
| 994 |
|
|
// the stalls will already be in place.
|
| 995 |
|
|
`ifdef OPT_PIPELINED
|
| 996 |
|
|
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
|
| 997 |
|
|
? wr_gpreg_vl : r_opA;
|
| 998 |
|
|
`else
|
| 999 |
|
|
assign opA = r_opA;
|
| 1000 |
|
|
`endif
|
| 1001 |
|
|
|
| 1002 |
|
|
`ifdef OPT_PIPELINED
|
| 1003 |
|
|
// Stall if we have decoded an instruction that will read register A
|
| 1004 |
|
|
// AND ... something that may write a register is running
|
| 1005 |
|
|
// AND (series of conditions here ...)
|
| 1006 |
|
|
// The operation might set flags, and we wish to read the
|
| 1007 |
|
|
// CC register
|
| 1008 |
|
|
// OR ... (No other conditions)
|
| 1009 |
|
|
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
|
| 1010 |
|
|
&&((opvalid)||(mem_rdbusy)
|
| 1011 |
|
|
||(div_busy)||(fpu_busy))
|
| 1012 |
|
|
&&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc))
|
| 1013 |
|
|
||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd));
|
| 1014 |
|
|
`else
|
| 1015 |
|
|
// There are no pipeline hazards, if we aren't pipelined
|
| 1016 |
|
|
assign dcdA_stall = 1'b0;
|
| 1017 |
|
|
`endif
|
| 1018 |
|
|
|
| 1019 |
|
|
`ifdef OPT_PIPELINED
|
| 1020 |
|
|
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
|
| 1021 |
|
|
? wr_gpreg_vl: r_opB;
|
| 1022 |
|
|
`else
|
| 1023 |
|
|
assign opB = r_opB;
|
| 1024 |
|
|
`endif
|
| 1025 |
|
|
|
| 1026 |
|
|
`ifdef OPT_PIPELINED
|
| 1027 |
|
|
// Stall if we have decoded an instruction that will read register B
|
| 1028 |
|
|
// AND ... something that may write a (unknown) register is running
|
| 1029 |
|
|
// AND (series of conditions here ...)
|
| 1030 |
|
|
// The operation might set flags, and we wish to read the
|
| 1031 |
|
|
// CC register
|
| 1032 |
|
|
// OR the operation might set register B, and we still need
|
| 1033 |
|
|
// a clock to add the offset to it
|
| 1034 |
|
|
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
|
| 1035 |
|
|
// If the op stage isn't valid, yet something
|
| 1036 |
|
|
// is running, then it must have been valid.
|
| 1037 |
|
|
// We'll use the last values from that stage
|
| 1038 |
|
|
// (opR_wr, opF_wr, opR) in our logic below.
|
| 1039 |
|
|
&&((opvalid)||(mem_rdbusy)
|
| 1040 |
|
|
||(div_busy)||(fpu_busy)||(alu_busy))
|
| 1041 |
|
|
&&(
|
| 1042 |
|
|
// Okay, what happens if the result register
|
| 1043 |
|
|
// from instruction 1 becomes the input for
|
| 1044 |
|
|
// instruction two, *and* there's an immediate
|
| 1045 |
|
|
// offset in instruction two? In that case, we
|
| 1046 |
|
|
// need an extra clock between the two
|
| 1047 |
|
|
// instructions to calculate the base plus
|
| 1048 |
|
|
// offset.
|
| 1049 |
|
|
//
|
| 1050 |
|
|
// What if instruction 1 (or before) is in a
|
| 1051 |
|
|
// memory pipeline? We may no longer know what
|
| 1052 |
|
|
// the register was! We will then need to
|
| 1053 |
|
|
// blindly wait. We'll temper this only waiting
|
| 1054 |
|
|
// if we're not piping this new instruction.
|
| 1055 |
|
|
// If we were piping, the pipe logic in the
|
| 1056 |
|
|
// decode circuit has told us that the hazard
|
| 1057 |
|
|
// is clear, so we're okay then.
|
| 1058 |
|
|
//
|
| 1059 |
|
|
((~dcd_zI)&&(
|
| 1060 |
|
|
((opR == dcdB)&&(opR_wr))
|
| 1061 |
|
|
||((mem_rdbusy)&&(~dcd_pipe))
|
| 1062 |
|
|
))
|
| 1063 |
|
|
// Stall following any instruction that will
|
| 1064 |
|
|
// set the flags, if we're going to need the
|
| 1065 |
|
|
// flags (CC) register for opB.
|
| 1066 |
|
|
||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc))
|
| 1067 |
|
|
// Stall on any ongoing memory operation that
|
| 1068 |
|
|
// will write to opB -- captured above
|
| 1069 |
|
|
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
|
| 1070 |
|
|
)
|
| 1071 |
|
|
||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd));
|
| 1072 |
|
|
assign dcdF_stall = ((~dcdF[3])
|
| 1073 |
|
|
||((dcdA_rd)&&(dcdA_cc))
|
| 1074 |
|
|
||((dcdB_rd)&&(dcdB_cc)))
|
| 1075 |
|
|
&&(opvalid)&&(opR_cc);
|
| 1076 |
|
|
// &&(dcdvalid) is checked for elsewhere
|
| 1077 |
|
|
`else
|
| 1078 |
|
|
// No stalls without pipelining, 'cause how can you have a pipeline
|
| 1079 |
|
|
// hazard without the pipeline?
|
| 1080 |
|
|
assign dcdB_stall = 1'b0;
|
| 1081 |
|
|
assign dcdF_stall = 1'b0;
|
| 1082 |
|
|
`endif
|
| 1083 |
|
|
//
|
| 1084 |
|
|
//
|
| 1085 |
|
|
// PIPELINE STAGE #4 :: Apply Instruction
|
| 1086 |
|
|
//
|
| 1087 |
|
|
//
|
| 1088 |
|
|
`ifdef OPT_NEW_INSTRUCTION_SET
|
| 1089 |
|
|
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
|
| 1090 |
|
|
(opvalid_alu), opn, opA, opB,
|
| 1091 |
|
|
alu_result, alu_flags, alu_valid, alu_illegal_op,
|
| 1092 |
|
|
alu_busy);
|
| 1093 |
|
|
`else
|
| 1094 |
|
|
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
|
| 1095 |
|
|
(opvalid_alu), opn, opA, opB,
|
| 1096 |
|
|
alu_result, alu_flags, alu_valid, alu_illegal_op);
|
| 1097 |
|
|
assign alu_busy = 1'b0;
|
| 1098 |
|
|
`endif
|
| 1099 |
|
|
|
| 1100 |
|
|
generate
|
| 1101 |
|
|
if (IMPLEMENT_DIVIDE != 0)
|
| 1102 |
|
|
begin
|
| 1103 |
|
|
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
|
| 1104 |
|
|
opA, opB, div_busy, div_valid, div_error, div_result,
|
| 1105 |
|
|
div_flags);
|
| 1106 |
|
|
end else begin
|
| 1107 |
|
|
assign div_error = 1'b0; // Can't be high unless div_valid
|
| 1108 |
|
|
assign div_busy = 1'b0;
|
| 1109 |
|
|
assign div_valid = 1'b0;
|
| 1110 |
|
|
assign div_result= 32'h00;
|
| 1111 |
|
|
assign div_flags = 4'h0;
|
| 1112 |
|
|
end endgenerate
|
| 1113 |
|
|
|
| 1114 |
|
|
generate
|
| 1115 |
|
|
if (IMPLEMENT_FPU != 0)
|
| 1116 |
|
|
begin
|
| 1117 |
|
|
//
|
| 1118 |
|
|
// sfpu thefpu(i_clk, i_rst, fpu_ce,
|
| 1119 |
|
|
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
|
| 1120 |
|
|
// fpu_flags);
|
| 1121 |
|
|
//
|
| 1122 |
|
|
assign fpu_error = 1'b0; // Must only be true if fpu_valid
|
| 1123 |
|
|
assign fpu_busy = 1'b0;
|
| 1124 |
|
|
assign fpu_valid = 1'b0;
|
| 1125 |
|
|
assign fpu_result= 32'h00;
|
| 1126 |
|
|
assign fpu_flags = 4'h0;
|
| 1127 |
|
|
end else begin
|
| 1128 |
|
|
assign fpu_error = 1'b0;
|
| 1129 |
|
|
assign fpu_busy = 1'b0;
|
| 1130 |
|
|
assign fpu_valid = 1'b0;
|
| 1131 |
|
|
assign fpu_result= 32'h00;
|
| 1132 |
|
|
assign fpu_flags = 4'h0;
|
| 1133 |
|
|
end endgenerate
|
| 1134 |
|
|
|
| 1135 |
|
|
|
| 1136 |
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
|
| 1137 |
|
|
initial alF_wr = 1'b0;
|
| 1138 |
|
|
initial alu_wr = 1'b0;
|
| 1139 |
|
|
always @(posedge i_clk)
|
| 1140 |
|
|
if (i_rst)
|
| 1141 |
|
|
begin
|
| 1142 |
|
|
alu_wr <= 1'b0;
|
| 1143 |
|
|
alF_wr <= 1'b0;
|
| 1144 |
|
|
end else if (alu_ce)
|
| 1145 |
|
|
begin
|
| 1146 |
|
|
// alu_reg <= opR;
|
| 1147 |
|
|
alu_wr <= (opR_wr)&&(set_cond);
|
| 1148 |
|
|
alF_wr <= (opF_wr)&&(set_cond);
|
| 1149 |
|
|
end else if (~alu_busy) begin
|
| 1150 |
|
|
// These are strobe signals, so clear them if not
|
| 1151 |
|
|
// set for any particular clock
|
| 1152 |
|
|
alu_wr <= (i_halt)&&(i_dbg_we);
|
| 1153 |
|
|
alF_wr <= 1'b0;
|
| 1154 |
|
|
end
|
| 1155 |
|
|
|
| 1156 |
|
|
`ifdef OPT_VLIW
|
| 1157 |
|
|
reg r_alu_phase;
|
| 1158 |
|
|
initial r_alu_phase = 1'b0;
|
| 1159 |
|
|
always @(posedge i_clk)
|
| 1160 |
|
|
if (i_rst)
|
| 1161 |
|
|
r_alu_phase <= 1'b0;
|
| 1162 |
|
|
else if ((adf_ce_unconditional)||(mem_ce))
|
| 1163 |
|
|
r_alu_phase <= op_phase;
|
| 1164 |
|
|
assign alu_phase = r_alu_phase;
|
| 1165 |
|
|
`else
|
| 1166 |
|
|
assign alu_phase = 1'b0;
|
| 1167 |
|
|
`endif
|
| 1168 |
|
|
|
| 1169 |
|
|
always @(posedge i_clk)
|
| 1170 |
|
|
if (adf_ce_unconditional)
|
| 1171 |
|
|
alu_reg <= opR;
|
| 1172 |
|
|
else if ((i_halt)&&(i_dbg_we))
|
| 1173 |
|
|
alu_reg <= i_dbg_reg;
|
| 1174 |
|
|
|
| 1175 |
|
|
//
|
| 1176 |
|
|
// DEBUG Register write access starts here
|
| 1177 |
|
|
//
|
| 1178 |
|
|
reg dbgv;
|
| 1179 |
|
|
initial dbgv = 1'b0;
|
| 1180 |
|
|
always @(posedge i_clk)
|
| 1181 |
|
|
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
|
| 1182 |
|
|
reg [31:0] dbg_val;
|
| 1183 |
|
|
always @(posedge i_clk)
|
| 1184 |
|
|
dbg_val <= i_dbg_data;
|
| 1185 |
|
|
always @(posedge i_clk)
|
| 1186 |
|
|
if ((adf_ce_unconditional)||(mem_ce))
|
| 1187 |
|
|
alu_gie <= op_gie;
|
| 1188 |
|
|
always @(posedge i_clk)
|
| 1189 |
|
|
if ((adf_ce_unconditional)
|
| 1190 |
|
|
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
|
| 1191 |
|
|
&&(~mem_stalled)))
|
| 1192 |
|
|
alu_pc <= op_pc;
|
| 1193 |
|
|
|
| 1194 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 1195 |
|
|
reg r_alu_illegal;
|
| 1196 |
|
|
initial r_alu_illegal = 0;
|
| 1197 |
|
|
always @(posedge i_clk)
|
| 1198 |
|
|
if ((i_rst)||(clear_pipeline))
|
| 1199 |
|
|
r_alu_illegal <= 1'b0;
|
| 1200 |
|
|
else if (alu_ce)
|
| 1201 |
|
|
r_alu_illegal <= op_illegal;
|
| 1202 |
|
|
else
|
| 1203 |
|
|
r_alu_illegal <= 1'b0;
|
| 1204 |
|
|
assign alu_illegal = (alu_illegal_op)||(r_alu_illegal);
|
| 1205 |
|
|
`else
|
| 1206 |
|
|
assign alu_illegal = 1'b0;
|
| 1207 |
|
|
`endif
|
| 1208 |
|
|
|
| 1209 |
|
|
initial r_alu_pc_valid = 1'b0;
|
| 1210 |
|
|
initial mem_pc_valid = 1'b0;
|
| 1211 |
|
|
always @(posedge i_clk)
|
| 1212 |
|
|
if (i_rst)
|
| 1213 |
|
|
r_alu_pc_valid <= 1'b0;
|
| 1214 |
|
|
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
|
| 1215 |
|
|
r_alu_pc_valid <= 1'b1;
|
| 1216 |
|
|
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
|
| 1217 |
|
|
r_alu_pc_valid <= 1'b0;
|
| 1218 |
|
|
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
|
| 1219 |
|
|
always @(posedge i_clk)
|
| 1220 |
|
|
if (i_rst)
|
| 1221 |
|
|
mem_pc_valid <= 1'b0;
|
| 1222 |
|
|
else
|
| 1223 |
|
|
mem_pc_valid <= (mem_ce);
|
| 1224 |
|
|
|
| 1225 |
|
|
wire bus_lock;
|
| 1226 |
|
|
`ifdef OPT_PIPELINED
|
| 1227 |
|
|
generate
|
| 1228 |
|
|
if (IMPLEMENT_LOCK != 0)
|
| 1229 |
|
|
begin
|
| 1230 |
|
|
reg [1:0] r_bus_lock;
|
| 1231 |
|
|
initial r_bus_lock = 2'b00;
|
| 1232 |
|
|
always @(posedge i_clk)
|
| 1233 |
|
|
if (i_rst)
|
| 1234 |
|
|
r_bus_lock <= 2'b00;
|
| 1235 |
|
|
else if ((op_ce)&&(op_lock))
|
| 1236 |
|
|
r_bus_lock <= 2'b11;
|
| 1237 |
|
|
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
|
| 1238 |
|
|
r_bus_lock <= r_bus_lock + 2'b11;
|
| 1239 |
|
|
assign bus_lock = |r_bus_lock;
|
| 1240 |
|
|
end else begin
|
| 1241 |
|
|
assign bus_lock = 1'b0;
|
| 1242 |
|
|
end endgenerate
|
| 1243 |
|
|
`else
|
| 1244 |
|
|
assign bus_lock = 1'b0;
|
| 1245 |
|
|
`endif
|
| 1246 |
|
|
|
| 1247 |
|
|
`ifdef OPT_PIPELINED_BUS_ACCESS
|
| 1248 |
|
|
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
| 1249 |
|
|
(opn[0]), opB, opA, opR,
|
| 1250 |
|
|
mem_busy, mem_pipe_stalled,
|
| 1251 |
|
|
mem_valid, bus_err, mem_wreg, mem_result,
|
| 1252 |
|
|
mem_cyc_gbl, mem_cyc_lcl,
|
| 1253 |
|
|
mem_stb_gbl, mem_stb_lcl,
|
| 1254 |
|
|
mem_we, mem_addr, mem_data,
|
| 1255 |
|
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
| 1256 |
|
|
|
| 1257 |
|
|
`else // PIPELINED_BUS_ACCESS
|
| 1258 |
|
|
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
|
| 1259 |
|
|
(opn[0]), opB, opA, opR,
|
| 1260 |
|
|
mem_busy,
|
| 1261 |
|
|
mem_valid, bus_err, mem_wreg, mem_result,
|
| 1262 |
|
|
mem_cyc_gbl, mem_cyc_lcl,
|
| 1263 |
|
|
mem_stb_gbl, mem_stb_lcl,
|
| 1264 |
|
|
mem_we, mem_addr, mem_data,
|
| 1265 |
|
|
mem_ack, mem_stall, mem_err, i_wb_data);
|
| 1266 |
|
|
`endif // PIPELINED_BUS_ACCESS
|
| 1267 |
|
|
assign mem_rdbusy = ((mem_busy)&&(~mem_we));
|
| 1268 |
|
|
|
| 1269 |
|
|
// Either the prefetch or the instruction gets the memory bus, but
|
| 1270 |
|
|
// never both.
|
| 1271 |
|
|
wbdblpriarb #(32,AW) pformem(i_clk, i_rst,
|
| 1272 |
|
|
// Memory access to the arbiter, priority position
|
| 1273 |
|
|
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
|
| 1274 |
|
|
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
|
| 1275 |
|
|
// Prefetch access to the arbiter
|
| 1276 |
|
|
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
|
| 1277 |
|
|
pf_ack, pf_stall, pf_err,
|
| 1278 |
|
|
// Common wires, in and out, of the arbiter
|
| 1279 |
|
|
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
|
| 1280 |
|
|
o_wb_we, o_wb_addr, o_wb_data,
|
| 1281 |
|
|
i_wb_ack, i_wb_stall, i_wb_err);
|
| 1282 |
|
|
|
| 1283 |
|
|
|
| 1284 |
|
|
|
| 1285 |
|
|
//
|
| 1286 |
|
|
//
|
| 1287 |
|
|
//
|
| 1288 |
|
|
//
|
| 1289 |
|
|
//
|
| 1290 |
|
|
//
|
| 1291 |
|
|
//
|
| 1292 |
|
|
//
|
| 1293 |
|
|
// PIPELINE STAGE #5 :: Write-back results
|
| 1294 |
|
|
//
|
| 1295 |
|
|
//
|
| 1296 |
|
|
// This stage is not allowed to stall. If results are ready to be
|
| 1297 |
|
|
// written back, they are written back at all cost. Sleepy CPU's
|
| 1298 |
|
|
// won't prevent write back, nor debug modes, halting the CPU, nor
|
| 1299 |
|
|
// anything else. Indeed, the (master_ce) bit is only as relevant
|
| 1300 |
|
|
// as knowinig something is available for writeback.
|
| 1301 |
|
|
|
| 1302 |
|
|
//
|
| 1303 |
|
|
// Write back to our generic register set ...
|
| 1304 |
|
|
// When shall we write back? On one of two conditions
|
| 1305 |
|
|
// Note that the flags needed to be checked before issuing the
|
| 1306 |
|
|
// bus instruction, so they don't need to be checked here.
|
| 1307 |
|
|
// Further, alu_wr includes (set_cond), so we don't need to
|
| 1308 |
|
|
// check for that here either.
|
| 1309 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 1310 |
|
|
assign wr_reg_ce = (dbgv)||(mem_valid)
|
| 1311 |
|
|
||((~clear_pipeline)&&(~alu_illegal)
|
| 1312 |
|
|
&&(((alu_wr)&&(alu_valid))
|
| 1313 |
|
|
||(div_valid)||(fpu_valid)));
|
| 1314 |
|
|
`else
|
| 1315 |
|
|
assign wr_reg_ce = (dbgv)||(mem_valid)
|
| 1316 |
|
|
||((~clear_pipeline)
|
| 1317 |
|
|
&&(((alu_wr)&&(alu_valid))
|
| 1318 |
|
|
||(div_valid)||(fpu_valid)));
|
| 1319 |
|
|
`endif
|
| 1320 |
|
|
// Which register shall be written?
|
| 1321 |
|
|
// COULD SIMPLIFY THIS: by adding three bits to these registers,
|
| 1322 |
|
|
// One or PC, one for CC, and one for GIE match
|
| 1323 |
|
|
// Note that the alu_reg is the register to write on a divide or
|
| 1324 |
|
|
// FPU operation.
|
| 1325 |
|
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
|
| 1326 |
|
|
// Are we writing to the CC register?
|
| 1327 |
|
|
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
|
| 1328 |
|
|
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
|
| 1329 |
|
|
assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
|
| 1330 |
|
|
// Are we writing to the PC?
|
| 1331 |
|
|
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
|
| 1332 |
|
|
|
| 1333 |
|
|
// What value to write?
|
| 1334 |
|
|
assign wr_gpreg_vl = ((mem_valid) ? mem_result
|
| 1335 |
|
|
:((div_valid|fpu_valid))
|
| 1336 |
|
|
? ((div_valid) ? div_result:fpu_result)
|
| 1337 |
|
|
:((dbgv) ? dbg_val : alu_result));
|
| 1338 |
|
|
assign wr_spreg_vl = ((mem_valid) ? mem_result
|
| 1339 |
|
|
:((dbgv) ? dbg_val : alu_result));
|
| 1340 |
|
|
always @(posedge i_clk)
|
| 1341 |
|
|
if (wr_reg_ce)
|
| 1342 |
|
|
regset[wr_reg_id] <= wr_gpreg_vl;
|
| 1343 |
|
|
|
| 1344 |
|
|
//
|
| 1345 |
|
|
// Write back to the condition codes/flags register ...
|
| 1346 |
|
|
// When shall we write to our flags register? alF_wr already
|
| 1347 |
|
|
// includes the set condition ...
|
| 1348 |
|
|
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
|
| 1349 |
|
|
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
|
| 1350 |
|
|
udiv_err_flag, ubus_err_flag, trap, ill_err_u,
|
| 1351 |
|
|
ubreak, step, 1'b1, sleep,
|
| 1352 |
|
|
((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
|
| 1353 |
|
|
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
|
| 1354 |
|
|
idiv_err_flag, ibus_err_flag, trap, ill_err_i,
|
| 1355 |
|
|
break_en, 1'b0, 1'b0, sleep,
|
| 1356 |
|
|
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
|
| 1357 |
|
|
|
| 1358 |
|
|
|
| 1359 |
|
|
// What value to write?
|
| 1360 |
|
|
always @(posedge i_clk)
|
| 1361 |
|
|
// If explicitly writing the register itself
|
| 1362 |
|
|
if ((wr_reg_ce)&&(wr_write_ucc))
|
| 1363 |
|
|
flags <= wr_gpreg_vl[3:0];
|
| 1364 |
|
|
// Otherwise if we're setting the flags from an ALU operation
|
| 1365 |
|
|
else if ((wr_flags_ce)&&(alu_gie))
|
| 1366 |
|
|
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
| 1367 |
|
|
: alu_flags);
|
| 1368 |
|
|
|
| 1369 |
|
|
always @(posedge i_clk)
|
| 1370 |
|
|
if ((wr_reg_ce)&&(wr_write_scc))
|
| 1371 |
|
|
iflags <= wr_gpreg_vl[3:0];
|
| 1372 |
|
|
else if ((wr_flags_ce)&&(~alu_gie))
|
| 1373 |
|
|
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
|
| 1374 |
|
|
: alu_flags);
|
| 1375 |
|
|
|
| 1376 |
|
|
// The 'break' enable bit. This bit can only be set from supervisor
|
| 1377 |
|
|
// mode. It control what the CPU does upon encountering a break
|
| 1378 |
|
|
// instruction.
|
| 1379 |
|
|
//
|
| 1380 |
|
|
// The goal, upon encountering a break is that the CPU should stop and
|
| 1381 |
|
|
// not execute the break instruction, choosing instead to enter into
|
| 1382 |
|
|
// either interrupt mode or halt first.
|
| 1383 |
|
|
// if ((break_en) AND (break_instruction)) // user mode or not
|
| 1384 |
|
|
// HALT CPU
|
| 1385 |
|
|
// else if (break_instruction) // only in user mode
|
| 1386 |
|
|
// set an interrupt flag, set the user break bit,
|
| 1387 |
|
|
// go to supervisor mode, allow supervisor to step the CPU.
|
| 1388 |
|
|
// Upon a CPU halt, any break condition will be reset. The
|
| 1389 |
|
|
// external debugger will then need to deal with whatever
|
| 1390 |
|
|
// condition has taken place.
|
| 1391 |
|
|
initial break_en = 1'b0;
|
| 1392 |
|
|
always @(posedge i_clk)
|
| 1393 |
|
|
if ((i_rst)||(i_halt))
|
| 1394 |
|
|
break_en <= 1'b0;
|
| 1395 |
|
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
| 1396 |
|
|
break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
|
| 1397 |
|
|
|
| 1398 |
|
|
initial break_pending = 1'b0;
|
| 1399 |
|
|
always @(posedge i_clk)
|
| 1400 |
|
|
if ((i_rst)||(clear_pipeline)||(~opvalid))
|
| 1401 |
|
|
break_pending <= 1'b0;
|
| 1402 |
|
|
else if (op_break)
|
| 1403 |
|
|
break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy);
|
| 1404 |
|
|
else
|
| 1405 |
|
|
break_pending <= 1'b0;
|
| 1406 |
|
|
|
| 1407 |
|
|
|
| 1408 |
|
|
assign o_break = ((break_en)||(~op_gie))&&(break_pending)
|
| 1409 |
|
|
&&(~clear_pipeline)
|
| 1410 |
|
|
||((~alu_gie)&&(bus_err))
|
| 1411 |
|
|
||((~alu_gie)&&(div_error))
|
| 1412 |
|
|
||((~alu_gie)&&(fpu_error))
|
| 1413 |
|
|
||((~alu_gie)&&(alu_illegal));
|
| 1414 |
|
|
|
| 1415 |
|
|
// The sleep register. Setting the sleep register causes the CPU to
|
| 1416 |
|
|
// sleep until the next interrupt. Setting the sleep register within
|
| 1417 |
|
|
// interrupt mode causes the processor to halt until a reset. This is
|
| 1418 |
|
|
// a panic/fault halt. The trick is that you cannot be allowed to
|
| 1419 |
|
|
// set the sleep bit and switch to supervisor mode in the same
|
| 1420 |
|
|
// instruction: users are not allowed to halt the CPU.
|
| 1421 |
|
|
always @(posedge i_clk)
|
| 1422 |
|
|
if ((i_rst)||(w_switch_to_interrupt))
|
| 1423 |
|
|
sleep <= 1'b0;
|
| 1424 |
|
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
|
| 1425 |
|
|
// In supervisor mode, we have no protections. The
|
| 1426 |
|
|
// supervisor can set the sleep bit however he wants.
|
| 1427 |
|
|
// Well ... not quite. Switching to user mode and
|
| 1428 |
|
|
// sleep mode shouold only be possible if the interrupt
|
| 1429 |
|
|
// flag isn't set.
|
| 1430 |
|
|
// Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
|
| 1431 |
|
|
// don't set the sleep bit
|
| 1432 |
|
|
// otherwise however it would o.w. be set
|
| 1433 |
|
|
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
|
| 1434 |
|
|
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
|
| 1435 |
|
|
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
|
| 1436 |
|
|
// In user mode, however, you can only set the sleep
|
| 1437 |
|
|
// mode while remaining in user mode. You can't switch
|
| 1438 |
|
|
// to sleep mode *and* supervisor mode at the same
|
| 1439 |
|
|
// time, lest you halt the CPU.
|
| 1440 |
|
|
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
|
| 1441 |
|
|
|
| 1442 |
|
|
always @(posedge i_clk)
|
| 1443 |
|
|
if ((i_rst)||(w_switch_to_interrupt))
|
| 1444 |
|
|
step <= 1'b0;
|
| 1445 |
|
|
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
|
| 1446 |
|
|
step <= wr_spreg_vl[`CPU_STEP_BIT];
|
| 1447 |
|
|
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
|
| 1448 |
|
|
step <= 1'b0;
|
| 1449 |
|
|
|
| 1450 |
|
|
// The GIE register. Only interrupts can disable the interrupt register
|
| 1451 |
|
|
assign w_switch_to_interrupt = (gie)&&(
|
| 1452 |
|
|
// On interrupt (obviously)
|
| 1453 |
|
|
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
|
| 1454 |
|
|
// If we are stepping the CPU
|
| 1455 |
|
|
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
|
| 1456 |
|
|
// If we encounter a break instruction, if the break
|
| 1457 |
|
|
// enable isn't set.
|
| 1458 |
|
|
||((master_ce)&&(break_pending)&&(~break_en))
|
| 1459 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 1460 |
|
|
// On an illegal instruction
|
| 1461 |
|
|
||(alu_illegal)
|
| 1462 |
|
|
`endif
|
| 1463 |
|
|
// On division by zero. If the divide isn't
|
| 1464 |
|
|
// implemented, div_valid and div_error will be short
|
| 1465 |
|
|
// circuited and that logic will be bypassed
|
| 1466 |
|
|
||(div_error)
|
| 1467 |
|
|
// Same thing on a floating point error. Note that
|
| 1468 |
|
|
// fpu_error must *never* be set unless fpu_valid is
|
| 1469 |
|
|
// also set as well, else this will fail.
|
| 1470 |
|
|
||(fpu_error)
|
| 1471 |
|
|
//
|
| 1472 |
|
|
||(bus_err)
|
| 1473 |
|
|
// If we write to the CC register
|
| 1474 |
|
|
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
| 1475 |
|
|
&&(wr_reg_id[4])&&(wr_write_cc))
|
| 1476 |
|
|
);
|
| 1477 |
|
|
assign w_release_from_interrupt = (~gie)&&(~i_interrupt)
|
| 1478 |
|
|
// Then if we write the sCC register
|
| 1479 |
|
|
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
|
| 1480 |
|
|
&&(wr_write_scc))
|
| 1481 |
|
|
);
|
| 1482 |
|
|
always @(posedge i_clk)
|
| 1483 |
|
|
if (i_rst)
|
| 1484 |
|
|
gie <= 1'b0;
|
| 1485 |
|
|
else if (w_switch_to_interrupt)
|
| 1486 |
|
|
gie <= 1'b0;
|
| 1487 |
|
|
else if (w_release_from_interrupt)
|
| 1488 |
|
|
gie <= 1'b1;
|
| 1489 |
|
|
|
| 1490 |
|
|
initial trap = 1'b0;
|
| 1491 |
|
|
always @(posedge i_clk)
|
| 1492 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1493 |
|
|
trap <= 1'b0;
|
| 1494 |
|
|
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
|
| 1495 |
|
|
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
|
| 1496 |
|
|
trap <= 1'b1;
|
| 1497 |
|
|
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
|
| 1498 |
|
|
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
|
| 1499 |
|
|
|
| 1500 |
|
|
initial ubreak = 1'b0;
|
| 1501 |
|
|
always @(posedge i_clk)
|
| 1502 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1503 |
|
|
ubreak <= 1'b0;
|
| 1504 |
|
|
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
|
| 1505 |
|
|
ubreak <= 1'b1;
|
| 1506 |
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
| 1507 |
|
|
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
|
| 1508 |
|
|
|
| 1509 |
|
|
|
| 1510 |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION
|
| 1511 |
|
|
initial ill_err_i = 1'b0;
|
| 1512 |
|
|
always @(posedge i_clk)
|
| 1513 |
|
|
if (i_rst)
|
| 1514 |
|
|
ill_err_i <= 1'b0;
|
| 1515 |
|
|
// Only the debug interface can clear this bit
|
| 1516 |
|
|
else if ((dbgv)&&(wr_write_scc))
|
| 1517 |
|
|
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
|
| 1518 |
|
|
else if ((alu_illegal)&&(~alu_gie))
|
| 1519 |
|
|
ill_err_i <= 1'b1;
|
| 1520 |
|
|
initial ill_err_u = 1'b0;
|
| 1521 |
|
|
always @(posedge i_clk)
|
| 1522 |
|
|
// The bit is automatically cleared on release from interrupt
|
| 1523 |
|
|
// or reset
|
| 1524 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1525 |
|
|
ill_err_u <= 1'b0;
|
| 1526 |
|
|
// If the supervisor (or debugger) writes to this register,
|
| 1527 |
|
|
// clearing the bit, then clear it
|
| 1528 |
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
| 1529 |
|
|
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
|
| 1530 |
|
|
else if ((alu_illegal)&&(alu_gie))
|
| 1531 |
|
|
ill_err_u <= 1'b1;
|
| 1532 |
|
|
`else
|
| 1533 |
|
|
assign ill_err_u = 1'b0;
|
| 1534 |
|
|
assign ill_err_i = 1'b0;
|
| 1535 |
|
|
`endif
|
| 1536 |
|
|
// Supervisor/interrupt bus error flag -- this will crash the CPU if
|
| 1537 |
|
|
// ever set.
|
| 1538 |
|
|
initial ibus_err_flag = 1'b0;
|
| 1539 |
|
|
always @(posedge i_clk)
|
| 1540 |
|
|
if (i_rst)
|
| 1541 |
|
|
ibus_err_flag <= 1'b0;
|
| 1542 |
|
|
else if ((dbgv)&&(wr_write_scc))
|
| 1543 |
|
|
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
| 1544 |
|
|
else if ((bus_err)&&(~alu_gie))
|
| 1545 |
|
|
ibus_err_flag <= 1'b1;
|
| 1546 |
|
|
// User bus error flag -- if ever set, it will cause an interrupt to
|
| 1547 |
|
|
// supervisor mode.
|
| 1548 |
|
|
initial ubus_err_flag = 1'b0;
|
| 1549 |
|
|
always @(posedge i_clk)
|
| 1550 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1551 |
|
|
ubus_err_flag <= 1'b0;
|
| 1552 |
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
|
| 1553 |
|
|
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
|
| 1554 |
|
|
else if ((bus_err)&&(alu_gie))
|
| 1555 |
|
|
ubus_err_flag <= 1'b1;
|
| 1556 |
|
|
|
| 1557 |
|
|
generate
|
| 1558 |
|
|
if (IMPLEMENT_DIVIDE != 0)
|
| 1559 |
|
|
begin
|
| 1560 |
|
|
reg r_idiv_err_flag, r_udiv_err_flag;
|
| 1561 |
|
|
|
| 1562 |
|
|
// Supervisor/interrupt divide (by zero) error flag -- this will
|
| 1563 |
|
|
// crash the CPU if ever set. This bit is thus available for us
|
| 1564 |
|
|
// to be able to tell if/why the CPU crashed.
|
| 1565 |
|
|
initial r_idiv_err_flag = 1'b0;
|
| 1566 |
|
|
always @(posedge i_clk)
|
| 1567 |
|
|
if (i_rst)
|
| 1568 |
|
|
r_idiv_err_flag <= 1'b0;
|
| 1569 |
|
|
else if ((dbgv)&&(wr_write_scc))
|
| 1570 |
|
|
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
| 1571 |
|
|
else if ((div_error)&&(~alu_gie))
|
| 1572 |
|
|
r_idiv_err_flag <= 1'b1;
|
| 1573 |
|
|
// User divide (by zero) error flag -- if ever set, it will
|
| 1574 |
|
|
// cause a sudden switch interrupt to supervisor mode.
|
| 1575 |
|
|
initial r_udiv_err_flag = 1'b0;
|
| 1576 |
|
|
always @(posedge i_clk)
|
| 1577 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1578 |
|
|
r_udiv_err_flag <= 1'b0;
|
| 1579 |
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
| 1580 |
|
|
&&(wr_write_ucc))
|
| 1581 |
|
|
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
|
| 1582 |
|
|
else if ((div_error)&&(alu_gie))
|
| 1583 |
|
|
r_udiv_err_flag <= 1'b1;
|
| 1584 |
|
|
|
| 1585 |
|
|
assign idiv_err_flag = r_idiv_err_flag;
|
| 1586 |
|
|
assign udiv_err_flag = r_udiv_err_flag;
|
| 1587 |
|
|
end else begin
|
| 1588 |
|
|
assign idiv_err_flag = 1'b0;
|
| 1589 |
|
|
assign udiv_err_flag = 1'b0;
|
| 1590 |
|
|
end endgenerate
|
| 1591 |
|
|
|
| 1592 |
|
|
generate
|
| 1593 |
|
|
if (IMPLEMENT_FPU !=0)
|
| 1594 |
|
|
begin
|
| 1595 |
|
|
// Supervisor/interrupt floating point error flag -- this will
|
| 1596 |
|
|
// crash the CPU if ever set.
|
| 1597 |
|
|
reg r_ifpu_err_flag, r_ufpu_err_flag;
|
| 1598 |
|
|
initial r_ifpu_err_flag = 1'b0;
|
| 1599 |
|
|
always @(posedge i_clk)
|
| 1600 |
|
|
if (i_rst)
|
| 1601 |
|
|
r_ifpu_err_flag <= 1'b0;
|
| 1602 |
|
|
else if ((dbgv)&&(wr_write_scc))
|
| 1603 |
|
|
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
| 1604 |
|
|
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
|
| 1605 |
|
|
r_ifpu_err_flag <= 1'b1;
|
| 1606 |
|
|
// User floating point error flag -- if ever set, it will cause
|
| 1607 |
|
|
// a sudden switch interrupt to supervisor mode.
|
| 1608 |
|
|
initial r_ufpu_err_flag = 1'b0;
|
| 1609 |
|
|
always @(posedge i_clk)
|
| 1610 |
|
|
if ((i_rst)&&(w_release_from_interrupt))
|
| 1611 |
|
|
r_ufpu_err_flag <= 1'b0;
|
| 1612 |
|
|
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
|
| 1613 |
|
|
&&(wr_write_ucc))
|
| 1614 |
|
|
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
|
| 1615 |
|
|
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
|
| 1616 |
|
|
r_ufpu_err_flag <= 1'b1;
|
| 1617 |
|
|
|
| 1618 |
|
|
assign ifpu_err_flag = r_ifpu_err_flag;
|
| 1619 |
|
|
assign ufpu_err_flag = r_ufpu_err_flag;
|
| 1620 |
|
|
end else begin
|
| 1621 |
|
|
assign ifpu_err_flag = 1'b0;
|
| 1622 |
|
|
assign ufpu_err_flag = 1'b0;
|
| 1623 |
|
|
end endgenerate
|
| 1624 |
|
|
|
| 1625 |
|
|
`ifdef OPT_VLIW
|
| 1626 |
|
|
reg r_ihalt_phase, r_uhalt_phase;
|
| 1627 |
|
|
|
| 1628 |
|
|
initial r_ihalt_phase = 0;
|
| 1629 |
|
|
initial r_uhalt_phase = 0;
|
| 1630 |
|
|
always @(posedge i_clk)
|
| 1631 |
|
|
if (i_rst)
|
| 1632 |
|
|
r_ihalt_phase <= 1'b0;
|
| 1633 |
|
|
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
|
| 1634 |
|
|
r_ihalt_phase <= alu_phase;
|
| 1635 |
|
|
always @(posedge i_clk)
|
| 1636 |
|
|
if ((i_rst)||(w_release_from_interrupt))
|
| 1637 |
|
|
r_uhalt_phase <= 1'b0;
|
| 1638 |
|
|
else if ((alu_gie)&&(alu_pc_valid))
|
| 1639 |
|
|
r_uhalt_phase <= alu_phase;
|
| 1640 |
|
|
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
|
| 1641 |
|
|
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
|
| 1642 |
|
|
|
| 1643 |
|
|
assign ihalt_phase = r_ihalt_phase;
|
| 1644 |
|
|
assign uhalt_phase = r_uhalt_phase;
|
| 1645 |
|
|
`else
|
| 1646 |
|
|
assign ihalt_phase = 1'b0;
|
| 1647 |
|
|
assign uhalt_phase = 1'b0;
|
| 1648 |
|
|
`endif
|
| 1649 |
|
|
|
| 1650 |
|
|
//
|
| 1651 |
|
|
// Write backs to the PC register, and general increments of it
|
| 1652 |
|
|
// We support two: upc and ipc. If the instruction is normal,
|
| 1653 |
|
|
// we increment upc, if interrupt level we increment ipc. If
|
| 1654 |
|
|
// the instruction writes the PC, we write whichever PC is appropriate.
|
| 1655 |
|
|
//
|
| 1656 |
|
|
// Do we need to all our partial results from the pipeline?
|
| 1657 |
|
|
// What happens when the pipeline has gie and ~gie instructions within
|
| 1658 |
|
|
// it? Do we clear both? What if a gie instruction tries to clear
|
| 1659 |
|
|
// a non-gie instruction?
|
| 1660 |
|
|
always @(posedge i_clk)
|
| 1661 |
|
|
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
|
| 1662 |
|
|
upc <= wr_spreg_vl[(AW-1):0];
|
| 1663 |
|
|
else if ((alu_gie)&&
|
| 1664 |
|
|
(((alu_pc_valid)&&(~clear_pipeline))
|
| 1665 |
|
|
||(mem_pc_valid)))
|
| 1666 |
|
|
upc <= alu_pc;
|
| 1667 |
|
|
|
| 1668 |
|
|
always @(posedge i_clk)
|
| 1669 |
|
|
if (i_rst)
|
| 1670 |
|
|
ipc <= RESET_ADDRESS;
|
| 1671 |
|
|
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
|
| 1672 |
|
|
ipc <= wr_spreg_vl[(AW-1):0];
|
| 1673 |
|
|
else if ((~alu_gie)&&
|
| 1674 |
|
|
(((alu_pc_valid)&&(~clear_pipeline))
|
| 1675 |
|
|
||(mem_pc_valid)))
|
| 1676 |
|
|
ipc <= alu_pc;
|
| 1677 |
|
|
|
| 1678 |
|
|
always @(posedge i_clk)
|
| 1679 |
|
|
if (i_rst)
|
| 1680 |
|
|
pf_pc <= RESET_ADDRESS;
|
| 1681 |
|
|
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
|
| 1682 |
|
|
pf_pc <= ipc;
|
| 1683 |
|
|
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
|
| 1684 |
|
|
pf_pc <= upc;
|
| 1685 |
|
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
| 1686 |
|
|
pf_pc <= wr_spreg_vl[(AW-1):0];
|
| 1687 |
|
|
`ifdef OPT_PIPELINED
|
| 1688 |
|
|
else if ((dcd_early_branch)&&(~clear_pipeline))
|
| 1689 |
|
|
pf_pc <= dcd_branch_pc + 1;
|
| 1690 |
|
|
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
|
| 1691 |
|
|
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
|
| 1692 |
|
|
`else
|
| 1693 |
|
|
else if ((alu_gie==gie)&&(
|
| 1694 |
|
|
((alu_pc_valid)&&(~clear_pipeline))
|
| 1695 |
|
|
||(mem_pc_valid)))
|
| 1696 |
|
|
pf_pc <= alu_pc;
|
| 1697 |
|
|
`endif
|
| 1698 |
|
|
|
| 1699 |
|
|
initial new_pc = 1'b1;
|
| 1700 |
|
|
always @(posedge i_clk)
|
| 1701 |
|
|
if ((i_rst)||(i_clear_pf_cache))
|
| 1702 |
|
|
new_pc <= 1'b1;
|
| 1703 |
|
|
else if (w_switch_to_interrupt)
|
| 1704 |
|
|
new_pc <= 1'b1;
|
| 1705 |
|
|
else if (w_release_from_interrupt)
|
| 1706 |
|
|
new_pc <= 1'b1;
|
| 1707 |
|
|
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
|
| 1708 |
|
|
new_pc <= 1'b1;
|
| 1709 |
|
|
else
|
| 1710 |
|
|
new_pc <= 1'b0;
|
| 1711 |
|
|
|
| 1712 |
|
|
`ifdef OPT_PIPELINED
|
| 1713 |
|
|
reg r_clear_icache;
|
| 1714 |
|
|
initial r_clear_icache = 1'b1;
|
| 1715 |
|
|
always @(posedge i_clk)
|
| 1716 |
|
|
if ((i_rst)||(i_clear_pf_cache))
|
| 1717 |
|
|
r_clear_icache <= 1'b1;
|
| 1718 |
|
|
else if ((wr_reg_ce)&&(wr_write_scc))
|
| 1719 |
|
|
r_clear_icache <= wr_spreg_vl[`CPU_CLRCACHE_BIT];
|
| 1720 |
|
|
else
|
| 1721 |
|
|
r_clear_icache <= 1'b0;
|
| 1722 |
|
|
assign w_clear_icache = r_clear_icache;
|
| 1723 |
|
|
`else
|
| 1724 |
|
|
assign w_clear_icache = 1'b0;
|
| 1725 |
|
|
`endif
|
| 1726 |
|
|
|
| 1727 |
|
|
//
|
| 1728 |
|
|
// The debug interface
|
| 1729 |
|
|
generate
|
| 1730 |
|
|
if (AW<32)
|
| 1731 |
|
|
begin
|
| 1732 |
|
|
always @(posedge i_clk)
|
| 1733 |
|
|
begin
|
| 1734 |
|
|
o_dbg_reg <= regset[i_dbg_reg];
|
| 1735 |
|
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
| 1736 |
|
|
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
|
| 1737 |
|
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
| 1738 |
|
|
begin
|
| 1739 |
|
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
| 1740 |
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
| 1741 |
|
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
| 1742 |
|
|
end
|
| 1743 |
|
|
end
|
| 1744 |
|
|
end else begin
|
| 1745 |
|
|
always @(posedge i_clk)
|
| 1746 |
|
|
begin
|
| 1747 |
|
|
o_dbg_reg <= regset[i_dbg_reg];
|
| 1748 |
|
|
if (i_dbg_reg[3:0] == `CPU_PC_REG)
|
| 1749 |
|
|
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
|
| 1750 |
|
|
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
|
| 1751 |
|
|
begin
|
| 1752 |
|
|
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
|
| 1753 |
|
|
o_dbg_reg[31:23] <= w_cpu_info;
|
| 1754 |
|
|
o_dbg_reg[`CPU_GIE_BIT] <= gie;
|
| 1755 |
|
|
end
|
| 1756 |
|
|
end
|
| 1757 |
|
|
end endgenerate
|
| 1758 |
|
|
|
| 1759 |
|
|
always @(posedge i_clk)
|
| 1760 |
|
|
o_dbg_cc <= { o_break, bus_err, gie, sleep };
|
| 1761 |
|
|
|
| 1762 |
|
|
always @(posedge i_clk)
|
| 1763 |
|
|
r_halted <= (i_halt)&&(
|
| 1764 |
|
|
// To be halted, any long lasting instruction must
|
| 1765 |
|
|
// be completed.
|
| 1766 |
|
|
(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
|
| 1767 |
|
|
&&(~div_busy)&&(~fpu_busy)
|
| 1768 |
|
|
// Operations must either be valid, or illegal
|
| 1769 |
|
|
&&((opvalid)||(i_rst)||(dcd_illegal))
|
| 1770 |
|
|
// Decode stage must be either valid, in reset, or ill
|
| 1771 |
|
|
&&((dcdvalid)||(i_rst)||(pf_illegal)));
|
| 1772 |
|
|
assign o_dbg_stall = ~r_halted;
|
| 1773 |
|
|
|
| 1774 |
|
|
//
|
| 1775 |
|
|
//
|
| 1776 |
|
|
// Produce accounting outputs: Account for any CPU stalls, so we can
|
| 1777 |
|
|
// later evaluate how well we are doing.
|
| 1778 |
|
|
//
|
| 1779 |
|
|
//
|
| 1780 |
|
|
assign o_op_stall = (master_ce)&&(op_stall);
|
| 1781 |
|
|
assign o_pf_stall = (master_ce)&&(~pf_valid);
|
| 1782 |
|
|
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
|
| 1783 |
|
|
|
| 1784 |
|
|
`ifdef DEBUG_SCOPE
|
| 1785 |
|
|
reg [31:0] r_stack;
|
| 1786 |
|
|
always @(posedge i_clk)
|
| 1787 |
|
|
if ((wr_reg_ce)&&(wr_reg_id == 5'h0d))
|
| 1788 |
|
|
r_stack <= wr_gpreg_vl;
|
| 1789 |
|
|
reg r_stack_pre, r_stack_post;
|
| 1790 |
|
|
always @(posedge i_clk)
|
| 1791 |
|
|
r_stack_pre <= (r_stack == 32'h03fff);
|
| 1792 |
|
|
always @(posedge i_clk)
|
| 1793 |
|
|
r_stack_post <= (r_stack == 32'h03eeb);
|
| 1794 |
|
|
|
| 1795 |
|
|
always @(posedge i_clk)
|
| 1796 |
|
|
o_debug <= {
|
| 1797 |
|
|
/*
|
| 1798 |
|
|
o_break, i_wb_err, pf_pc[1:0],
|
| 1799 |
|
|
flags,
|
| 1800 |
|
|
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
|
| 1801 |
|
|
op_ce, alu_ce, mem_ce,
|
| 1802 |
|
|
//
|
| 1803 |
|
|
master_ce, opvalid_alu, opvalid_mem,
|
| 1804 |
|
|
//
|
| 1805 |
|
|
alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
|
| 1806 |
|
|
mem_we,
|
| 1807 |
|
|
// ((opvalid_alu)&&(alu_stall))
|
| 1808 |
|
|
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
|
| 1809 |
|
|
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
|
| 1810 |
|
|
// opA[23:20], opA[3:0],
|
| 1811 |
|
|
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
|
| 1812 |
|
|
*/
|
| 1813 |
|
|
/*
|
| 1814 |
|
|
i_rst, master_ce, (new_pc),
|
| 1815 |
|
|
((dcd_early_branch)&&(dcdvalid)),
|
| 1816 |
|
|
pf_valid, pf_illegal,
|
| 1817 |
|
|
op_ce, dcd_ce, dcdvalid, dcd_stalled,
|
| 1818 |
|
|
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
|
| 1819 |
|
|
pf_pc[7:0], pf_addr[7:0]
|
| 1820 |
|
|
*/
|
| 1821 |
|
|
|
| 1822 |
|
|
(i_wb_err)||(r_stack_post), (gie)||(r_stack_pre), (alu_illegal)||(r_stack_post),
|
| 1823 |
|
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
| 1824 |
|
|
mem_busy,
|
| 1825 |
|
|
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
|
| 1826 |
|
|
o_wb_addr[8:0] }
|
| 1827 |
|
|
: { instruction[31:21] },
|
| 1828 |
|
|
pf_valid, (pf_valid) ? alu_pc[14:0]
|
| 1829 |
|
|
:{ pf_cyc, pf_stb, pf_pc[12:0] }
|
| 1830 |
|
|
|
| 1831 |
|
|
/*
|
| 1832 |
|
|
i_wb_err, gie, new_pc, dcd_early_branch, // 4
|
| 1833 |
|
|
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
|
| 1834 |
|
|
instruction[30:27], // 4
|
| 1835 |
|
|
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
|
| 1836 |
|
|
dcdvalid,
|
| 1837 |
|
|
((dcd_early_branch)&&(~clear_pipeline)) // 15
|
| 1838 |
|
|
? dcd_branch_pc[14:0]:pf_pc[14:0]
|
| 1839 |
|
|
*/
|
| 1840 |
|
|
};
|
| 1841 |
|
|
`endif
|
| 1842 |
|
|
|
| 1843 |
|
|
/*
|
| 1844 |
|
|
always @(posedge i_clk)
|
| 1845 |
|
|
o_debug <= {
|
| 1846 |
|
|
// External control interaction (4b)
|
| 1847 |
|
|
i_halt, i_rst, i_clear_cache, o_break,
|
| 1848 |
|
|
// Bus interaction (8b)
|
| 1849 |
|
|
pf_cyc,(o_wb_gbl_cyc|o_wb_lcl_cyc), o_wb_gbl_stb, o_wb_lcl_stb,
|
| 1850 |
|
|
o_wb_we, i_wb_ack, i_wb_stall, i_wb_err,
|
| 1851 |
|
|
// PC control (4b)
|
| 1852 |
|
|
gie, new_pc, dcd_early_branch, 1'b0,
|
| 1853 |
|
|
// Our list of pipeline stage values (8b)
|
| 1854 |
|
|
pf_valid, pf_illegal, dcdvalid, opvalid, alu_valid, mem_valid,
|
| 1855 |
|
|
alu_pc_valid, mem_pc_valid,
|
| 1856 |
|
|
// Our list of circuit enables ... (8b)
|
| 1857 |
|
|
(new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
|
| 1858 |
|
|
dcd_ce, op_ce, alu_ce, mem_ce, wr_reg_ce, wr_flags_ce,
|
| 1859 |
|
|
1'b0,
|
| 1860 |
|
|
// Useful PC values (64b)
|
| 1861 |
|
|
((dcd_early_branch)&&(~clear_pipeline))
|
| 1862 |
|
|
? dcd_branch_pc[15:0]:pf_pc[15:0],
|
| 1863 |
|
|
(gie)?upc[15:0]:ipc[15:0], instruction_pc[15:0], instruction[31:16] };
|
| 1864 |
|
|
*/
|
| 1865 |
|
|
|
| 1866 |
|
|
endmodule
|
