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///////////////////////////////////////////////////////////////////////////////

//

// Filename:    zipcpuhs.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     This is the top level module holding the core of the Zip CPU

//              together.  The Zip CPU is designed to be as simple as possible.

//      (actual implementation aside ...)  The instruction set is about as

//      RISC as you can get, there are only 26 instruction types supported, not

//      including the floating point instruction set.  Please see the

//      accompanying spec.pdf file for a description of these instructions.

//

//      All instructions are 32-bits wide.  All bus accesses, both address and

//      data, are 32-bits over a wishbone bus.

//

//

//      This version of the ZipCPU has been modified for "high speed" operation.

//      By that I mean, it has been modified so that it can handle a high speed

//      system clock.  The nominal five stage pipeline has therefore been

//      broken into nine pieces, as outlined below:

//

//              1. Prefetch, returns the instruction from memory. 

//

//              2. Instruction Decode: triplet instructions, VLIW upper half,

//                      VLIW lower half, and normal instructions

//

//              3. Instruction Decode: Select among the four types of 

//                      instructions

//

//              4. Read Operand B

//

//              5. Read Operand A, add the immediate offset to Operand B

//

//              6. 16 ALU operations

//

//              7. Select among ALU results

//

//              8. Select from ALU, Memory, Divide, FPU results

//

//              9. Write-back Results

//

//      Further information about the ZipCPU may be found in the spec.pdf file.

//      (The documentation within this file is likely to become out of date

//      and out of sync with the spec.pdf, so look to the spec.pdf for

//      accurate and up to date information.)

//

//

//      A note about pipelining.  The approach used to accommodate pipelining

//      in this implementation assumes that if will be impossible to tell if

//      a particular stage will stall until the logic for that stage completes.

//      There is no time, therefore, for the stall logic to ripple from the

//      end of the pipeline to the beginning.  At best, it can ripple from

//      one stage to the next.  Stall logic, therefore, is latched in a 

//      FLIP-FLOP, rather than done in a combinatorial fashion.  Hopefully,

//      you'll have a copy of the stall logic slides.  If not, here's the

//      outline of how stalls will be done:

//

//      assign  (n)_slp = // stall logic for location n, based upon the prior

//                      //      stages info

//      assign  (n)_slc = // stall logic for location n, based upon a copy of

//                      //      what was in the prior stage

//

//

//      // We'll shorten _valid to _v, _stall to _s, _copy to _c

//      always @(posedge i_clk)

//              if ((i_rst)||(clear_pipeline)

//                      (n)_v = 0;

//              else if (!(n)_stall)

//                      (n)_v = ( (n-1)_v && (!(n)_slp) );

//              else

//                      (n)_v = ( !(n)_slc );

//

//      always @(posedge i_clk)

//              if ((i_rst)||(clear_pipeline)

//                      (n)_s = 1'b0;

//              else if (!(n)_s)

//                      (n)_s = ((n-1)_v) && ( (n)_slp || (n+1)_s );

//              else

//                      (n)_s = ( (n)_slc || (n+1)_s );

//                      

//      always @(posedge i_clk)

//              if ((n)_s)

//                      (n)_data  = PROCESS[(n)_c];

//                      // Can't chnge copy if not stalled

//              else

//                      (n)_data = PROCESS[(n-1)_data];

//                      (n)_c <= (n-1)_data;

//

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

///////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015-2016, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////////

//

// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined

// fetches are more complicated and therefore use more FPGA resources, while

// single fetches will cause the CPU to stall for about 5 stalls each 

// instruction cycle, effectively reducing the instruction count per clock to

// about 0.2.  However, the area cost may be worth it.  Consider:

//

//      Slice LUTs              ZipSystem       ZipCPU

//      Single Fetching         2521            1734

//      Pipelined fetching      2796            2046

//

//

//

`define CPU_CC_REG      4'he

`define CPU_PC_REG      4'hf

`define CPU_CLRCACHE_BIT 14     // Floating point error flag, set on error

`define CPU_PHASE_BIT   13      // Floating point error flag, set on error

`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error

`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero

`define CPU_BUSERR_BIT  10      // Bus error flag, set on error

`define CPU_TRAP_BIT    9       // User TRAP has taken place

`define CPU_ILL_BIT     8       // Illegal instruction

`define CPU_BREAK_BIT   7

`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions

`define CPU_GIE_BIT     5

`define CPU_SLEEP_BIT   4

// Compile time defines

//

`include "cpudefs.v"

//

//

module  zipcpuhs(i_clk, i_rst, i_interrupt,

                // Debug interface

                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,

                        o_dbg_stall, o_dbg_reg, o_dbg_cc,

                        o_break,

                // CPU interface to the wishbone bus

                o_wb_gbl_cyc, o_wb_gbl_stb,

                        o_wb_lcl_cyc, o_wb_lcl_stb,

                        o_wb_we, o_wb_addr, o_wb_data,

                        i_wb_ack, i_wb_stall, i_wb_data,

                        i_wb_err,

                // Accounting/CPU usage interface

                o_op_stall, o_pf_stall, o_i_count

`ifdef  DEBUG_SCOPE

                , o_debug

`endif

                );

        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,

                        LGICACHE=6;

`ifdef  OPT_MULTIPLY

        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;

`else

        parameter       IMPLEMENT_MPY = 0;

`endif

`ifdef  OPT_DIVIDE

        parameter       IMPLEMENT_DIVIDE = 1;

`else

        parameter       IMPLEMENT_DIVIDE = 0;

`endif

`ifdef  OPT_IMPLEMENT_FPU

        parameter       IMPLEMENT_FPU = 1,

`else

        parameter       IMPLEMENT_FPU = 0,

`endif

                        IMPLEMENT_LOCK=1;

`ifdef  OPT_EARLY_BRANCHING

        parameter       EARLY_BRANCHING = 1;

`else

        parameter       EARLY_BRANCHING = 0;

`endif

        parameter       AW=ADDRESS_WIDTH;

        input                   i_clk, i_rst, i_interrupt;

        // Debug interface -- inputs

        input                   i_halt, i_clear_pf_cache;

        input           [4:0]    i_dbg_reg;

        input                   i_dbg_we;

        input           [31:0]   i_dbg_data;

        // Debug interface -- outputs

        output  wire            o_dbg_stall;

        output  reg     [31:0]   o_dbg_reg;

        output  reg     [3:0]    o_dbg_cc;

        output  wire            o_break;

        // Wishbone interface -- outputs

        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;

        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;

        output  wire    [(AW-1):0]       o_wb_addr;

        output  wire    [31:0]   o_wb_data;

        // Wishbone interface -- inputs

        input                   i_wb_ack, i_wb_stall;

        input           [31:0]   i_wb_data;

        input                   i_wb_err;

        // Accounting outputs ... to help us count stalls and usage

        output  wire            o_op_stall;

        output  wire            o_pf_stall;

        output  wire            o_i_count;

        //

`ifdef  DEBUG_SCOPE

        output  reg     [31:0]   o_debug;

`endif

        // Registers

        //

        //      The distributed RAM style comment is necessary on the

        // SPARTAN6 with XST to prevent XST from oversimplifying the register

        // set and in the process ruining everything else.  It basically

        // optimizes logic away, to where it no longer works.  The logic

        // as described herein will work, this just makes sure XST implements

        // that logic.

        //

        (* ram_style = "distributed" *)

        reg     [31:0]   regset [0:31];

        // Condition codes

        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z

        reg     [3:0]    flags, iflags;

        wire    [14:0]   w_uflags, w_iflags;

        reg             trap, break_en, step, gie, sleep, r_halted,

                        break_pending;

        wire            w_clear_icache;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg             ill_err_u, ill_err_i;

`else

        wire            ill_err_u, ill_err_i;

`endif

        reg             ubreak;

        reg             ibus_err_flag, ubus_err_flag;

        wire            idiv_err_flag, udiv_err_flag;

        wire            ifpu_err_flag, ufpu_err_flag;

        wire            ihalt_phase, uhalt_phase;

        // The master chip enable

        wire            master_ce;

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Variable declarations

        //

        reg     [(AW-1):0]       pf_pc;

        reg     new_pc;

        wire    clear_pipeline;

        assign  clear_pipeline = new_pc;

        wire            dcd_stalled;

        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;

        wire    [(AW-1):0]       pf_addr;

        wire    [31:0]           pf_data;

        wire    [31:0]           instruction;

        wire    [(AW-1):0]       instruction_pc;

        wire    pf_v, instruction_gie, pf_illegal;

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Variable declarations

        //

        //

        wire            op_stall, dcd_ce, dcd_phase;

        wire    [3:0]    dcdOp;

        wire    [4:0]    dcd_iA, dcd_iB, dcd_iR;

        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;

        wire    [3:0]    dcdF;

        wire            dcd_wR, dcd_rA, dcd_rB,

                                dcdALU, dcdM, dcdDV, dcdFP,

                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,

                                dcd_pipe, dcd_ljmp;

        reg     [1:0]    r_dcdvalid;

        wire            dcd_v;

        wire    [(AW-1):0]       dcd_pc;

        wire    [31:0]   dcd_I;

        wire            dcd_zI; // true if dcdI == 0

        wire    dcdA_stall, dcdB_stall, dcdF_stall;

        wire    dcd_illegal;

        wire                    dcd_early_branch;

        wire    [(AW-1):0]       dcd_branch_pc;

        //

        //

        //      PIPELINE STAGE #3a :: Read Operands

        //              Variable declarations

        //

        //

        //

        // Now, let's read our operands

        reg             opa_v, opa_DV, opa_FP, opa_ALU, opa_M,

                        opa_rA, opa_rB;

        reg     [4:0]    alu_reg;

        reg     [3:0]    opa_opn;

        reg     [4:0]    opa_R, opa_iA;

        reg     [31:0]   r_opa_B;

        reg     [(AW-1):0]       opa_pc;

        wire    [31:0]   opA_nowait, opa_Bnowait, opa_A, opa_B, opa_I;

        reg             opa_wR, opa_ccR, opa_wF, opa_gie;

        wire    [13:0]   opa_Fl;

        reg     [5:0]    r_opa_F;

        wire    [7:0]    opa_F;

        wire            opa_ce, opa_phase, opa_pipe;

        // Some pipeline control wires

        reg     opa_A_alu, opa_A_mem;

        reg     opa_B_alu, opa_B_mem;

        reg     opa_illegal;

        reg     opa_break;

        reg     opa_lock;

        //

        //

        //      PIPELINE STAGE #3b :: Read Operands

        //              Variable declarations

        //

        //

        //

        // Now, let's read our operands

        reg     [3:0]    opb_opn;

        reg             opb_v, opb_v_mem, opb_v_alu;

        reg             opb_v_div, opb_v_fpu;

        reg     [4:0]    opb_R;

        reg     [31:0]   r_opb_A, r_opb_B;

        reg     [(AW-1):0]       opb_pc;

        wire    [31:0]   opb_A_nowait, opb_B_nowait, opb_A, opb_B;

        reg             opb_wR, opb_ccR, opb_wF, opb_gie;

        wire    [13:0]   opb_Fl;

        reg     [5:0]    r_opb_F;

        wire    [7:0]    opb_F;

        wire            opb_ce, opb_phase, opb_pipe;

        // Some pipeline control wires

        reg     opb_A_alu, opb_A_mem;

        reg     opb_B_alu, opb_B_mem;

        reg     opb_illegal;

        reg     opb_break;

        reg     opb_lock;

        //

        //

        //      PIPELINE STAGE #4 :: ALU / Memory / Divide

        //              Variable declarations

        //

        //

        reg             stage_busy;

        reg     [(AW-1):0]       alu_pc;

        reg             r_alu_pc_v, mem_pc_v;

        wire            alu_pc_v;

        wire            alu_phase;

        wire            alu_ce, alu_stall;

        wire    [31:0]   alu_result;

        wire    [3:0]    alu_flags;

        wire            alu_v, alu_busy;

        wire            set_cond;

        reg             alu_wr, alF_wr, alu_gie;

        wire            alu_illegal_op;

        wire            alu_illegal;

        wire    mem_ce, mem_stalled;

        wire    mem_pipe_stalled;

        wire    mem_v, mem_ack, mem_stall, mem_err, bus_err,

                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;

        wire    [4:0]            mem_wreg;

        wire                    mem_busy, mem_rdbusy;

        wire    [(AW-1):0]       mem_addr;

        wire    [31:0]           mem_data, mem_result;

        wire    div_ce, div_error, div_busy, div_v;

        wire    [31:0]   div_result;

        wire    [3:0]    div_flags;

        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_div)

                                &&(~stage_busy)&&(set_cond);

        wire    fpu_ce, fpu_error, fpu_busy, fpu_v;

        wire    [31:0]   fpu_result;

        wire    [3:0]    fpu_flags;

        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_fpu)

                                &&(~stage_busy)&&(set_cond);

        //

        //

        //      PIPELINE STAGE #5 :: Write-back

        //              Variable declarations

        //

        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;

        wire    [4:0]    wr_reg_id;

        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;

        wire    w_switch_to_interrupt, w_release_from_interrupt;

        reg     [(AW-1):0]       upc, ipc;

        //

        //      MASTER: clock enable.

        //

        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Calculate stall conditions

        //

        //      These are calculated externally, within the prefetch module.

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Calculate stall conditions

        assign          dcd_ce = ((~dcd_v)||(~dcd_stalled))&&(~clear_pipeline);

        assign          dcd_stalled = (dcd_v)&&(opa_stall);

        //

        //      PIPELINE STAGE #3 :: Read Operands

        //              Calculate stall conditions

        wire    op_lock_stall;

        assign  opa_stall_slp = (

                                // Likewise for B, also includes logic

                                // regarding immediate offset (register must

                                // be in register file if we need to add to

                                // an immediate)

                                (((dcdB_rd)&&(~dcd_zI))

                                        &&((opa_v)&&(opb_R == dcdB)

                                                ||(mem_rdbusy)

                                                ||((div_busy)&&(div_R == dcdB))

                                                ||((fpu_busy)&&(fpu_R == dcdB))

                                                ||((alua_v)&&(alua_R==dcdB))

                                                ||((alub_v)&&(alub_R==dcdB))

                                                ||((alu_busy))

                                        &&(

                                        // 1.

                                        ((~dcd_zI)&&(

                                                ((opb_R == dcdB)&&(opb_wR))

                                                ||((mem_rdbusy)&&(~dcd_pipe))

                                                ))

                                        // 2.

                                        ||((opF_wr)&&(dcdB_cc))

                                        )))

                                // Or if we need to wait on flags to work on the

                                // CC register

                                ||(((~dcdF[3])

                                                ||((dcd_rA)&&(dcdA_cc))

                                                ||((dcd_rB)&&(dcdB_cc)))

                                        &&(opb_v)&&(opb_ccR))

                        );

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Calculate stall conditions

        //

        // 1. Basic stall is if the previous stage is valid and the next is

        //      busy.  

        // 2. Also stall if the prior stage is valid and the master clock enable

        //      is de-selected

        // 3. Stall if someone on the other end is writing the CC register,

        //      since we don't know if it'll put us to sleep or not.

        // 4. Last case: Stall if we would otherwise move a break instruction

        //      through the ALU.  Break instructions are not allowed through

        //      the ALU.

        assign  alu_stall_clp = (~master_ce);

        assign  alu_stall_cls = (~master_ce);

        always @(posedge i_clk)

                stage_busy <= (alu_ce)||(mem_ce)||(fpu_ce)||(div_ce)

                        ||(alu_busy)||(mem_rdbusy)||(fpu_busy)||(div_busy);

        assign  stage_ce = (~div_busy)&&(~alu_busy)&&(~mem_rdbusy)&&(~fpu_busy);

        //

        //

        // Note: if you change the conditions for mem_ce, you must also change

        // alu_pc_v.

        //

        assign  mem_ce = (master_ce)&&(opb_v_mem)&&(~mem_stalled)

                        &&(~clear_pipeline);

        assign  mem_stall_clp = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)

                                        ||(wr_write_pc)||(wr_write_cc)

                                ||((opb_v_mem)&&(

                                        (mem_pipe_stalled)

                                        ||((~opb_pipe)&&(mem_busy))));

        assign  mem_stall_cls = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)

                                        ||(wr_write_pc)||(wr_write_cc)

                                ||((cp_opb_v_mem)&&(

                                        (mem_pipe_stalled)

                                        ||((~cp_opb_pipe)&&(mem_busy))));

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //

        //

        fastcache #(LGICACHE, ADDRESS_WIDTH)

                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),

                                        i_clear_pf_cache,

                                // dcd_pc,

                                ~dcd_stalled,

                                ((dcd_early_branch)&&(~clear_pipeline))

                                        ? dcd_branch_pc:pf_pc,

                                instruction, instruction_pc, pf_v,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

                                pf_illegal);

        assign  instruction_gie = gie;

        //

        // The ifastdec decoder takes two clocks to decode an instruction.

        // Therefore, to determine if a decoded instruction is valid, we

        // need to wait two clocks from pf_v.  Hence, we dump this into

        // a pipeline below.

        //

        initial r_dcdvalid = 2'b00;

        always @(posedge i_clk)

                if ((i_rst)||(clear_pipeline)||(w_clear_icache))

                        r_dcdvalid <= 2'b00;

                else if (dcd_ce)

                        r_dcdvalid <= { r_dcdvalid[0], pf_v };

                else if (opa_ce)

                        r_dcdvalid <= 1'b0;

        assign  dcd_v = r_dcdvalid[1];

        ifastdec #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,

                        IMPLEMENT_FPU)

                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),

                        dcd_ce, dcd_stalled, instruction, instruction_gie,

                        instruction_pc, pf_v, pf_illegal, dcd_phase,

                        dcd_illegal, dcd_pc, dcd_gie,

                        { dcd_Rcc, dcd_Rpc, dcd_iR },

                        { dcd_Acc, dcd_Apc, dcd_iA },

                        { dcd_Bcc, dcd_Bpc, dcd_iB },

                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcdOp,

                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,

                        dcd_wR,dcd_rA, dcd_rB,

                        dcd_early_branch,

                        dcd_branch_pc, dcd_ljmp,

                        dcd_pipe);

        //

        //

        //      PIPELINE STAGE #3 :: Read Operands (Registers)

        //

        //

        reg             opa_pipe;

        initial opa_pipe = 1'b0;

        // To be a pipeable operation, there must be 

        //      two valid adjacent instructions

        //      Both must be memory instructions

        //      Both must be writes, or both must be reads

        //      Both operations must be to the same identical address,

        //              or at least a single (one) increment above that address

        //

        // However ... we need to know this before this clock, hence this is

        // calculated in the instruction decoder.

        always @(posedge i_clk)

                if (!opa_stall)

                begin

                        opa_v <= dcdvalid&&(~opa_stall_slp);

                        opa_stall <= (dcdvalid)&&(opa_stall_slp);

                        opa_pipe <= dcd_pipe;

                        opa_wR <= dcd_wR;

                        { opa_Acc, opa_Apc, opa_iA, opa_rA }

                                <= { dcd_Acc, dcd_Apc, dcd_iA, dcd_rA };

                        { opa_Bcc, opa_Bpc, opa_iB, opa_rB }

                                <= { dcd_Bcc, dcd_Bpc, dcd_iB, dcd_rB };

                        // Register A

                        if (dcd_Apc)

                                opa_vA <= (dcd_iA[4]==dcd_gie) ? dcd_pc

                                                : (dcd_iA)?upc : ipc;

                        else if (dcd_Acc)

                                opa_vA <= (dcd_iA[4])?user_flags_reg

                                                : supervisor_flags_reg;

                        else

                                opa_vA <= regset[dcd_iA];

                        // Register B

                        if (!dcd_rB)

                                opa_vB <= 32'h00;

                        else if (dcd_Bpc)

                                opa_vB <= (dcd_iB[4]==dcd_gie) ? dcd_pc

                                                : (dcd_iB)?upc : ipc;

                        else if (dcd_Bcc)

                                opa_vB <= (dcd_iB[4])?user_flags_reg

                                                : supervisor_flags_reg;

                        else

                                opa_vB <= regset[dcd_iB];

                        // Copy

                        cp_opa_pc   <= dcd_pc;

                        cp_opa_gie  <= dcd_gie;

                        cp_opa_pipe <= dcd_pipe;

                        { cp_opa_Rcc, cp_opa_Rpc, cp_opa_iR }

                                <= { dcd_Rcc, dcd_Rpc, dcd_iR };

                        { cp_opa_Acc, cp_opa_Apc, cp_opa_iA }

                                <= { dcd_Acc, dcd_Apc, dcd_iA };

                        { cp_opa_Bcc, cp_opa_Bpc, cp_opa_iB }

                                <= { dcd_Bcc, dcd_Bpc, dcd_iB };

                end else begin

                        opa_v     <= (~opa_stall_slc);

                        opa_stall <= (opa_stall_slc);

                        opa_pipe  <= cp_opa_pipe;

                        // Register A

                        if (cp_opa_Apc)

                                opa_vA <= (cp_opa_iA[4]==cp_opa_gie) ? cp_opa_pc

                                                : (cp_opa_iA)?upc : ipc;

                        else if (dcd_Acc)

                                opa_vA <= (cp_opa_iA[4])?user_flags_reg

                                                : supervisor_flags_reg;

                        else

                                opa_vA <= regset[cp_opa_iA];

                        // Register B

                        if (!cp_opa_rB)

                                opa_vB <= 32'h00;

                        else if (cp_opa_Bpc)

                                opa_vB <= (cp_opa_iB[4]==cp_opa_gie) ? cp_opa_pc

                                                : (cp_opa_iB)?upc : ipc;

                        else if (cp_opa_Bcc)

                                opa_vB <= (cp_opa_iB[4])?user_flags_reg

                                                : supervisor_flags_reg;

                        else

                                opa_vB <= regset[cp_opa_iB];

                end

        wire    [8:0]    w_cpu_info;

        assign  w_cpu_info = {

`ifdef  OPT_ILLEGAL_INSTRUCTION

        1'b1,

`else

        1'b0,

`endif

        1'b1,

`ifdef  OPT_DIVIDE

        1'b1,

`else

        1'b0,

`endif