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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: lloled.v
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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`define OLED_IDLE 3'h0
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`define OLED_START 3'h1
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`define OLED_BITS 3'h2
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`define OLED_READY 3'h3
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`define OLED_STOP 3'h4
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`define OLED_STOP_B 3'h5
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// Modes
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`define OLED_MOD_SPI 2'b00
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`define OLED_MOD_QOUT 2'b10
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`define OLED_MOD_QIN 2'b11
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module lloled(i_clk,
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// Module interface
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i_wr, i_dbit, i_word, i_len, o_busy,
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// OLED interface
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o_sck, o_cs_n, o_mosi, o_dbit);
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parameter CTRBITS = 8;
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input i_clk;
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// Chip interface
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// Can send info
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// i_wr = 1,
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// i_word = { 1'b0, 32'info to send },
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// i_len = # of bytes in word-1
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input i_wr, i_dbit;
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input [31:0] i_word;
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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output reg o_busy;
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// Interface with the OLED lines
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output reg o_sck, o_cs_n, o_mosi, o_dbit;
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// Timing:
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//
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// Tick Clk BSY/WR CS_n BIT/MO STATE
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// 0 1 0/0 1 -
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// 1 1 0/1 1 -
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// 2 1 1/0 0 - OLED_START
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// 3 0 1/0 0 - OLED_START
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// 4 0 1/0 0 0 OLED_BITS
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// 5 1 1/0 0 0 OLED_BITS
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// 6 0 1/0 0 1 OLED_BITS
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// 7 1 1/0 0 1 OLED_BITS
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// 8 0 1/0 0 2 OLED_BITS
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// 9 1 1/0 0 2 OLED_BITS
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// 10 0 1/0 0 3 OLED_BITS
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// 11 1 1/0 0 3 OLED_BITS
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// 12 0 1/0 0 4 OLED_BITS
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// 13 1 1/0 0 4 OLED_BITS
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// 14 0 1/0 0 5 OLED_BITS
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// 15 1 1/0 0 5 OLED_BITS
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// 16 0 1/0 0 6 OLED_BITS
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// 17 1 1/1 0 6 OLED_BITS
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// 18 0 1/1 0 7 OLED_READY
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// 19 1 0/1 0 7 OLED_READY
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// 20 0 1/0/V 0 8 OLED_BITS
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// 21 1 1/0 0 8 OLED_BITS
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// 22 0 1/0 0 9 OLED_BITS
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// 23 1 1/0 0 9 OLED_BITS
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// 24 0 1/0 0 10 OLED_BITS
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// 25 1 1/0 0 10 OLED_BITS
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// 26 0 1/0 0 11 OLED_BITS
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// 27 1 1/0 0 11 OLED_BITS
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// 28 0 1/0 0 12 OLED_BITS
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// 29 1 1/0 0 12 OLED_BITS
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// 30 0 1/0 0 13 OLED_BITS
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// 31 1 1/0 0 13 OLED_BITS
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// 32 0 1/0 0 14 OLED_BITS
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// 33 1 1/0 0 14 OLED_BITS
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// 34 0 1/0 0 15 OLED_READY
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// 35 1 1/0 0 15 OLED_READY
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// 36 1 1/0/V 0 - OLED_STOP
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// 37 1 1/0 0 - OLED_STOPB
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// 38 1 1/0 1 - OLED_IDLE
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// 39 1 0/0 1 -
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reg [5:0] spi_len;
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reg [31:0] r_word;
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reg [2:0] state;
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initial state = `OLED_IDLE;
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initial o_sck = 1'b1;
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initial o_cs_n = 1'b1;
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initial o_mosi = 1'b0;
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initial o_busy = 1'b0;
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reg [(CTRBITS-1):0] counter;
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reg last_counter, pre_last_counter;
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always @(posedge i_clk) // Clock cycle time > 150 ns > 300 ticks
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last_counter <= (counter == {{(CTRBITS-1){1'b0}},1'b1});
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always @(posedge i_clk)
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pre_last_counter <= (counter == {{(CTRBITS-2){1'b0}},2'b10});
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always @(posedge i_clk)
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if (state == `OLED_IDLE)
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counter <= {(CTRBITS){1'b1}};
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else
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counter <= counter + {(CTRBITS){1'b1}};
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always @(posedge i_clk)
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if ((state == `OLED_IDLE)&&(o_sck))
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begin
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o_cs_n <= 1'b1;
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o_busy <= 1'b0;
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r_word <= i_word;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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o_sck <= 1'b1;
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o_dbit <= i_dbit;
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if (i_wr)
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begin
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state <= `OLED_START;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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end
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end else if (state == `OLED_START)
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begin // We come in here with sck high, stay here 'til sck is low
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o_sck <= 1'b0;
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if (o_sck == 1'b0)
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begin
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state <= `OLED_BITS;
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spi_len<= spi_len - 6'h1;
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r_word <= { r_word[30:0], 1'b0 };
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end
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_mosi <= r_word[31];
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end else if (~last_counter)
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begin
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o_busy <= (pre_last_counter)&&(o_sck)
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&&((state != `OLED_READY)||(~i_wr));
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end else if (~o_sck)
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begin
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o_sck <= 1'b1;
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o_busy <= 1'b1;
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end else if (state == `OLED_BITS)
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begin
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// Should enter into here with at least a spi_len
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// of one, perhaps more
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o_sck <= 1'b0;
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o_busy <= 1'b1;
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o_mosi <= r_word[31];
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r_word <= { r_word[30:0], 1'b0 };
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spi_len <= spi_len - 6'h1;
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if (spi_len == 6'h1)
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state <= `OLED_READY;
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end else if (state == `OLED_READY)
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begin
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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// This is the state on the last clock (both low and
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// high clocks) of the data. Data is valid during
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// this state. Here we chose to either STOP or
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// continue and transmit more.
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o_sck <= 1'b0;
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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state <= `OLED_BITS;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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// Set up the first bits on the bus
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o_mosi <= i_word[31];
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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// Read a bit upon any transition
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end else begin
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o_sck <= 1'b1;
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state <= `OLED_STOP;
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o_busy <= 1'b1;
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end
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end else if (state == `OLED_STOP)
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begin
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o_sck <= 1'b1; // Stop the clock
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o_busy <= 1'b1; // Still busy till port is clear
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state <= `OLED_STOP_B;
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end else // if (state == `OLED_STOP_B)
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begin
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o_cs_n <= 1'b1; // Deselect CS
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o_sck <= 1'b1;
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// Do I need this????
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// spi_len <= 3; // Minimum CS high time before next cmd
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state <= `OLED_IDLE;
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o_mosi <= 1'b1;
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o_busy <= 1'b1;
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end
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/*
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*/
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endmodule
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