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[/] [openarty/] [trunk/] [rtl/] [rxuart.v] - Blame information for rev 50

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////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    rxuart.v
4
//
5 50 dgisselq
// Project:     wbuart32, a full featured UART with simulator
6 3 dgisselq
//
7
// Purpose:     Receive and decode inputs from a single UART line.
8
//
9
//
10
//      To interface with this module, connect it to your system clock,
11
//      pass it the 32 bit setup register (defined below) and the UART
12
//      input.  When data becomes available, the o_wr line will be asserted
13
//      for one clock cycle.  On parity or frame errors, the o_parity_err
14
//      or o_frame_err lines will be asserted.  Likewise, on a break 
15
//      condition, o_break will be asserted.  These lines are self clearing.
16
//
17
//      There is a synchronous reset line, logic high.
18
//
19
//      Now for the setup register.  The register is 32 bits, so that this
20
//      UART may be set up over a 32-bit bus.
21
//
22 50 dgisselq
//      i_setup[30]     True if we are not using hardware flow control.  This bit
23
//              is ignored within this module, as any receive hardware flow
24
//              control will need to be implemented elsewhere.
25
//
26 3 dgisselq
//      i_setup[29:28]  Indicates the number of data bits per word.  This will
27 50 dgisselq
//              either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
28
//              for a six bit word, or 2'b11 for a five bit word.
29 3 dgisselq
//
30
//      i_setup[27]     Indicates whether or not to use one or two stop bits.
31
//              Set this to one to expect two stop bits, zero for one.
32
//
33
//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
34
//              to 1'b1 to include parity.
35
//
36
//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
37
//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
38
//              parity to be set based upon data.  (Both assume the parity
39
//              enable value is set.)
40
//
41
//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
42
//              in the case of a fixed parity bit, this bit indicates whether
43
//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
44
//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
45
//              selects odd.
46
//
47
//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
48
//              So, for example, if you have a 200 MHz clock and wish to
49
//              run your UART at 9600 baud, you would take 200 MHz and divide
50
//              by 9600 to set this value to 24'd20834.  Likewise if you wished
51
//              to run this serial port at 115200 baud from a 200 MHz clock,
52
//              you would set the value to 24'd1736
53
//
54
//      Thus, to set the UART for the common setting of an 8-bit word, 
55
//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
56
//      would want to set the setup value to:
57
//
58
//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
59
//      32'h005161              // For 9600 baud, 8 bit, no parity
60
//      
61
//
62
//
63
// Creator:     Dan Gisselquist, Ph.D.
64
//              Gisselquist Technology, LLC
65
//
66
////////////////////////////////////////////////////////////////////////////////
67
//
68
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
69
//
70
// This program is free software (firmware): you can redistribute it and/or
71
// modify it under the terms of  the GNU General Public License as published
72
// by the Free Software Foundation, either version 3 of the License, or (at
73
// your option) any later version.
74
//
75
// This program is distributed in the hope that it will be useful, but WITHOUT
76
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
77
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
78
// for more details.
79
//
80
// You should have received a copy of the GNU General Public License along
81 50 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
82 3 dgisselq
// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
84
//
85
// License:     GPL, v3, as defined and found on www.gnu.org,
86
//              http://www.gnu.org/licenses/gpl.html
87
//
88
//
89
////////////////////////////////////////////////////////////////////////////////
90
//
91
//
92
// States: (@ baud counter == 0)
93
//      0        First bit arrives
94
//      ..7     Bits arrive
95
//      8       Stop bit (x1)
96
//      9       Stop bit (x2)
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//      c       break condition
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//      d       Waiting for the channel to go high
99
//      e       Waiting for the reset to complete
100
//      f       Idle state
101
`define RXU_BIT_ZERO            4'h0
102
`define RXU_BIT_ONE             4'h1
103
`define RXU_BIT_TWO             4'h2
104
`define RXU_BIT_THREE           4'h3
105
`define RXU_BIT_FOUR            4'h4
106
`define RXU_BIT_FIVE            4'h5
107
`define RXU_BIT_SIX             4'h6
108
`define RXU_BIT_SEVEN           4'h7
109
`define RXU_PARITY              4'h8
110
`define RXU_STOP                4'h9
111
`define RXU_SECOND_STOP         4'ha
112
// Unused 4'hb
113
// Unused 4'hc
114
`define RXU_BREAK               4'hd
115
`define RXU_RESET_IDLE          4'he
116
`define RXU_IDLE                4'hf
117
 
118 50 dgisselq
module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,
119 3 dgisselq
                        o_parity_err, o_frame_err, o_ck_uart);
120 50 dgisselq
        parameter [30:0] INITIAL_SETUP = 31'd868;
121 3 dgisselq
        // 8 data bits, no parity, (at least 1) stop bit
122
        input                   i_clk, i_reset;
123 50 dgisselq
        input           [30:0]   i_setup;
124
        input                   i_uart_rx;
125 3 dgisselq
        output  reg             o_wr;
126
        output  reg     [7:0]    o_data;
127
        output  reg             o_break;
128
        output  reg             o_parity_err, o_frame_err;
129
        output  wire            o_ck_uart;
130
 
131
 
132
        wire    [27:0]   clocks_per_baud, break_condition, half_baud;
133
        wire    [1:0]    data_bits;
134
        wire            use_parity, parity_even, dblstop, fixd_parity;
135
        reg     [29:0]   r_setup;
136 50 dgisselq
        reg     [3:0]    state;
137
 
138 3 dgisselq
        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
139 50 dgisselq
        // assign hw_flow_control = !r_setup[30];
140 3 dgisselq
        assign  data_bits   = r_setup[29:28];
141
        assign  dblstop     = r_setup[27];
142
        assign  use_parity  = r_setup[26];
143
        assign  fixd_parity = r_setup[25];
144
        assign  parity_even = r_setup[24];
145
        assign  break_condition = { r_setup[23:0], 4'h0 };
146 50 dgisselq
        assign  half_baud = { 5'h00, r_setup[23:1] }-28'h1;
147
        reg     [27:0]   baud_counter;
148
        reg             zero_baud_counter;
149 3 dgisselq
 
150 50 dgisselq
 
151
        // Since this is an asynchronous receiver, we need to register our
152
        // input a couple of clocks over to avoid any problems with 
153
        // metastability.  We do that here, and then ignore all but the
154
        // ck_uart wire.
155 3 dgisselq
        reg     q_uart, qq_uart, ck_uart;
156
        initial q_uart  = 1'b0;
157
        initial qq_uart = 1'b0;
158
        initial ck_uart = 1'b0;
159
        always @(posedge i_clk)
160
        begin
161 50 dgisselq
                q_uart <= i_uart_rx;
162 3 dgisselq
                qq_uart <= q_uart;
163
                ck_uart <= qq_uart;
164
        end
165 50 dgisselq
 
166
        // In case anyone else wants this clocked, stabilized value, we
167
        // offer it on our output.
168 3 dgisselq
        assign  o_ck_uart = ck_uart;
169
 
170 50 dgisselq
        // Keep track of the number of clocks since the last change.
171
        //
172
        // This is used to determine if we are in either a break or an idle
173
        // condition, as discussed further below.
174 3 dgisselq
        reg     [27:0]   chg_counter;
175
        initial chg_counter = 28'h00;
176
        always @(posedge i_clk)
177
                if (i_reset)
178
                        chg_counter <= 28'h00;
179
                else if (qq_uart != ck_uart)
180
                        chg_counter <= 28'h00;
181
                else if (chg_counter < break_condition)
182
                        chg_counter <= chg_counter + 1;
183
 
184 50 dgisselq
        // Are we in a break condition?
185
        //
186
        // A break condition exists if the line is held low for longer than
187
        // a data word.  Hence, we keep track of when the last change occurred.
188
        // If it was more than break_condition clocks ago, and the current input
189
        // value is a 0, then we're in a break--and nothing can be read until
190
        // the line idles again.
191 3 dgisselq
        initial o_break    = 1'b0;
192
        always @(posedge i_clk)
193
                o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0;
194 50 dgisselq
 
195
        // Are we between characters?
196
        //
197
        // The opposite of a break condition is where the line is held high
198
        // for more clocks than would be in a character.  When this happens,
199
        // we know we have synchronization--otherwise, we might be sampling
200
        // from within a data word.
201
        //
202
        // This logic is used later to hold the RXUART in a reset condition
203
        // until we know we are between data words.  At that point, we should
204
        // be able to hold on to our synchronization.
205
        reg     line_synch;
206
        initial line_synch = 1'b0;
207 3 dgisselq
        always @(posedge i_clk)
208
                line_synch <= ((chg_counter >= break_condition)&&(ck_uart));
209
 
210 50 dgisselq
        // Are we in the middle of a baud iterval?  Specifically, are we
211
        // in the middle of a start bit?  Set this to high if so.  We'll use
212
        // this within our state machine to transition out of the IDLE
213
        // state.
214
        reg     half_baud_time;
215
        initial half_baud_time = 0;
216
        always @(posedge i_clk)
217
                half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud);
218
 
219
 
220
        // Allow our controlling processor to change our setup at any time
221
        // outside of receiving/processing a character.
222
        initial r_setup     = INITIAL_SETUP[29:0];
223
        always @(posedge i_clk)
224
                if (state >= `RXU_RESET_IDLE)
225
                        r_setup <= i_setup[29:0];
226
 
227
 
228
        // Our monster state machine.  YIKES!
229
        //
230
        // Yeah, this may be more complicated than it needs to be.  The basic
231
        // progression is:
232
        //      RESET -> RESET_IDLE -> (when line is idle) -> IDLE
233
        //      IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} -> 
234
        //              (optional) PARITY -> STOP -> (optional) SECOND_STOP
235
        //              -> IDLE
236
        //      ANY -> (on break) BREAK -> IDLE
237
        //
238
        // There are 16 states, although all are not used.  These are listed
239
        // at the top of this file.
240
        //
241
        //      Logic inputs (12):      (I've tried to minimize this number)
242
        //              state   (4)
243
        //              i_reset
244
        //              line_synch
245
        //              o_break
246
        //              ckuart
247
        //              half_baud_time
248
        //              zero_baud_counter
249
        //              use_parity
250
        //              dblstop
251
        //      Logic outputs (4):
252
        //              state
253
        //
254 3 dgisselq
        initial state = `RXU_RESET_IDLE;
255
        always @(posedge i_clk)
256
        begin
257
                if (i_reset)
258
                        state <= `RXU_RESET_IDLE;
259 50 dgisselq
                else if (state == `RXU_RESET_IDLE)
260 3 dgisselq
                begin
261
                        if (line_synch)
262
                                // Goto idle state from a reset
263
                                state <= `RXU_IDLE;
264
                        else // Otherwise, stay in this condition 'til reset
265
                                state <= `RXU_RESET_IDLE;
266
                end else if (o_break)
267
                begin // We are in a break condition
268
                        state <= `RXU_BREAK;
269
                end else if (state == `RXU_BREAK)
270
                begin // Goto idle state following return ck_uart going high
271
                        if (ck_uart)
272
                                state <= `RXU_IDLE;
273
                        else
274
                                state <= `RXU_BREAK;
275
                end else if (state == `RXU_IDLE)
276
                begin // Idle state, independent of baud counter
277
                        if ((~ck_uart)&&(half_baud_time))
278
                        begin
279
                                // We are in the center of a valid start bit
280
                                case (data_bits)
281
                                2'b00: state <= `RXU_BIT_ZERO;
282
                                2'b01: state <= `RXU_BIT_ONE;
283
                                2'b10: state <= `RXU_BIT_TWO;
284
                                2'b11: state <= `RXU_BIT_THREE;
285
                                endcase
286
                        end else // Otherwise, just stay here in idle
287
                                state <= `RXU_IDLE;
288
                end else if (zero_baud_counter)
289
                begin
290
                        if (state < `RXU_BIT_SEVEN)
291
                                // Data arrives least significant bit first.
292
                                // By the time this is clocked in, it's what
293
                                // you'll have.
294
                                state <= state + 1;
295 50 dgisselq
                        else if (state == `RXU_BIT_SEVEN)
296 3 dgisselq
                                state <= (use_parity) ? `RXU_PARITY:`RXU_STOP;
297 50 dgisselq
                        else if (state == `RXU_PARITY)
298 3 dgisselq
                                state <= `RXU_STOP;
299 50 dgisselq
                        else if (state == `RXU_STOP)
300 3 dgisselq
                        begin // Stop (or parity) bit(s)
301 50 dgisselq
                                if (~ck_uart) // On frame error, wait 4 ch idle
302 3 dgisselq
                                        state <= `RXU_RESET_IDLE;
303
                                else if (dblstop)
304
                                        state <= `RXU_SECOND_STOP;
305
                                else
306
                                        state <= `RXU_IDLE;
307
                        end else // state must equal RX_SECOND_STOP
308
                        begin
309 50 dgisselq
                                if (~ck_uart) // On frame error, wait 4 ch idle
310 3 dgisselq
                                        state <= `RXU_RESET_IDLE;
311 50 dgisselq
                                else
312 3 dgisselq
                                        state <= `RXU_IDLE;
313
                        end
314
                end
315
        end
316
 
317 50 dgisselq
        // Data bit capture logic.
318
        //
319
        // This is drastically simplified from the state machine above, based
320
        // upon: 1) it doesn't matter what it is until the end of a captured
321
        // byte, and 2) the data register will flush itself of any invalid
322
        // data in all other cases.  Hence, let's keep it real simple.
323
        // The only trick, though, is that if we have parity, then the data
324
        // register needs to be held through that state without getting
325
        // updated.
326
        reg     [7:0]    data_reg;
327
        always @(posedge i_clk)
328
                if ((zero_baud_counter)&&(state != `RXU_PARITY))
329
                        data_reg <= { ck_uart, data_reg[7:1] };
330
 
331
        // Parity calculation logic
332
        //
333
        // As with the data capture logic, all that must be known about this
334
        // bit is that it is the exclusive-OR of all bits prior.  The first
335
        // of those will follow idle, so we set ourselves to zero on idle.
336
        // Then, as we walk through the states of a bit, all will adjust this
337
        // value up until the parity bit, where the value will be read.  Setting
338
        // it then or after will be irrelevant, so ... this should be good
339
        // and simplified.  Note--we don't need to adjust this on reset either,
340
        // since the reset state will lead to the idle state where we'll be
341
        // reset before any transmission takes place.
342
        reg             calc_parity;
343
        always @(posedge i_clk)
344
                if (state == `RXU_IDLE)
345
                        calc_parity <= 0;
346
                else if (zero_baud_counter)
347
                        calc_parity <= calc_parity ^ ck_uart;
348
 
349
        // Parity error logic
350
        //
351
        // Set during the parity bit interval, read during the last stop bit
352
        // interval, cleared on BREAK, RESET_IDLE, or IDLE states.
353
        initial o_parity_err = 1'b0;
354
        always @(posedge i_clk)
355
                if ((zero_baud_counter)&&(state == `RXU_PARITY))
356
                begin
357
                        if (fixd_parity)
358
                                // Fixed parity bit--independent of any dat
359
                                // value.
360
                                o_parity_err <= (ck_uart ^ parity_even);
361
                        else if (parity_even)
362
                                // Parity even: The XOR of all bits including
363
                                // the parity bit must be zero.
364
                                o_parity_err <= (calc_parity != ck_uart);
365
                        else
366
                                // Parity odd: the parity bit must equal the
367
                                // XOR of all the data bits.
368
                                o_parity_err <= (calc_parity == ck_uart);
369
                end else if (state >= `RXU_BREAK)
370
                        o_parity_err <= 1'b0;
371
 
372
        // Frame error determination
373
        //
374
        // For the purpose of this controller, a frame error is defined as a
375
        // stop bit (or second stop bit, if so enabled) not being high midway
376
        // through the stop baud interval.   The frame error value is
377
        // immediately read, so we can clear it under all other circumstances.
378
        // Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and
379
        // most importantly in RXU_IDLE.
380
        initial o_frame_err  = 1'b0;
381
        always @(posedge i_clk)
382
                if ((zero_baud_counter)&&((state == `RXU_STOP)
383
                                                ||(state == `RXU_SECOND_STOP)))
384
                        o_frame_err <= (o_frame_err)||(~ck_uart);
385
                else if ((zero_baud_counter)||(state >= `RXU_BREAK))
386
                        o_frame_err <= 1'b0;
387
 
388
        // Our data bit logic doesn't need nearly the complexity of all that
389
        // work above.  Indeed, we only need to know if we are at the end of
390
        // a stop bit, in which case we copy the data_reg into our output
391
        // data register, o_data.
392
        //
393
        // We would also set o_wr to be true when this is the case, but ... we
394
        // won't know if there is a frame error on the second stop bit for 
395
        // another baud interval yet.  So, instead, we set up the logic so that
396
        // we know on the next zero baud counter that we can write out.  That's
397
        // the purpose of pre_wr.
398
        initial o_data = 8'h00;
399
        reg     pre_wr;
400
        initial pre_wr = 1'b0;
401
        always @(posedge i_clk)
402
                if (i_reset)
403
                begin
404
                        pre_wr <= 1'b0;
405
                        o_data <= 8'h00;
406
                end else if ((zero_baud_counter)&&(state == `RXU_STOP))
407
                begin
408
                        pre_wr <= 1'b1;
409
                        case (data_bits)
410
                        2'b00: o_data <= data_reg;
411
                        2'b01: o_data <= { 1'b0, data_reg[7:1] };
412
                        2'b10: o_data <= { 2'b0, data_reg[7:2] };
413
                        2'b11: o_data <= { 3'b0, data_reg[7:3] };
414
                        endcase
415
                end else if ((zero_baud_counter)||(state == `RXU_IDLE))
416
                        pre_wr <= 1'b0;
417
 
418
        // Create an output strobe, true for one clock only, once we know
419
        // all we need to know.  o_data will be set on the last baud interval,
420
        // o_parity_err on the last parity baud interval (if it existed,
421
        // cleared otherwise, so ... we should be good to go here.)
422
        initial o_wr   = 1'b0;
423
        always @(posedge i_clk)
424
                if ((zero_baud_counter)||(state == `RXU_IDLE))
425
                        o_wr <= (pre_wr)&&(!i_reset);
426
                else
427
                        o_wr <= 1'b0;
428
 
429
        // The baud counter
430
        //
431
        // This is used as a "clock divider" if you will, but the clock needs
432
        // to be reset before any byte can be decoded.  In all other respects,
433
        // we set ourselves up for clocks_per_baud counts between baud
434
        // intervals.
435
        always @(posedge i_clk)
436
                if (i_reset)
437
                        baud_counter <= clocks_per_baud-28'h01;
438
                else if (zero_baud_counter)
439
                        baud_counter <= clocks_per_baud-28'h01;
440
                else case(state)
441
                        `RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01;
442
                        `RXU_BREAK:     baud_counter <= clocks_per_baud-28'h01;
443
                        `RXU_IDLE:      baud_counter <= clocks_per_baud-28'h01;
444
                        default:        baud_counter <= baud_counter-28'h01;
445
                endcase
446
 
447
        // zero_baud_counter
448
        //
449
        // Rather than testing whether or not (baud_counter == 0) within our
450
        // (already too complicated) state transition tables, we use
451
        // zero_baud_counter to pre-charge that test on the clock
452
        // before--cleaning up some otherwise difficult timing dependencies.
453 3 dgisselq
        initial zero_baud_counter = 1'b0;
454
        always @(posedge i_clk)
455 50 dgisselq
                if (state == `RXU_IDLE)
456
                        zero_baud_counter <= 1'b0;
457
                else
458 3 dgisselq
                zero_baud_counter <= (baud_counter == 28'h01);
459
 
460
 
461
endmodule
462
 
463
 

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