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[/] [openarty/] [trunk/] [rtl/] [txuart.v] - Blame information for rev 50

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1 3 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
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// Filename:    txuart.v
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//
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// Project:     wbuart32, a full featured UART with simulator
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//
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// Purpose:     Transmit outputs over a single UART line.
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//
9
//      To interface with this module, connect it to your system clock,
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//      pass it the 32 bit setup register (defined below) and the byte
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//      of data you wish to transmit.  Strobe the i_wr line high for one
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//      clock cycle, and your data will be off.  Wait until the 'o_busy'
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//      line is low before strobing the i_wr line again--this implementation
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//      has NO BUFFER, so strobing i_wr while the core is busy will just
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//      cause your data to be lost.  The output will be placed on the o_txuart
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//      output line.  If you wish to set/send a break condition, assert the
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//      i_break line otherwise leave it low.
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//
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//      There is a synchronous reset line, logic high.
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//
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//      Now for the setup register.  The register is 32 bits, so that this
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//      UART may be set up over a 32-bit bus.
23
//
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//      i_setup[30]     Set this to zero to use hardware flow control, and to
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//              one to ignore hardware flow control.  Only works if the hardware
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//              flow control has been properly wired.
27
//
28
//              If you don't want hardware flow control, fix the i_rts bit to
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//              1'b1, and let the synthesys tools optimize out the logic.
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//
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//      i_setup[29:28]  Indicates the number of data bits per word.  This will
32 50 dgisselq
//              either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10
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//              for a six bit word, or 2'b11 for a five bit word.
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//
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//      i_setup[27]     Indicates whether or not to use one or two stop bits.
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//              Set this to one to expect two stop bits, zero for one.
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//
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//      i_setup[26]     Indicates whether or not a parity bit exists.  Set this
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//              to 1'b1 to include parity.
40
//
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//      i_setup[25]     Indicates whether or not the parity bit is fixed.  Set
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//              to 1'b1 to include a fixed bit of parity, 1'b0 to allow the
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//              parity to be set based upon data.  (Both assume the parity
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//              enable value is set.)
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//
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//      i_setup[24]     This bit is ignored if parity is not used.  Otherwise,
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//              in the case of a fixed parity bit, this bit indicates whether
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//              mark (1'b1) or space (1'b0) parity is used.  Likewise if the
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//              parity is not fixed, a 1'b1 selects even parity, and 1'b0
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//              selects odd.
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//
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//      i_setup[23:0]   Indicates the speed of the UART in terms of clocks.
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//              So, for example, if you have a 200 MHz clock and wish to
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//              run your UART at 9600 baud, you would take 200 MHz and divide
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//              by 9600 to set this value to 24'd20834.  Likewise if you wished
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//              to run this serial port at 115200 baud from a 200 MHz clock,
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//              you would set the value to 24'd1736
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//
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//      Thus, to set the UART for the common setting of an 8-bit word, 
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//      one stop bit, no parity, and 115200 baud over a 200 MHz clock, you
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//      would want to set the setup value to:
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//
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//      32'h0006c8              // For 115,200 baud, 8 bit, no parity
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//      32'h005161              // For 9600 baud, 8 bit, no parity
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//      
66
//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
72 50 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define TXU_BIT_ZERO    4'h0
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`define TXU_BIT_ONE     4'h1
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`define TXU_BIT_TWO     4'h2
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`define TXU_BIT_THREE   4'h3
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`define TXU_BIT_FOUR    4'h4
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`define TXU_BIT_FIVE    4'h5
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`define TXU_BIT_SIX     4'h6
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`define TXU_BIT_SEVEN   4'h7
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`define TXU_PARITY      4'h8    // Constant 1
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`define TXU_STOP        4'h9    // Constant 1
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`define TXU_SECOND_STOP 4'ha
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// 4'hb // Unused
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// 4'hc // Unused
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// `define      TXU_START       4'hd    // An unused state
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`define TXU_BREAK       4'he
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`define TXU_IDLE        4'hf
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//
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//
114 50 dgisselq
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
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                i_cts_n, o_uart_tx, o_busy);
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        parameter       [30:0]   INITIAL_SETUP = 31'd868;
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        input                   i_clk, i_reset;
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        input           [30:0]   i_setup;
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        input                   i_break;
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        input                   i_wr;
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        input           [7:0]    i_data;
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        // Hardware flow control Ready-To-Send bit.  Set this to one to use
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        // the core without flow control.  (A more appropriate name would be
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        // the Ready-To-Receive bit ...)
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        input                   i_cts_n;
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        // And the UART input line itself
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        output  reg             o_uart_tx;
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        // A line to tell others when we are ready to accept data.  If
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        // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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        // for transmission.
131 3 dgisselq
        output  wire            o_busy;
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        wire    [27:0]   clocks_per_baud, break_condition;
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        wire    [1:0]    data_bits;
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        wire            use_parity, parity_even, dblstop, fixd_parity,
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                        fixdp_value, hw_flow_control;
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        reg     [30:0]   r_setup;
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        assign  clocks_per_baud = { 4'h0, r_setup[23:0] };
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        assign  break_condition = { r_setup[23:0], 4'h0 };
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        assign  hw_flow_control = !r_setup[30];
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        assign  data_bits       =  r_setup[29:28];
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        assign  dblstop         =  r_setup[27];
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        assign  use_parity      =  r_setup[26];
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        assign  fixd_parity     =  r_setup[25];
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        assign  parity_even     =  r_setup[24];
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        assign  fixdp_value     =  r_setup[24];
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        reg     [27:0]   baud_counter;
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        reg     [3:0]    state;
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        reg     [7:0]    lcl_data;
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        reg             calc_parity, r_busy, zero_baud_counter;
152
 
153 50 dgisselq
 
154
        // First step ... handle any hardware flow control, if so enabled.
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        //
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        // Clock in the flow control data, two clocks to avoid metastability
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        // Default to using hardware flow control (uart_setup[30]==0 to use it).
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        // Set this high order bit off if you do not wish to use it.
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        reg     q_cts_n, qq_cts_n, ck_cts;
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        // While we might wish to give initial values to q_rts and ck_cts,
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        // 1) it's not required since the transmitter starts in a long wait
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        // state, and 2) doing so will prevent the synthesizer from optimizing
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        // this pin in the case it is hard set to 1'b1 external to this
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        // peripheral.
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        //
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        // initial      q_cts_n  = 1'b1;
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        // initial      qq_cts_n = 1'b1;
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        // initial      ck_cts   = 1'b0;
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        always  @(posedge i_clk)
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                q_cts_n <= i_cts_n;
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        always  @(posedge i_clk)
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                qq_cts_n <= q_cts_n;
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        always  @(posedge i_clk)
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                ck_cts <= (!qq_cts_n)||(!hw_flow_control);
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        initial o_uart_tx = 1'b1;
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        initial r_busy = 1'b1;
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        initial state  = `TXU_IDLE;
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        initial lcl_data= 8'h0;
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        initial calc_parity = 1'b0;
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        // initial      baud_counter = clocks_per_baud;//ILLEGAL--not constant
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        always @(posedge i_clk)
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        begin
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                if (i_reset)
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                begin
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                        r_busy <= 1'b1;
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                        state <= `TXU_IDLE;
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                end else if (i_break)
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                begin
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                        state <= `TXU_BREAK;
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                        r_busy <= 1'b1;
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                end else if (!zero_baud_counter)
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                begin // r_busy needs to be set coming into here
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                        r_busy <= 1'b1;
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                end else if (state == `TXU_BREAK)
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                begin
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                        state <= `TXU_IDLE;
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                        r_busy <= 1'b1;
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                end else if (state == `TXU_IDLE)        // STATE_IDLE
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                begin
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                        if ((i_wr)&&(!r_busy))
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                        begin   // Immediately start us off with a start bit
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                                r_busy <= 1'b1;
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                                case(data_bits)
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                                2'b00: state <= `TXU_BIT_ZERO;
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                                2'b01: state <= `TXU_BIT_ONE;
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                                2'b10: state <= `TXU_BIT_TWO;
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                                2'b11: state <= `TXU_BIT_THREE;
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                                endcase
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                        end else begin // Stay in idle
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                                r_busy <= !ck_cts;
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                        end
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                end else begin
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                        // One clock tick in each of these states ...
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                        // baud_counter <= clocks_per_baud - 28'h01;
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                        r_busy <= 1'b1;
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                        if (state[3] == 0) // First 8 bits
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                        begin
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                                if (state == `TXU_BIT_SEVEN)
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                                        state <= (use_parity)?`TXU_PARITY:`TXU_STOP;
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                                else
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                                        state <= state + 1;
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                        end else if (state == `TXU_PARITY)
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                        begin
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                                state <= `TXU_STOP;
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                        end else if (state == `TXU_STOP)
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                        begin // two stop bit(s)
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                                if (dblstop)
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                                        state <= `TXU_SECOND_STOP;
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                                else
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                                        state <= `TXU_IDLE;
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                        end else // `TXU_SECOND_STOP and default:
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                        begin
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                                state <= `TXU_IDLE; // Go back to idle
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                                // Still r_busy, since we need to wait
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                                // for the baud clock to finish counting
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                                // out this last bit.
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                        end
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                end
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        end
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242 50 dgisselq
        // o_busy
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        //
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        // This is a wire, designed to be true is we are ever busy above.
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        // originally, this was going to be true if we were ever not in the
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        // idle state.  The logic has since become more complex, hence we have
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        // a register dedicated to this and just copy out that registers value.
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        assign  o_busy = (r_busy);
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        // r_setup
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        //
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        // Our setup register.  Accept changes between any pair of transmitted
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        // words.  The register itself has many fields to it.  These are
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        // broken out up top, and indicate what 1) our baud rate is, 2) our
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        // number of stop bits, 3) what type of parity we are using, and 4)
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        // the size of our data word.
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        initial r_setup = INITIAL_SETUP;
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        always @(posedge i_clk)
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                if (state == `TXU_IDLE)
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                        r_setup <= i_setup;
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        // lcl_data
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        //
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        // This is our working copy of the i_data register which we use
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        // when transmitting.  It is only of interest during transmit, and is
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        // allowed to be whatever at any other time.  Hence, if r_busy isn't
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        // true, we can always set it.  On the one clock where r_busy isn't
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        // true and i_wr is, we set it and r_busy is true thereafter.
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        // Then, on any zero_baud_counter (i.e. change between baud intervals)
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        // we simple logically shift the register right to grab the next bit.
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        always @(posedge i_clk)
273
                if (!r_busy)
274
                        lcl_data <= i_data;
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                else if (zero_baud_counter)
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                        lcl_data <= { 1'b0, lcl_data[7:1] };
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278
        // o_uart_tx
279
        //
280
        // This is the final result/output desired of this core.  It's all
281
        // centered about o_uart_tx.  This is what finally needs to follow
282
        // the UART protocol.
283
        //
284
        // Ok, that said, our rules are:
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        //      1'b0 on any break condition
286
        //      1'b0 on a start bit (IDLE, write, and not busy)
287
        //      lcl_data[0] during any data transfer, but only at the baud
288
        //              change
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        //      PARITY -- During the parity bit.  This depends upon whether or
290
        //              not the parity bit is fixed, then what it's fixed to,
291
        //              or changing, and hence what it's calculated value is.
292
        //      1'b1 at all other times (stop bits, idle, etc)
293
        always @(posedge i_clk)
294
                if (i_reset)
295
                        o_uart_tx <= 1'b1;
296
                else if ((i_break)||((i_wr)&&(!r_busy)))
297
                        o_uart_tx <= 1'b0;
298
                else if (zero_baud_counter)
299
                        casez(state)
300
                        4'b0???:        o_uart_tx <= lcl_data[0];
301
                        `TXU_PARITY:    o_uart_tx <= calc_parity;
302
                        default:        o_uart_tx <= 1'b1;
303
                        endcase
304
 
305
 
306
        // calc_parity
307
        //
308
        // Calculate the parity to be placed into the parity bit.  If the
309
        // parity is fixed, then the parity bit is given by the fixed parity
310
        // value (r_setup[24]).  Otherwise the parity is given by the GF2
311
        // sum of all the data bits (plus one for even parity).
312
        always @(posedge i_clk)
313
                if (fixd_parity)
314
                        calc_parity <= fixdp_value;
315
                else if (zero_baud_counter)
316
                begin
317
                        if (state[3] == 0) // First 8 bits of msg
318
                                calc_parity <= calc_parity ^ lcl_data[0];
319
                        else
320
                                calc_parity <= parity_even;
321
                end else if (!r_busy)
322
                        calc_parity <= parity_even;
323
 
324
 
325
        // All of the above logic is driven by the baud counter.  Bits must last
326
        // clocks_per_baud in length, and this baud counter is what we use to
327
        // make certain of that.
328
        //
329
        // The basic logic is this: at the beginning of a bit interval, start
330
        // the baud counter and set it to count clocks_per_baud.  When it gets
331
        // to zero, restart it.
332
        //
333
        // However, comparing a 28'bit number to zero can be rather complex--
334
        // especially if we wish to do anything else on that same clock.  For
335
        // that reason, we create "zero_baud_counter".  zero_baud_counter is
336
        // nothing more than a flag that is true anytime baud_counter is zero.
337
        // It's true when the logic (above) needs to step to the next bit.
338
        // Simple enough?
339
        //
340
        // I wish we could stop there, but there are some other (ugly)
341
        // conditions to deal with that offer exceptions to this basic logic.
342
        //
343
        // 1. When the user has commanded a BREAK across the line, we need to
344
        // wait several baud intervals following the break before we start
345
        // transmitting, to give any receiver a chance to recognize that we are
346
        // out of the break condition, and to know that the next bit will be
347
        // a stop bit.
348
        //
349
        // 2. A reset is similar to a break condition--on both we wait several
350
        // baud intervals before allowing a start bit.
351
        //
352
        // 3. In the idle state, we stop our counter--so that upon a request
353
        // to transmit when idle we can start transmitting immediately, rather
354
        // than waiting for the end of the next (fictitious and arbitrary) baud
355
        // interval.
356
        //
357
        // When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
358
        // the idle state, but we also just accepted a command to start writing
359
        // the next word.  At this point, the baud counter needs to be reset
360
        // to the number of clocks per baud, and zero_baud_counter set to zero.
361
        //
362
        // The logic is a bit twisted here, in that it will only check for the
363
        // above condition when zero_baud_counter is false--so as to make
364
        // certain the STOP bit is complete.
365
        initial zero_baud_counter = 1'b0;
366
        initial baud_counter = 28'h05;
367
        always @(posedge i_clk)
368 3 dgisselq
        begin
369
                zero_baud_counter <= (baud_counter == 28'h01);
370
                if ((i_reset)||(i_break))
371 50 dgisselq
                begin
372 3 dgisselq
                        // Give ourselves 16 bauds before being ready
373
                        baud_counter <= break_condition;
374 50 dgisselq
                        zero_baud_counter <= 1'b0;
375
                end else if (!zero_baud_counter)
376 3 dgisselq
                        baud_counter <= baud_counter - 28'h01;
377
                else if (state == `TXU_BREAK)
378 50 dgisselq
                        // Give us four idle baud intervals before becoming
379
                        // available
380 3 dgisselq
                        baud_counter <= clocks_per_baud<<2;
381
                else if (state == `TXU_IDLE)
382
                begin
383 50 dgisselq
                        baud_counter <= 28'h0;
384
                        zero_baud_counter <= 1'b1;
385
                        if ((i_wr)&&(!r_busy))
386
                        begin
387 3 dgisselq
                                baud_counter <= clocks_per_baud - 28'h01;
388 50 dgisselq
                                zero_baud_counter <= 1'b0;
389
                        end
390 3 dgisselq
                end else
391
                        baud_counter <= clocks_per_baud - 28'h01;
392
        end
393
endmodule
394
 

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