URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [wbicapetwo.v] - Blame information for rev 13

Go to most recent revision | Details | Compare with Previous | View Log


///////////////////////////////////////////////////////////////////////////
//
// Filename:    wbicapetwo.v
//
// Project:     Wishbone to ICAPE2 interface conversion
//
// Purpose:     This routine maps the configuration registers of a 7-series
//              Xilinx part onto register addresses on a wishbone bus interface
//              via the ICAPE2 access port to those parts.  The big thing this
//              captures is the timing and handshaking required to read and
//              write registers from the configuration interface.
//
//              As an example of what can be done, writing a 32'h00f to
//              local address 5'h4 sends the IPROG command to the FPGA, causing
//              it to immediately reconfigure itself.
//
//              As another example, the warm boot start address is located
//              in register 5'h10.  Writing to this address, followed by
//              issuing the IPROG command just mentioned will cause the
//              FPGA to configure from that warm boot start address.
// 
//              For more details on the configuration interface, the registers
//              in question, their meanings and what they do, please see
//              User's Guide 470, the "7 Series FPGAs Configuration" User
//              Guide.
//
// Notes:       This module supports both reads and writes from the ICAPE2
//              interface.  These follow the following pattern.
//
//      For writes:
//              (Idle)  0xffffffff      (Dummy)
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0xaa995566      SYNC WORD
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  ...             Write command
//              (CS/W)  ...             Write value, from Wishbone bus
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x30008001      Write to CMD register (address 4)
//              (CS/W)  0x0000000d      DESYNC command
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (Idle)
//
//      and for reads:
//              (Idle)  0xffffffff      (Dummy)
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0xaa995566      SYNC WORD
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  ...             Read command
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (Idle)  0x20000000      (Idle the interface again, so we can rd)
//              (CS/R)  0x20000000      (Wait)
//              (CS/R)  0x20000000      (Wait)
//              (CS/R)  0x20000000      (Wait)
//              (CS/R)  0x20000000      (Wait)
//              (Idle)  0x20000000      (Idle the interface before writing)
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x30008001      Write to CMD register (address 4)
//              (CS/W)  0x0000000d      DESYNC command
//              (CS/W)  0x20000000      NOOP
//              (CS/W)  0x20000000      NOOP
//              (Idle)
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
`define MBOOT_IDLE      5'h00
`define MBOOT_START     5'h01
`define MBOOT_READ      5'h06
`define MBOOT_WRITE     5'h0f
`define MBOOT_DESYNC    5'h11
module  wbicapetwo(i_clk,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data, o_dbg);
        input                   i_clk;
        // Wishbone inputs
        input                   i_wb_cyc, i_wb_stb, i_wb_we;
        input           [4:0]    i_wb_addr;
        input           [31:0]   i_wb_data;
        // Wishbone outputs
        output  reg             o_wb_ack, o_wb_stall;
        output  reg     [31:0]   o_wb_data;
        // Debugging output
        output  wire    [31:0]   o_dbg;
        // ICAPE2 interface signals
        //      These are kept internal to this block ...
 
        reg             wb_req, r_we;
        reg     [31:0]   r_data;
        reg     [4:0]    r_addr;
 
`ifdef  DIVIDE_BY_FOUR
        reg     [1:0]    slow_clk_counter;
        reg             clk_stb, clk_stall;
        wire            slow_clk;
        always @(posedge i_clk)
        begin
                slow_clk  <= slow_clk + 2'b01;
                // We'll move on the positive edge of the clock, so therefore
                // clk_stb must be true one clock before that, so we test for
                // it one clock before that.
                clk_stb   <= (slow_clk_counter == 2'b10);
                // CLK_STALL is set to true two clocks before any cycle that
                // will, by necessity, stall.
                clk_stall <= (slow_clk_counter != 2'b01);
        end
 
        assign  slow_clk = slow_clk_counter[1];
`else
        reg             slow_clk, clk_stb, clk_stall;
        always @(posedge i_clk)
        begin
                slow_clk  <= (slow_clk + 1'b1);
                // We'll move on the positive edge of the clock, so therefore
                // clk_stb must be true one clock before that, so we test for
                // it one clock before that.
                clk_stb   <= (slow_clk == 1'b1);
                // CLK_STALL is set to true two clocks before any cycle that
                // will, by necessity, stall.
                clk_stall <= (slow_clk != 1'b0); //True all but one clock
        end
`endif
 
        reg     [31:0]   cfg_in;
        reg             cfg_cs_n, cfg_rdwrn;
        wire    [31:0]   cfg_out;
        reg     [4:0]    state;
        initial state = `MBOOT_IDLE;
        initial cfg_cs_n = 1'b1;
        always @(posedge i_clk)
        begin
                // In general, o_wb_ack is always zero.  The exceptions to this
                // will be handled individually below.
                o_wb_ack <= 1'b0;
                // We can simplify our logic a touch by always setting
                // o_wb_data.  It will only be examined if o_wb_ack
                // is also true, so this is okay.
                o_wb_data <= cfg_out;
 
                // Turn any request "off", so that it will not be ack'd, if
                // the wb_cyc line is ever lowered.
                wb_req <= wb_req & i_wb_cyc;
                o_wb_stall <= (state != `MBOOT_IDLE)||(clk_stall);
                if (clk_stb)
                begin
                        state <= state + 5'h01;
                        case(state)
                        `MBOOT_IDLE: begin
                                cfg_cs_n <= 1'b1;
                                cfg_rdwrn <= 1'b1;
                                cfg_in <= 32'hffffffff; // Dummy word
 
                                state <= `MBOOT_IDLE;
 
                                o_wb_ack <= 1'b0;
 
                                r_addr <= i_wb_addr;
                                r_data <= i_wb_data;
                                r_we   <= i_wb_we;
                                if(i_wb_stb) // &&(!o_wb_stall)
                                begin
                                        state <= `MBOOT_START;
                                        wb_req <= 1'b1;
                                        //
                                        o_wb_ack <= 1'b0;
                                end end
                        `MBOOT_START: begin
                                cfg_in <= 32'hffffffff; // NOOP
                                cfg_cs_n <= 1'b1;
                                end
                        5'h02: begin
                                cfg_cs_n <= 1'b0; // Activate interface
                                cfg_rdwrn <= 1'b0;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h03: begin
                                cfg_in <= 32'haa995566; // Sync word
                                cfg_cs_n <= 1'b0;
                                end
                        5'h04: begin
                                cfg_in <= 32'h20000000; // NOOP
                                cfg_cs_n <= 1'b0;
                                end
                        5'h05: begin
                                cfg_in <= 32'h20000000; // NOOP
                                state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
                                cfg_cs_n <= 1'b0;
                                end
                        `MBOOT_READ: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };
                                end
                        5'h07: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h08: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h09: begin // Idle the interface before the read cycle
                                cfg_cs_n <= 1'b1;
                                cfg_rdwrn <= 1'b1;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h0a: begin // Re-activate the interface and wait 3 cycles
                                cfg_cs_n <= 1'b0;
                                cfg_rdwrn <= 1'b1;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h0b: begin // ... still waiting, cycle two
                                cfg_in <= 32'h20000000; // NOOP
                                cfg_cs_n <= 1'b0;
                                end
                        5'h0c: begin // ... still waiting, cycle three
                                cfg_in <= 32'h20000000; // NOOP
                                cfg_cs_n <= 1'b0;
                                end
                        5'h0d: begin // ... still waiting, cycle four
                                cfg_in <= 32'h20000000; // NOOP
                                cfg_cs_n <= 1'b0;
                                end
                        5'h0e: begin // and now our answer is there
                                cfg_cs_n <= 1'b1;
                                cfg_rdwrn <= 1'b1;
                                cfg_in <= 32'h20000000; // NOOP
                                //
                                // Wishbone return
                                o_wb_ack <= wb_req;
                                // o_wb_data <= cfg_out; // Independent of state
                                wb_req <= 1'b0;
                                //
                                state <= `MBOOT_DESYNC;
                                end
                        `MBOOT_WRITE: begin
                                // Issue a write command to the given address
                                cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };
                                cfg_cs_n <= 1'b0;
                                end
                        5'h10: begin
                                cfg_in <= r_data;       // Write the value
                                cfg_cs_n <= 1'b0;
                                end
                        `MBOOT_DESYNC: begin
                                cfg_cs_n <= 1'b0;
                                cfg_rdwrn <= 1'b0;
                                cfg_in <= 32'h20000000; // 1st NOOP
                                end
                        5'h12: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h20000000; // 2nd NOOP
                                end
                        5'h13: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h30008001; // Write to CMD register
                                end
                        5'h14: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h0000000d; // DESYNC command
                                end
                        5'h15: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h16: begin
                                cfg_cs_n <= 1'b0;
                                cfg_in <= 32'h20000000; // NOOP
                                end
                        5'h17: begin
                                // Acknowledge the bus transaction, it is now complete
                                o_wb_ack <= wb_req;
                                wb_req <= 1'b0;
                                //
                                cfg_cs_n <= 1'b1;
                                cfg_rdwrn <= 1'b0;
                                cfg_in <= 32'hffffffff; // DUMMY
                                //
                                state <= `MBOOT_IDLE;
                                end
                        default: begin
                                wb_req <= 1'b0;
                                cfg_cs_n <= 1'b1;
                                cfg_rdwrn <= 1'b0;
                                state <= `MBOOT_IDLE;
                                cfg_in <= 32'hffffffff; // DUMMY WORD
                                end
                        endcase
                end
        end
 
        genvar  k;
        //
        // The data registers to the ICAPE2 interface are bit swapped within
        // each byte.  Thus, in order to read from or write to the interface,
        // we need to bit swap the bits in each byte.  These next lines
        // accomplish that for both the input and output ports.
        //
        wire    [31:0]   bit_swapped_cfg_in;
        generate
        for(k=0; k<8; k=k+1)
        begin
                assign bit_swapped_cfg_in[   k] = cfg_in[   7-k];
                assign bit_swapped_cfg_in[ 8+k] = cfg_in[ 8+7-k];
                assign bit_swapped_cfg_in[16+k] = cfg_in[16+7-k];
                assign bit_swapped_cfg_in[24+k] = cfg_in[24+7-k];
        end endgenerate
 
        wire    [31:0]   bit_swapped_cfg_out;
        generate
        for(k=0; k<8; k=k+1)
        begin
                assign cfg_out[   k] = bit_swapped_cfg_out[   7-k];
                assign cfg_out[ 8+k] = bit_swapped_cfg_out[ 8+7-k];
                assign cfg_out[16+k] = bit_swapped_cfg_out[16+7-k];
                assign cfg_out[24+k] = bit_swapped_cfg_out[24+7-k];
        end endgenerate
 
        ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),
                        .CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),
                        .I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));
 
        assign o_dbg = {
`ifdef  DIVIDE_BY_FOUR
                slow_clk_counter, clk_stb, clk_stall,
`else
                1'b0, slow_clk, clk_stb, clk_stall,
`endif
                i_wb_stb, o_wb_ack, cfg_cs_n, cfg_rdwrn,
                o_wb_stall, state, 2'h0,
                        cfg_in[7:0],
                        cfg_out[7:0] };
 
endmodule

Line No.	Rev	Author	Line
1	3	dgisselq	`///////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: wbicapetwo.v`
4			`//`
5			`// Project: Wishbone to ICAPE2 interface conversion`
6			`//`
7			`// Purpose: This routine maps the configuration registers of a 7-series`
8			`// Xilinx part onto register addresses on a wishbone bus interface`
9			`// via the ICAPE2 access port to those parts. The big thing this`
10			`// captures is the timing and handshaking required to read and`
11			`// write registers from the configuration interface.`
12			`//`
13			`// As an example of what can be done, writing a 32'h00f to`
14			`// local address 5'h4 sends the IPROG command to the FPGA, causing`
15			`// it to immediately reconfigure itself.`
16			`//`
17			`// As another example, the warm boot start address is located`
18			`// in register 5'h10. Writing to this address, followed by`
19			`// issuing the IPROG command just mentioned will cause the`
20			`// FPGA to configure from that warm boot start address.`
21			`//`
22			`// For more details on the configuration interface, the registers`
23			`// in question, their meanings and what they do, please see`
24			`// User's Guide 470, the "7 Series FPGAs Configuration" User`
25			`// Guide.`
26			`//`
27			`// Notes: This module supports both reads and writes from the ICAPE2`
28			`// interface. These follow the following pattern.`
29			`//`
30			`// For writes:`
31			`// (Idle) 0xffffffff (Dummy)`
32			`// (CS/W) 0x20000000 NOOP`
33			`// (CS/W) 0xaa995566 SYNC WORD`
34			`// (CS/W) 0x20000000 NOOP`
35			`// (CS/W) 0x20000000 NOOP`
36			`// (CS/W) ... Write command`
37			`// (CS/W) ... Write value, from Wishbone bus`
38			`// (CS/W) 0x20000000 NOOP`
39			`// (CS/W) 0x20000000 NOOP`
40			`// (CS/W) 0x30008001 Write to CMD register (address 4)`
41			`// (CS/W) 0x0000000d DESYNC command`
42			`// (CS/W) 0x20000000 NOOP`
43			`// (CS/W) 0x20000000 NOOP`
44			`// (Idle)`
45			`//`
46			`// and for reads:`
47			`// (Idle) 0xffffffff (Dummy)`
48			`// (CS/W) 0x20000000 NOOP`
49			`// (CS/W) 0xaa995566 SYNC WORD`
50			`// (CS/W) 0x20000000 NOOP`
51			`// (CS/W) 0x20000000 NOOP`
52			`// (CS/W) ... Read command`
53			`// (CS/W) 0x20000000 NOOP`
54			`// (CS/W) 0x20000000 NOOP`
55			`// (Idle) 0x20000000 (Idle the interface again, so we can rd)`
56			`// (CS/R) 0x20000000 (Wait)`
57			`// (CS/R) 0x20000000 (Wait)`
58			`// (CS/R) 0x20000000 (Wait)`
59			`// (CS/R) 0x20000000 (Wait)`
60			`// (Idle) 0x20000000 (Idle the interface before writing)`
61			`// (CS/W) 0x20000000 NOOP`
62			`// (CS/W) 0x20000000 NOOP`
63			`// (CS/W) 0x30008001 Write to CMD register (address 4)`
64			`// (CS/W) 0x0000000d DESYNC command`
65			`// (CS/W) 0x20000000 NOOP`
66			`// (CS/W) 0x20000000 NOOP`
67			`// (Idle)`
68			`// Creator: Dan Gisselquist, Ph.D.`
69			`// Gisselquist Technology, LLC`
70			`//`
71			`///////////////////////////////////////////////////////////////////////////`
72			`//`
73			`// Copyright (C) 2015, Gisselquist Technology, LLC`
74			`//`
75			`// This program is free software (firmware): you can redistribute it and/or`
76			`// modify it under the terms of the GNU General Public License as published`
77			`// by the Free Software Foundation, either version 3 of the License, or (at`
78			`// your option) any later version.`
79			`//`
80			`// This program is distributed in the hope that it will be useful, but WITHOUT`
81			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
82			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
83			`// for more details.`
84			`//`
85			`// License: GPL, v3, as defined and found on www.gnu.org,`
86			`// http://www.gnu.org/licenses/gpl.html`
87			`//`
88			`//`
89			`///////////////////////////////////////////////////////////////////////////`
90			`//`
91			`define MBOOT_IDLE 5'h00
92			`define MBOOT_START 5'h01
93			`define MBOOT_READ 5'h06
94			`define MBOOT_WRITE 5'h0f
95			`define MBOOT_DESYNC 5'h11
96			`module wbicapetwo(i_clk,`
97			`i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,`
98	13	dgisselq	`o_wb_ack, o_wb_stall, o_wb_data, o_dbg);`
99	3	dgisselq	`input i_clk;`
100			`// Wishbone inputs`
101			`input i_wb_cyc, i_wb_stb, i_wb_we;`
102			`input [4:0] i_wb_addr;`
103			`input [31:0] i_wb_data;`
104			`// Wishbone outputs`
105			`output reg o_wb_ack, o_wb_stall;`
106			`output reg [31:0] o_wb_data;`
107	13	dgisselq	`// Debugging output`
108			`output wire [31:0] o_dbg;`
109	3	dgisselq	`// ICAPE2 interface signals`
110			`// These are kept internal to this block ...`
111
112			`reg wb_req, r_we;`
113			`reg [31:0] r_data;`
114			`reg [4:0] r_addr;`
115
116	13	dgisselq	`ifdef DIVIDE_BY_FOUR
117			`reg [1:0] slow_clk_counter;`
118			`reg clk_stb, clk_stall;`
119			`wire slow_clk;`
120			`always @(posedge i_clk)`
121			`begin`
122			`slow_clk <= slow_clk + 2'b01;`
123			`// We'll move on the positive edge of the clock, so therefore`
124			`// clk_stb must be true one clock before that, so we test for`
125			`// it one clock before that.`
126			`clk_stb <= (slow_clk_counter == 2'b10);`
127			`// CLK_STALL is set to true two clocks before any cycle that`
128			`// will, by necessity, stall.`
129			`clk_stall <= (slow_clk_counter != 2'b01);`
130			`end`
131
132			`assign slow_clk = slow_clk_counter[1];`
133			`else
134			`reg slow_clk, clk_stb, clk_stall;`
135			`always @(posedge i_clk)`
136			`begin`
137			`slow_clk <= (slow_clk + 1'b1);`
138			`// We'll move on the positive edge of the clock, so therefore`
139			`// clk_stb must be true one clock before that, so we test for`
140			`// it one clock before that.`
141			`clk_stb <= (slow_clk == 1'b1);`
142			`// CLK_STALL is set to true two clocks before any cycle that`
143			`// will, by necessity, stall.`
144			`clk_stall <= (slow_clk != 1'b0); //True all but one clock`
145			`end`
146			`endif
147
148	3	dgisselq	`reg [31:0] cfg_in;`
149			`reg cfg_cs_n, cfg_rdwrn;`
150			`wire [31:0] cfg_out;`
151			`reg [4:0] state;`
152			initial state = `MBOOT_IDLE;
153			`initial cfg_cs_n = 1'b1;`
154			`always @(posedge i_clk)`
155			`begin`
156	13	dgisselq	`// In general, o_wb_ack is always zero. The exceptions to this`
157			`// will be handled individually below.`
158	3	dgisselq	`o_wb_ack <= 1'b0;`
159	13	dgisselq	`// We can simplify our logic a touch by always setting`
160			`// o_wb_data. It will only be examined if o_wb_ack`
161			`// is also true, so this is okay.`
162			`o_wb_data <= cfg_out;`
163
164	3	dgisselq	`// Turn any request "off", so that it will not be ack'd, if`
165			`// the wb_cyc line is ever lowered.`
166			`wb_req <= wb_req & i_wb_cyc;`
167	13	dgisselq	o_wb_stall <= (state != `MBOOT_IDLE)\|\|(clk_stall);
168			`if (clk_stb)`
169	3	dgisselq	`begin`
170			`state <= state + 5'h01;`
171			`case(state)`
172			`MBOOT_IDLE: begin
173			`cfg_cs_n <= 1'b1;`
174			`cfg_rdwrn <= 1'b1;`
175			`cfg_in <= 32'hffffffff; // Dummy word`
176
177			state <= `MBOOT_IDLE;
178
179			`o_wb_ack <= 1'b0;`
180
181			`r_addr <= i_wb_addr;`
182			`r_data <= i_wb_data;`
183			`r_we <= i_wb_we;`
184	13	dgisselq	`if(i_wb_stb) // &&(!o_wb_stall)`
185	3	dgisselq	`begin`
186			state <= `MBOOT_START;
187			`wb_req <= 1'b1;`
188			`//`
189			`o_wb_ack <= 1'b0;`
190			`end end`
191	13	dgisselq	`MBOOT_START: begin
192			`cfg_in <= 32'hffffffff; // NOOP`
193			`cfg_cs_n <= 1'b1;`
194			`end`
195	3	dgisselq	`5'h02: begin`
196			`cfg_cs_n <= 1'b0; // Activate interface`
197			`cfg_rdwrn <= 1'b0;`
198			`cfg_in <= 32'h20000000; // NOOP`
199			`end`
200	13	dgisselq	`5'h03: begin`
201			`cfg_in <= 32'haa995566; // Sync word`
202			`cfg_cs_n <= 1'b0;`
203			`end`
204			`5'h04: begin`
205			`cfg_in <= 32'h20000000; // NOOP`
206			`cfg_cs_n <= 1'b0;`
207			`end`
208	3	dgisselq	`5'h05: begin`
209			`cfg_in <= 32'h20000000; // NOOP`
210			state <= (r_we) ? `MBOOT_WRITE : `MBOOT_READ;
211	13	dgisselq	`cfg_cs_n <= 1'b0;`
212	3	dgisselq	`end`
213	13	dgisselq	`MBOOT_READ: begin
214			`cfg_cs_n <= 1'b0;`
215			`cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 };`
216			`end`
217			`5'h07: begin`
218			`cfg_cs_n <= 1'b0;`
219			`cfg_in <= 32'h20000000; // NOOP`
220			`end`
221			`5'h08: begin`
222			`cfg_cs_n <= 1'b0;`
223			`cfg_in <= 32'h20000000; // NOOP`
224			`end`
225	3	dgisselq	`5'h09: begin // Idle the interface before the read cycle`
226			`cfg_cs_n <= 1'b1;`
227			`cfg_rdwrn <= 1'b1;`
228			`cfg_in <= 32'h20000000; // NOOP`
229			`end`
230			`5'h0a: begin // Re-activate the interface and wait 3 cycles`
231			`cfg_cs_n <= 1'b0;`
232			`cfg_rdwrn <= 1'b1;`
233			`cfg_in <= 32'h20000000; // NOOP`
234			`end`
235	13	dgisselq	`5'h0b: begin // ... still waiting, cycle two`
236	3	dgisselq	`cfg_in <= 32'h20000000; // NOOP`
237	13	dgisselq	`cfg_cs_n <= 1'b0;`
238			`end`
239			`5'h0c: begin // ... still waiting, cycle three`
240	3	dgisselq	`cfg_in <= 32'h20000000; // NOOP`
241	13	dgisselq	`cfg_cs_n <= 1'b0;`
242			`end`
243			`5'h0d: begin // ... still waiting, cycle four`
244	3	dgisselq	`cfg_in <= 32'h20000000; // NOOP`
245	13	dgisselq	`cfg_cs_n <= 1'b0;`
246			`end`
247	3	dgisselq	`5'h0e: begin // and now our answer is there`
248			`cfg_cs_n <= 1'b1;`
249			`cfg_rdwrn <= 1'b1;`
250			`cfg_in <= 32'h20000000; // NOOP`
251			`//`
252			`// Wishbone return`
253			`o_wb_ack <= wb_req;`
254	13	dgisselq	`// o_wb_data <= cfg_out; // Independent of state`
255	3	dgisselq	`wb_req <= 1'b0;`
256			`//`
257			state <= `MBOOT_DESYNC;
258			`end`
259	13	dgisselq	`MBOOT_WRITE: begin
260			`// Issue a write command to the given address`
261	3	dgisselq	`cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 };`
262	13	dgisselq	`cfg_cs_n <= 1'b0;`
263			`end`
264			`5'h10: begin`
265			`cfg_in <= r_data; // Write the value`
266			`cfg_cs_n <= 1'b0;`
267			`end`
268	3	dgisselq	`MBOOT_DESYNC: begin
269			`cfg_cs_n <= 1'b0;`
270			`cfg_rdwrn <= 1'b0;`
271			`cfg_in <= 32'h20000000; // 1st NOOP`
272			`end`
273	13	dgisselq	`5'h12: begin`
274			`cfg_cs_n <= 1'b0;`
275			`cfg_in <= 32'h20000000; // 2nd NOOP`
276			`end`
277			`5'h13: begin`
278			`cfg_cs_n <= 1'b0;`
279			`cfg_in <= 32'h30008001; // Write to CMD register`
280			`end`
281			`5'h14: begin`
282			`cfg_cs_n <= 1'b0;`
283			`cfg_in <= 32'h0000000d; // DESYNC command`
284			`end`
285			`5'h15: begin`
286			`cfg_cs_n <= 1'b0;`
287			`cfg_in <= 32'h20000000; // NOOP`
288			`end`
289			`5'h16: begin`
290			`cfg_cs_n <= 1'b0;`
291			`cfg_in <= 32'h20000000; // NOOP`
292			`end`
293	3	dgisselq	`5'h17: begin`
294			`// Acknowledge the bus transaction, it is now complete`
295			`o_wb_ack <= wb_req;`
296			`wb_req <= 1'b0;`
297			`//`
298			`cfg_cs_n <= 1'b1;`
299			`cfg_rdwrn <= 1'b0;`
300			`cfg_in <= 32'hffffffff; // DUMMY`
301			`//`
302			state <= `MBOOT_IDLE;
303			`end`
304			`default: begin`
305	13	dgisselq	`wb_req <= 1'b0;`
306	3	dgisselq	`cfg_cs_n <= 1'b1;`
307			`cfg_rdwrn <= 1'b0;`
308			state <= `MBOOT_IDLE;
309			`cfg_in <= 32'hffffffff; // DUMMY WORD`
310			`end`
311			`endcase`
312			`end`
313			`end`
314
315			`genvar k;`
316			`//`
317			`// The data registers to the ICAPE2 interface are bit swapped within`
318			`// each byte. Thus, in order to read from or write to the interface,`
319			`// we need to bit swap the bits in each byte. These next lines`
320			`// accomplish that for both the input and output ports.`
321			`//`
322			`wire [31:0] bit_swapped_cfg_in;`
323			`generate`
324			`for(k=0; k<8; k=k+1)`
325			`begin`
326			`assign bit_swapped_cfg_in[ k] = cfg_in[ 7-k];`
327			`assign bit_swapped_cfg_in[ 8+k] = cfg_in[ 8+7-k];`
328			`assign bit_swapped_cfg_in[16+k] = cfg_in[16+7-k];`
329			`assign bit_swapped_cfg_in[24+k] = cfg_in[24+7-k];`
330			`end endgenerate`
331
332			`wire [31:0] bit_swapped_cfg_out;`
333			`generate`
334			`for(k=0; k<8; k=k+1)`
335			`begin`
336			`assign cfg_out[ k] = bit_swapped_cfg_out[ 7-k];`
337			`assign cfg_out[ 8+k] = bit_swapped_cfg_out[ 8+7-k];`
338			`assign cfg_out[16+k] = bit_swapped_cfg_out[16+7-k];`
339			`assign cfg_out[24+k] = bit_swapped_cfg_out[24+7-k];`
340			`end endgenerate`
341
342			`ICAPE2 #(.ICAP_WIDTH("X32")) reconfig(.CLK(slow_clk),`
343			`.CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn),`
344			`.I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out));`
345	13	dgisselq
346			`assign o_dbg = {`
347			`ifdef DIVIDE_BY_FOUR
348			`slow_clk_counter, clk_stb, clk_stall,`
349			`else
350			`1'b0, slow_clk, clk_stb, clk_stall,`
351			`endif
352			`i_wb_stb, o_wb_ack, cfg_cs_n, cfg_rdwrn,`
353			`o_wb_stall, state, 2'h0,`
354			`cfg_in[7:0],`
355			`cfg_out[7:0] };`
356
357	3	dgisselq	`endmodule`

Browse

Tools

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [wbicapetwo.v] - Blame information for rev 13