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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbm2axisp.v
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//
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// Project: Pipelined Wishbone to AXI converter
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//
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// Purpose: The B4 Wishbone SPEC allows transactions at a speed as fast as
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// one per clock. The AXI bus allows transactions at a speed of
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// one read and one write transaction per clock. These capabilities work
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// by allowing requests to take place prior to responses, such that the
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// requests might go out at once per clock and take several clocks, and
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// the responses may start coming back several clocks later. In other
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// words, both protocols allow multiple transactions to be "in flight" at
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// the same time. Current wishbone to AXI converters, however, handle only
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// one transaction at a time: initiating the transaction, and then waiting
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// for the transaction to complete before initiating the next.
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//
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// The purpose of this core is to maintain the speed of both busses, while
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// transiting from the Wishbone (as master) to the AXI bus (as slave) and
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// back again.
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//
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// Since the AXI bus allows transactions to be reordered, whereas the
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// wishbone does not, this core can be configured to reorder return
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// transactions as well.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module wbm2axisp #(
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
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parameter DW = 32, // Wishbone data width
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parameter AW = 26, // Wishbone address width
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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) (
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input i_clk, // System clock
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// input i_reset,// Wishbone reset signal--unused
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// AXI write address channel signals
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input i_axi_awready, // Slave is ready to accept
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output reg [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
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output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address
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output wire [7:0] o_axi_awlen, // Write Burst Length
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output wire [2:0] o_axi_awsize, // Write Burst size
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output wire [1:0] o_axi_awburst, // Write Burst type
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output wire [0:0] o_axi_awlock, // Write lock type
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output wire [3:0] o_axi_awcache, // Write Cache type
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output wire [2:0] o_axi_awprot, // Write Protection type
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output wire [3:0] o_axi_awqos, // Write Quality of Svc
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output reg o_axi_awvalid, // Write address valid
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// AXI write data channel signals
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input i_axi_wready, // Write data ready
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output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wdata, // Write data
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output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wstrb, // Write strobes
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output wire o_axi_wlast, // Last write transaction
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output reg o_axi_wvalid, // Write valid
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// AXI write response channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_bid, // Response ID
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input [1:0] i_axi_bresp, // Write response
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input i_axi_bvalid, // Write reponse valid
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output wire o_axi_bready, // Response ready
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// AXI read address channel signals
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input i_axi_arready, // Read address ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
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output wire [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address
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output wire [7:0] o_axi_arlen, // Read Burst Length
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output wire [2:0] o_axi_arsize, // Read Burst size
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output wire [1:0] o_axi_arburst, // Read Burst type
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output wire [0:0] o_axi_arlock, // Read lock type
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output wire [3:0] o_axi_arcache, // Read Cache type
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output wire [2:0] o_axi_arprot, // Read Protection type
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output wire [3:0] o_axi_arqos, // Read Protection type
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output reg o_axi_arvalid, // Read address valid
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// AXI read data channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_rid, // Response ID
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input [1:0] i_axi_rresp, // Read response
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input i_axi_rvalid, // Read reponse valid
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input [C_AXI_DATA_WIDTH-1:0] i_axi_rdata, // Read data
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input i_axi_rlast, // Read last
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output wire o_axi_rready, // Read Response ready
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// We'll share the clock and the reset
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_we,
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input [(AW-1):0] i_wb_addr,
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input [(DW-1):0] i_wb_data,
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input [(DW/8-1):0] i_wb_sel,
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output reg o_wb_ack,
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output wire o_wb_stall,
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output reg [(DW-1):0] o_wb_data,
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output reg o_wb_err,
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output wire [31:0] o_dbg
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);
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//*****************************************************************************
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// Parameter declarations
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//*****************************************************************************
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localparam CTL_SIG_WIDTH = 3; // Control signal width
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localparam RD_STS_WIDTH = 16; // Read status signal width
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localparam WR_STS_WIDTH = 16; // Write status signal width
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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// Things we're not changing ...
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assign o_axi_awlen = 8'h0; // Burst length is one
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assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
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assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
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assign o_axi_awlock = 1'b0; // Normal signaling
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assign o_axi_arlock = 1'b0; // Normal signaling
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assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
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assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
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assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
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assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
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// Command logic
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// Write address logic
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always @(posedge i_clk)
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o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
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||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
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generate
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if (DW == 32)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall) // 26 bit address becomes 28 bit ...
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o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall) // 28 bit address ...
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o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };
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end endgenerate
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reg [5:0] transaction_id;
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always @(posedge i_clk)
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if (!i_wb_cyc)
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transaction_id <= 6'h00;
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else if ((i_wb_stb)&&(~o_wb_stall))
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transaction_id <= transaction_id + 6'h01;
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always @(posedge i_clk)
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if ((i_wb_stb)&&(~o_wb_stall))
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o_axi_awid <= transaction_id;
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// Read address logic
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assign o_axi_arid = o_axi_awid;
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assign o_axi_araddr = o_axi_awaddr;
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assign o_axi_arlen = o_axi_awlen;
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assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
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always @(posedge i_clk)
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o_axi_arvalid <= (!o_wb_stall)&&(i_wb_stb)&&(!i_wb_we)
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||(o_wb_stall)&&(o_axi_arvalid)&&(!i_axi_arready);
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// Write data logic
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generate
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if (DW == 32)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wdata <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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always @(posedge i_clk)
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if (!o_wb_stall)
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case(i_wb_addr[1:0])
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2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0,i_wb_sel};
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2'b01:o_axi_wstrb<={ 4'h0, 4'h0,i_wb_sel, 4'h0};
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2'b10:o_axi_wstrb<={ 4'h0,i_wb_sel, 4'h0, 4'h0};
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2'b11:o_axi_wstrb<={i_wb_sel, 4'h0, 4'h0, 4'h0};
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endcase
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wdata <= i_wb_data;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wstrb <= i_wb_sel;
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end endgenerate
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assign o_axi_wlast = 1'b1;
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always @(posedge i_clk)
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o_axi_wvalid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
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||(o_wb_stall)&&(o_axi_wvalid)&&(!i_axi_wready);
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// Read data channel / response logic
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assign o_axi_rready = 1'b1;
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assign o_axi_bready = 1'b1;
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wire w_fifo_full;
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generate
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if (STRICT_ORDER == 0)
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begin
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// Reorder FIFO
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//
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localparam LGFIFOLN = C_AXI_ID_WIDTH;
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localparam FIFOLN = (1<<LGFIFOLN);
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// FIFO reorder buffer
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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initial reorder_fifo_valid = 0;
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initial reorder_fifo_err = 0;
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if (DW == 32)
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begin
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] low_addr;
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always @(posedge i_clk)
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if ((i_wb_stb)&&(!o_wb_stall))
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low_addr <= i_wb_addr[1:0];
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always @(posedge i_clk)
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if ((o_axi_arvalid)&&(i_axi_arready))
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reorder_fifo_addr[o_axi_arid] <= low_addr;
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always @(posedge i_clk)
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case(reorder_fifo_addr[fifo_tail][1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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o_wb_data <= reorder_fifo_data[fifo_tail];
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end
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wire [(LGFIFOLN-1):0] fifo_head;
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assign fifo_head = transaction_id;
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// Let's do some math to figure out where the FIFO head will
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// point to next, but let's also insist that it be LGFIFOLN
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// bits in size as well. This'll be part of the fifo_full
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// calculation below.
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wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
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assign n_fifo_head = fifo_head+1'b1;
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assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
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always @(posedge i_clk)
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begin
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if ((i_axi_rvalid)&&(o_axi_rready))
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reorder_fifo_data[i_axi_rid]<= i_axi_rdata;
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if ((i_axi_rvalid)&&(o_axi_rready))
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begin
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reorder_fifo_valid[i_axi_rid] <= 1'b1;
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reorder_fifo_err[i_axi_rid] <= i_axi_rresp[1];
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end
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if ((i_axi_bvalid)&&(o_axi_bready))
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| 295 |
|
|
begin
|
| 296 |
|
|
reorder_fifo_valid[i_axi_bid] <= 1'b1;
|
| 297 |
|
|
reorder_fifo_err[i_axi_bid] <= i_axi_bresp[1];
|
| 298 |
|
|
end
|
| 299 |
|
|
|
| 300 |
|
|
if (reorder_fifo_valid[fifo_tail])
|
| 301 |
|
|
begin
|
| 302 |
|
|
o_wb_ack <= 1'b1;
|
| 303 |
|
|
o_wb_err <= reorder_fifo_err[fifo_tail];
|
| 304 |
|
|
fifo_tail <= fifo_tail + 6'h1;
|
| 305 |
|
|
reorder_fifo_valid[fifo_tail] <= 1'b0;
|
| 306 |
|
|
reorder_fifo_err[fifo_tail] <= 1'b0;
|
| 307 |
|
|
end else begin
|
| 308 |
|
|
o_wb_ack <= 1'b0;
|
| 309 |
|
|
o_wb_err <= 1'b0;
|
| 310 |
|
|
end
|
| 311 |
|
|
|
| 312 |
|
|
if (!i_wb_cyc)
|
| 313 |
|
|
begin
|
| 314 |
|
|
reorder_fifo_valid <= {(FIFOLN){1'b0}};
|
| 315 |
|
|
reorder_fifo_err <= {(FIFOLN){1'b0}};
|
| 316 |
|
|
fifo_tail <= 6'h0;
|
| 317 |
|
|
o_wb_err <= 1'b0;
|
| 318 |
|
|
o_wb_ack <= 1'b0;
|
| 319 |
|
|
end
|
| 320 |
|
|
end
|
| 321 |
|
|
|
| 322 |
|
|
assign o_dbg = {
|
| 323 |
|
|
i_wb_stb, o_wb_stall, o_wb_ack, o_wb_err,
|
| 324 |
|
|
fifo_head, fifo_tail, // 12 bits
|
| 325 |
|
|
{ ((i_axi_rvalid)&&(o_axi_rready)) ? i_axi_rid
|
| 326 |
|
|
: ((i_axi_bvalid)&&(o_axi_bready)) ? i_axi_bid
|
| 327 |
|
|
: 6'hf }, // 6 bits
|
| 328 |
|
|
o_axi_arvalid, i_axi_arready,
|
| 329 |
|
|
o_axi_awvalid, i_axi_awready,
|
| 330 |
|
|
o_axi_wvalid, i_axi_wready, // 28 bits so far ...
|
| 331 |
|
|
i_axi_rvalid, i_axi_bvalid, 2'b00
|
| 332 |
|
|
};
|
| 333 |
|
|
|
| 334 |
|
|
|
| 335 |
|
|
reg r_fifo_full;
|
| 336 |
|
|
always @(posedge i_clk)
|
| 337 |
|
|
begin
|
| 338 |
|
|
if (!i_wb_cyc)
|
| 339 |
|
|
r_fifo_full <= 1'b0;
|
| 340 |
|
|
else if ((i_wb_stb)&&(~o_wb_stall)
|
| 341 |
|
|
&&(reorder_fifo_valid[fifo_tail]))
|
| 342 |
|
|
r_fifo_full <= (fifo_tail==n_fifo_head);
|
| 343 |
|
|
else if ((i_wb_stb)&&(~o_wb_stall))
|
| 344 |
|
|
r_fifo_full <= (fifo_tail==nn_fifo_head);
|
| 345 |
|
|
else if (reorder_fifo_valid[fifo_tail])
|
| 346 |
|
|
r_fifo_full <= 1'b0;
|
| 347 |
|
|
else
|
| 348 |
|
|
r_fifo_full <= (fifo_tail==n_fifo_head);
|
| 349 |
|
|
end
|
| 350 |
|
|
assign w_fifo_full = r_fifo_full;
|
| 351 |
|
|
end else begin
|
| 352 |
|
|
//
|
| 353 |
|
|
// Strict ordering, but can only read every fourth addresses
|
| 354 |
|
|
//
|
| 355 |
|
|
assign w_fifo_full = 1'b0;
|
| 356 |
|
|
always @(posedge i_clk)
|
| 357 |
|
|
o_wb_data <= i_axi_rdata[31:0];
|
| 358 |
|
|
always @(posedge i_clk)
|
| 359 |
|
|
o_wb_ack <= (i_wb_cyc)&&(
|
| 360 |
|
|
((i_axi_rvalid)&&(o_axi_rready))
|
| 361 |
|
|
||((i_axi_bvalid)&&(o_axi_bready)));
|
| 362 |
|
|
always @(posedge i_clk)
|
| 363 |
|
|
o_wb_err <= (i_wb_cyc)&&((o_wb_err)
|
| 364 |
|
|
||((i_axi_rvalid)&&(i_axi_rresp[1]))
|
| 365 |
|
|
||((i_axi_bvalid)&&(i_axi_bresp[1])));
|
| 366 |
|
|
|
| 367 |
|
|
assign o_dbg = {
|
| 368 |
|
|
i_wb_stb, o_wb_stall, o_wb_ack, o_wb_err,
|
| 369 |
|
|
12'h00, // 12 bits
|
| 370 |
|
|
{ ((i_axi_rvalid)&&(o_axi_rready)) ? i_axi_rid
|
| 371 |
|
|
: ((i_axi_bvalid)&&(o_axi_bready)) ? i_axi_bid
|
| 372 |
|
|
: 6'hf }, // 6 bits
|
| 373 |
|
|
o_axi_arvalid, i_axi_arready,
|
| 374 |
|
|
o_axi_awvalid, i_axi_awready,
|
| 375 |
|
|
o_axi_wvalid, i_axi_wready, // 28 bits so far ...
|
| 376 |
|
|
i_axi_rvalid, i_axi_bvalid, 2'b00
|
| 377 |
|
|
};
|
| 378 |
|
|
end endgenerate
|
| 379 |
|
|
|
| 380 |
|
|
|
| 381 |
|
|
// Now, the difficult signal ... the stall signal
|
| 382 |
|
|
// Let's build for a single cycle input ... and only stall if something
|
| 383 |
|
|
// outgoing is valid and nothing is ready.
|
| 384 |
|
|
assign o_wb_stall = (i_wb_cyc)&&(
|
| 385 |
|
|
(w_fifo_full)
|
| 386 |
|
|
||((o_axi_awvalid)&&(!i_axi_awready))
|
| 387 |
|
|
||((o_axi_wvalid )&&(!i_axi_wready ))
|
| 388 |
|
|
||((o_axi_arvalid)&&(!i_axi_arready)));
|
| 389 |
|
|
endmodule
|
| 390 |
|
|
|
