| 1 |
3 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: wbudeword.v
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: FPGA library
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: Once a word has come from the bus, undergone compression, had
|
| 8 |
|
|
// idle cycles and interrupts placed in it, this routine converts
|
| 9 |
|
|
// that word form a 36-bit single word into a series of 6-bit words
|
| 10 |
|
|
// that can head to the output routine. Hence, it 'deword's the value:
|
| 11 |
|
|
// unencoding the 36-bit word encoding.
|
| 12 |
|
|
//
|
| 13 |
|
|
//
|
| 14 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 15 |
|
|
// Gisselquist Technology, LLC
|
| 16 |
|
|
//
|
| 17 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 18 |
|
|
//
|
| 19 |
|
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
| 20 |
|
|
//
|
| 21 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 22 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 23 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 24 |
|
|
// your option) any later version.
|
| 25 |
|
|
//
|
| 26 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 27 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 28 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 29 |
|
|
// for more details.
|
| 30 |
|
|
//
|
| 31 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 32 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 33 |
|
|
//
|
| 34 |
|
|
//
|
| 35 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 36 |
|
|
//
|
| 37 |
|
|
//
|
| 38 |
|
|
module wbudeword(i_clk, i_stb, i_word, i_tx_busy, o_stb, o_nl_hexbits, o_busy);
|
| 39 |
|
|
input i_clk, i_stb;
|
| 40 |
|
|
input [35:0] i_word;
|
| 41 |
|
|
input i_tx_busy;
|
| 42 |
|
|
output reg o_stb;
|
| 43 |
|
|
output reg [6:0] o_nl_hexbits;
|
| 44 |
|
|
output reg o_busy;
|
| 45 |
|
|
|
| 46 |
|
|
|
| 47 |
|
|
wire [2:0] w_len;
|
| 48 |
|
|
assign w_len = (i_word[35:33]==3'b000)? 3'b001
|
| 49 |
|
|
: (i_word[35:32]==4'h2)? 3'b110
|
| 50 |
|
|
: (i_word[35:32]==4'h3)? (3'b010+{1'b0,i_word[31:30]})
|
| 51 |
|
|
: (i_word[35:34]==2'b01)? 3'b010
|
| 52 |
|
|
: (i_word[35:34]==2'b10)? 3'b001
|
| 53 |
|
|
: 3'b110;
|
| 54 |
|
|
|
| 55 |
|
|
reg r_dly;
|
| 56 |
|
|
reg [2:0] r_len;
|
| 57 |
|
|
reg [29:0] r_word;
|
| 58 |
|
|
initial o_stb = 1'b0;
|
| 59 |
|
|
initial o_busy = 1'b0;
|
| 60 |
|
|
initial r_dly = 1'b0;
|
| 61 |
|
|
always @(posedge i_clk)
|
| 62 |
|
|
if ((i_stb)&&(~o_busy)) // Only accept when not busy
|
| 63 |
|
|
begin
|
| 64 |
|
|
r_len <= w_len-3'b001;
|
| 65 |
|
|
r_word <= i_word[29:0];
|
| 66 |
|
|
o_stb <= 1'b1;
|
| 67 |
|
|
o_nl_hexbits <= { 1'b0, i_word[35:30] }; // No newline ... yet
|
| 68 |
|
|
o_busy <= 1'b1;
|
| 69 |
|
|
r_dly <= 1'b1;
|
| 70 |
|
|
end else if ((o_stb)&&(i_tx_busy))
|
| 71 |
|
|
begin
|
| 72 |
|
|
o_busy <= 1'b1; // wait and do nothing
|
| 73 |
|
|
r_dly <= 1'b1;
|
| 74 |
|
|
end else if (o_stb) // and (~i_tx_busy) means ours was accepted
|
| 75 |
|
|
o_stb <= 1'b0; // Delay one clock
|
| 76 |
|
|
else if (r_len > 0)
|
| 77 |
|
|
begin
|
| 78 |
|
|
o_stb <= 1'b1;
|
| 79 |
|
|
o_nl_hexbits <= { 1'b0, r_word[29:24] };
|
| 80 |
|
|
r_word[29:6] <= r_word[23:0];
|
| 81 |
|
|
r_len <= r_len - 3'b001;
|
| 82 |
|
|
o_busy <= 1'b1; // wait and do nothing
|
| 83 |
|
|
r_dly <= 1'b1;
|
| 84 |
|
|
end else if (~o_nl_hexbits[6])
|
| 85 |
|
|
begin
|
| 86 |
|
|
o_stb <= 1'b1;
|
| 87 |
|
|
o_nl_hexbits <= 7'h40;
|
| 88 |
|
|
o_busy <= 1'b1; // wait and do nothing
|
| 89 |
|
|
r_dly <= 1'b1;
|
| 90 |
|
|
end else begin
|
| 91 |
|
|
r_dly <= 1'b0;
|
| 92 |
|
|
o_busy <= (r_dly);
|
| 93 |
|
|
end
|
| 94 |
|
|
|
| 95 |
|
|
endmodule
|
| 96 |
|
|
|
