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dgisselq |
///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbusixchar.v
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//
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// Project: FPGA library
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//
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// Purpose: Supports a conversion from a six digit bus to a printable
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// ASCII character representing those six bits. The encoding is
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// as follows:
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//
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// 0-9 -> 0-9
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// A-Z -> 10-35
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// a-z -> 36-61
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// @ -> 62
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// % -> 63
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//
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// Note that decoding is stateless, yet requires one clock.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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//
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module wbusixchar(i_clk, i_stb, i_bits, o_stb, o_char, o_busy, i_busy);
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input i_clk;
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input i_stb;
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input [6:0] i_bits;
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output reg o_stb;
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output reg [7:0] o_char;
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output wire o_busy;
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input i_busy;
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initial o_char = 8'h00;
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always @(posedge i_clk)
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if ((i_stb)&&(~o_busy))
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begin
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if (i_bits[6])
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o_char <= 8'h0a;
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else if (i_bits[5:0] <= 6'h09) // A digit, WORKS
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o_char <= "0" + { 4'h0, i_bits[3:0] };
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else if (i_bits[5:0] <= 6'd35) // Upper case
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o_char <= "A" + { 2'h0, i_bits[5:0] } - 8'd10; // -'A'+10
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else if (i_bits[5:0] <= 6'd61)
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o_char <= "a" + { 2'h0, i_bits[5:0] } - 8'd36;// -'a'+(10+26)
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else if (i_bits[5:0] == 6'd62) // An '@' sign
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o_char <= 8'h40;
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else // if (i_char == 6'h63) // A '%' sign
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o_char <= 8'h25;
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end
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always @(posedge i_clk)
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if ((o_stb)&&(~i_busy))
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o_stb <= 1'b0;
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else if ((i_stb)&&(~o_stb))
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o_stb <= 1'b1;
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assign o_busy = o_stb;
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endmodule
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