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[/] [openarty/] [trunk/] [rtl/] [wbutohex.v] - Blame information for rev 3

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1 3 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbutohex.v
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//
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// Project:     FPGA library
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//
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// Purpose:     Supports a printable character conversion from a printable
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//              ASCII character to six bits of valid data.  The encoding is
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//              as follows:
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//
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//              0-9     ->      0-9
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//              A-Z     ->      10-35
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//              a-z     ->      36-61
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//              @       ->      62
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//              %       ->      63
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//
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//              Note that decoding is stateless, yet requires one clock.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module  wbutohex(i_clk, i_stb, i_byte, o_stb, o_valid, o_hexbits);
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        input                   i_clk, i_stb;
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        input           [7:0]    i_byte;
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        output  reg             o_stb, o_valid;
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        output  reg     [5:0]    o_hexbits;
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        always @(posedge i_clk)
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                o_stb <= i_stb;
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        always @(posedge i_clk)
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        begin
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                // These are the defaults, to be overwridden by the ifs below
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                o_valid <= 1'b1;
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                o_hexbits <= 6'h00;
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                if ((i_byte >= 8'h30)&&(i_byte <= 8'h39)) // A digit
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                        o_hexbits <= { 2'b0, i_byte[3:0] };
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                else if ((i_byte >= 8'h41)&&(i_byte <= 8'h5a)) // Upper case
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                        o_hexbits <= (i_byte[5:0] - 6'h01 + 6'h0a);// -'A'+10
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                else if ((i_byte >= 8'h61)&&(i_byte <= 8'h7a))
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                        o_hexbits <= (i_byte[5:0] +6'h03);       // -'a'+(10+26)
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                else if (i_byte == 8'h40) // An '@' sign
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                        o_hexbits <= 6'h3e;
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                else if (i_byte == 8'h25) // A '%' sign
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                        o_hexbits <= 6'h3f;
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                else
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                        o_valid <= 1'b0;
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        end
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endmodule
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