OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [sim/] [verilated/] [enetctrlsim.h] - Blame information for rev 58

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 58 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    enetsim.h
4
//
5
// Project:     OpenArty, an entirely open SoC based upon the Arty platform
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Technology, LLC
11
//
12
////////////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2016, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// You should have received a copy of the GNU General Public License along
27
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
28
// target there if the PDF file isn't present.)  If not, see
29
// <http://www.gnu.org/licenses/> for a copy.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
#ifndef ENETCTRLSIM_H
39
#define ENETCTRLSIM_H
40
 
41
#define ENET_MEMWORDS   32
42
class   ENETCTRLSIM     {
43
        int     m_consecutive_clocks, m_lastout,
44
                m_tickcount, m_ticks_per_clock, m_lastclk;
45
        int     TICKS_PER_CLOCK, PHY_ADDR;
46
        int     m_mem[ENET_MEMWORDS];
47
 
48
public:
49
        bool    m_synched;
50
        int     m_datareg, m_halfword, m_outreg;
51
        ENETCTRLSIM(void);
52
        ~ENETCTRLSIM(void) {}
53
 
54
        int     operator()(int inreset, int clk, int data);
55
        int     operator[](int index) const;
56
};
57
 
58
#endif  // ENETCTRLSIM_H
59
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.