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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Module name: openhmc_sync_fifo_xilinx
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*
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*/
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`default_nettype none
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module openhmc_sync_fifo_xilinx #(
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`ifdef CAG_ASSERTIONS
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parameter DISABLE_EMPTY_ASSERT = 0,
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parameter DISABLE_FULL_ASSERT = 0,
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parameter DISABLE_SHIFT_OUT_ASSERT = 0,
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parameter DISABLE_XCHECK_ASSERT = 0,
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`endif
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parameter DWIDTH = 8
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) (
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input wire clk,
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input wire res_n,
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input wire [DWIDTH-1:0] d_in,
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input wire shift_in,
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input wire shift_out,
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output reg [DWIDTH-1:0] d_out,
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output wire full,
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output reg empty,
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output wire almost_full,
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output wire almost_empty
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);
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wire [DWIDTH-1:0] d_out_w;
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wire empty_w;
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wire shift_out_w;
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wire shift_in_w;
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assign shift_out_w = !empty_w && (empty || shift_out);
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assign shift_in_w = shift_in;
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`ifdef ASYNC_RES
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always @(posedge clk or negedge res_n) `else
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always @(posedge clk ) `endif
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begin
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if (!res_n)
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begin
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empty <= 1'b1;
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d_out <= {DWIDTH {1'b0}};
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end
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else
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begin
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if (!empty_w && (empty || shift_out))
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begin
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d_out <= d_out_w;
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empty <= 1'b0;
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end
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else if (shift_out)
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empty <= 1'b1;
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end
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end
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openhmc_srl_fifo_16 #(
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`ifdef CAG_ASSERTIONS
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.DISABLE_EMPTY_ASSERT(DISABLE_EMPTY_ASSERT),
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.DISABLE_FULL_ASSERT(DISABLE_FULL_ASSERT),
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`endif
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.DWIDTH(DWIDTH)
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) srl_fifo_I (
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.clk(clk),
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.res_n(res_n),
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.d_in(d_in),
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.d_out(d_out_w),
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.shift_out(shift_out_w),
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.shift_in(shift_in_w),
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.full(full),
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.almost_full(almost_full),
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.empty(empty_w),
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.almost_empty(almost_empty)
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);
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`ifdef CAG_COVERAGE
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full_cov: cover property (@(posedge clk) disable iff(!res_n) (full == 1'b1));
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almost_full_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_full == 1'b1));
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empty_cov: cover property (@(posedge clk) disable iff(!res_n) (empty == 1'b1));
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almost_empty_cov: cover property (@(posedge clk) disable iff(!res_n) (almost_empty == 1'b1));
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covergroup shift_in_and_out @(posedge clk);
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shift_in_and_out_cp: coverpoint ({shift_in, shift_out}) iff (shift_in || shift_out)
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{
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bins count[] = {[1:3]};
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}
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endgroup
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shift_in_and_out shift_in_and_out_I;
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initial begin
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shift_in_and_out_I = new();
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shift_in_and_out_I.set_inst_name("shift_in_and_out_I");
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end
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`endif // CAG_COVERAGE
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`ifdef CAG_ASSERTIONS
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shift_in_and_full: assert property (@(posedge clk) disable iff(!res_n) (shift_in |-> !full));
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if (DISABLE_SHIFT_OUT_ASSERT == 0)
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shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
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if (DISABLE_XCHECK_ASSERT == 0)
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d_out_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
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final
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begin
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if (DISABLE_FULL_ASSERT == 0)
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begin
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assert_full_set: assert (!full);
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assert_almost_full_set: assert (!almost_full);
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end
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if (DISABLE_EMPTY_ASSERT == 0)
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begin
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assert_almost_empty_not_set: assert (almost_empty);
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assert_empty_not_set: assert (empty);
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end
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end
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`endif // CAG_ASSERTIONS
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endmodule
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`default_nettype wire
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