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/*
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* .--------------. .----------------. .------------.
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* | .------------. | .--------------. | .----------. |
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* | | ____ ____ | | | ____ ____ | | | ______ | |
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* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
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* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
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* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
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* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
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* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
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* | | | | | | | | | | | |
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* |_| | '------------' | '--------------' | '----------' |
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* '--------------' '----------------' '------------'
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*
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* openHMC - An Open Source Hybrid Memory Cube Controller
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* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
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* www.ziti.uni-heidelberg.de
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* B6, 26
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* 68159 Mannheim
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* Germany
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*
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* Contact: openhmc@ziti.uni-heidelberg.de
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* http://ra.ziti.uni-heidelberg.de/openhmc
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*
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* This source file is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This source file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this source file. If not, see .
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*
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*
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*/
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`ifndef hmc_TB_SV
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`define hmc_TB_SV
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class hmc_tb #( parameter AXI4_DATA_BYTES=`AXI4BYTES, parameter AXI4_TUSER_WIDTH=`AXI4BYTES, parameter NUM_LANES=2**`LOG_NUM_LANES) extends uvm_env;
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//-- UVCs
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axi4_stream_env #(
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.DATA_BYTES(AXI4_DATA_BYTES),
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.TUSER_WIDTH(AXI4_TUSER_WIDTH)
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) axi4_req;
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axi4_stream_env #(
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.DATA_BYTES(AXI4_DATA_BYTES),
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.TUSER_WIDTH(AXI4_TUSER_WIDTH)
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) axi4_rsp;
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hmc_env # (.NUM_LANES(NUM_LANES))hmc;
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hmc_module_env hmc_module;
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axi4_stream_config axi4_rsp_config;
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axi4_stream_config axi4_req_config;
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hmc_link_config link_cfg;
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cag_rgm_rfs_env #(
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.ADDR_WIDTH(`RFS_OPENHMC_RF_AWIDTH),
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.READ_DATA_WIDTH(`RFS_OPENHMC_RF_RWIDTH),
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.WRITE_DATA_WIDTH(`RFS_OPENHMC_RF_WWIDTH)
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) rfs_hmc_I;
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rf_openhmc_rf_c rf_model_hmc;
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vseqr v_seqr;
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int i = 2;
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`uvm_component_param_utils(hmc_tb #(.AXI4_DATA_BYTES(AXI4_DATA_BYTES), .AXI4_TUSER_WIDTH(AXI4_TUSER_WIDTH), .NUM_LANES(NUM_LANES) ))
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function new (string name="hmc_tb", uvm_component parent=null);
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super.new(name,parent);
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endfunction : new
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virtual function void build_phase(uvm_phase phase);
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//-- factory overrides
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set_inst_override_by_type("axi4_req.master.sequencer",
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axi4_stream_master_sequencer #( .DATA_BYTES(AXI4_DATA_BYTES), .TUSER_WIDTH(AXI4_TUSER_WIDTH)
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)::get_type(),
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hmc_2_axi4_sequencer #( .DATA_BYTES(AXI4_DATA_BYTES),
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.TUSER_WIDTH(AXI4_TUSER_WIDTH)
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)::get_type()
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);
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set_inst_override_by_type("hmc_module.axi4_req_mon",
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hmc_module_mon::get_type(),
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axi4_stream_hmc_monitor #( .DATA_BYTES(AXI4_DATA_BYTES),
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.TUSER_WIDTH(AXI4_TUSER_WIDTH))::get_type()
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);
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set_inst_override_by_type("hmc_module.axi4_rsp_mon",
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hmc_module_mon::get_type(),
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axi4_stream_hmc_monitor #( .DATA_BYTES(AXI4_DATA_BYTES),
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.TUSER_WIDTH(AXI4_TUSER_WIDTH))::get_type()
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);
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super.build_phase(phase);
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//-- deploy configuration
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if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_req_config", axi4_req_config)) begin
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uvm_report_fatal(get_type_name(), $psprintf("axi4_config not set via config_db"));
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end else begin
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uvm_config_db#(axi4_stream_config)::set(this, "axi4_req", "axi4_stream_cfg", axi4_req_config);
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end
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if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_rsp_config", axi4_rsp_config)) begin
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uvm_report_fatal(get_type_name(), $psprintf("axi4_config not set via config_db"));
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end else begin
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uvm_config_db#(axi4_stream_config)::set(this, "axi4_rsp", "axi4_stream_cfg", axi4_rsp_config);
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end
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//hmc link uvc
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if (!uvm_config_db#(hmc_link_config)::get(this, "", "link_cfg", link_cfg)) begin
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uvm_report_fatal(get_type_name(), $psprintf("hmc_link_uvc_config not set via config_db"));
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end else begin
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uvm_config_db#(hmc_link_config)::set(this, "v_seqr", "link_cfg", link_cfg);
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uvm_config_db#(hmc_link_config)::set(this, "hmc", "link_config", link_cfg);
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end
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//-- create instances
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hmc = hmc_env #(.NUM_LANES(NUM_LANES))::type_id::create("hmc",this);
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axi4_req = axi4_stream_env #(.DATA_BYTES(AXI4_DATA_BYTES),.TUSER_WIDTH(AXI4_TUSER_WIDTH))::type_id::create("axi4_req",this);
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axi4_rsp = axi4_stream_env #(.DATA_BYTES(AXI4_DATA_BYTES),.TUSER_WIDTH(AXI4_TUSER_WIDTH))::type_id::create("axi4_rsp",this);
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hmc_module = hmc_module_env::type_id::create("hmc_module",this);
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rfs_hmc_I = cag_rgm_rfs_env #(.ADDR_WIDTH(`RFS_OPENHMC_RF_AWIDTH), .READ_DATA_WIDTH(`RFS_OPENHMC_RF_RWIDTH),.WRITE_DATA_WIDTH(`RFS_OPENHMC_RF_WWIDTH))::type_id::create("rfs_hmc_I", this);
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rf_model_hmc = rf_openhmc_rf_c::type_id::create("rf_model_hmc",this);
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v_seqr = vseqr::type_id::create("v_seqr", this);
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endfunction : build_phase
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function void connect_phase(uvm_phase phase);
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hmc_2_axi4_sequencer #(.DATA_BYTES(AXI4_DATA_BYTES),.TUSER_WIDTH(AXI4_TUSER_WIDTH)) axi4_req_seqr;
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axi4_stream_hmc_monitor #(.DATA_BYTES(AXI4_DATA_BYTES), .TUSER_WIDTH(AXI4_TUSER_WIDTH) ) axi4_hmc_req_mon;
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axi4_stream_hmc_monitor #(.DATA_BYTES(AXI4_DATA_BYTES), .TUSER_WIDTH(AXI4_TUSER_WIDTH) ) axi4_hmc_rsp_mon;
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super.connect_phase(phase);
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rfs_hmc_I.assign_vi(tb_top.rfs_hmc_if);
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rfs_hmc_I.set_rf(rf_model_hmc);
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//-- cast sequencer
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if ( !$cast(axi4_req_seqr, axi4_req.master.sequencer))
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`uvm_fatal(get_type_name(), $psprintf("error in seqr cast"));
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//-- cast AXI4 to HMC pkt monitors
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if ( !$cast(axi4_hmc_req_mon, hmc_module.axi4_req_mon))
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`uvm_fatal(get_type_name(), $psprintf("error in axi4_req_mon cast"));
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if ( !$cast(axi4_hmc_rsp_mon, hmc_module.axi4_rsp_mon))
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`uvm_fatal(get_type_name(), $psprintf("error in axi4_rsp_mon cast"));
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axi4_req.master.sequencer = axi4_req_seqr;
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//-- connect the AXI4 UVC UVM analysis ports to the corresponding Module UVC monitors
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axi4_req.monitor.item_collected_port.connect(axi4_hmc_req_mon.axi4_port);
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axi4_rsp.monitor.item_collected_port.connect(axi4_hmc_rsp_mon.axi4_port);
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//-- connect the AXi4 to HMC pkt response monitor to the tag handler
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axi4_hmc_rsp_mon.item_collected_port.connect(axi4_req_seqr.handler.hmc_rsp_port);
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//-- virtual sequencer
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v_seqr.axi4_req_seqr = axi4_req_seqr;
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v_seqr.rf_seqr_hmc = rfs_hmc_I.sequencer;
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//--hmc monitor to scb
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hmc.req_transaction_mon.transaction_finished_port.connect(hmc_module.scb.hmc_req_port); //--direkt
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hmc.rsp_transaction_mon.transaction_finished_port.connect(hmc_module.scb.hmc_rsp_port);
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v_seqr.scb = hmc_module.scb;
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endfunction : connect_phase
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function void extract_phase(uvm_phase phase);
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link_cfg.responder.config_cg.sample();
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endfunction : extract_phase
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endclass : hmc_tb
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`endif // hmc_TB_SV
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