URL https://opencores.org/ocsvn/openjtag-project/openjtag-project/trunk

Subversion Repositories openjtag-project

[/] [openjtag-project/] [trunk/] [OpenJTAG/] [Quartus_II/] [db/] [Open_JTAG.hier_info] - Blame information for rev 18

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|Open_JTAG
tms <= inst4.DB_MAX_OUTPUT_PORT_TYPE
clk => clock_mux:inst1.clk
txe => serializer:inst2.txe
rxf => serializer:inst2.rxf
rst => serializer:inst2.rst
rst => tap_sm:inst.rst
tdo => serializer:inst2.tdo
db[0] <> serializer:inst2.db[0]
db[1] <> serializer:inst2.db[1]
db[2] <> serializer:inst2.db[2]
db[3] <> serializer:inst2.db[3]
db[4] <> serializer:inst2.db[4]
db[5] <> serializer:inst2.db[5]
db[6] <> serializer:inst2.db[6]
db[7] <> serializer:inst2.db[7]
tck <= inst3.DB_MAX_OUTPUT_PORT_TYPE
wrk <= tap_sm:inst.wrk
wr <= serializer:inst2.wr
rd <= serializer:inst2.rd
tdi <= serializer:inst2.tdi
trst <= serializer:inst2.trst
wcks <= clock_mux:inst1.wcks
new_state[0] <= serializer:inst2.new_state[0]
new_state[1] <= serializer:inst2.new_state[1]
new_state[2] <= serializer:inst2.new_state[2]
new_state[3] <= serializer:inst2.new_state[3]
sm[0] <= tap_sm:inst.sm[0]
sm[1] <= tap_sm:inst.sm[1]
sm[2] <= tap_sm:inst.sm[2]
sm[3] <= tap_sm:inst.sm[3]
 
 
|Open_JTAG|tap_sm:inst
clk => state[0].CLK
clk => state[1].CLK
clk => state[2].CLK
clk => state[3].CLK
clk => tck~reg0.CLK
clk => tms~reg0.CLK
clk => wrk~reg0.CLK
clk => sm[0]~reg0.CLK
clk => sm[1]~reg0.CLK
clk => sm[2]~reg0.CLK
clk => sm[3]~reg0.CLK
clk => astate[0].CLK
clk => astate[1].CLK
clk => astate[2].CLK
clk => astate[3].CLK
clk => rclk.CLK
rst => ~NO_FANOUT~
new_state[0] => astate[0].DATAIN
new_state[1] => astate[1].DATAIN
new_state[2] => astate[2].DATAIN
new_state[3] => astate[3].DATAIN
tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE
tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE
wrk <= wrk~reg0.DB_MAX_OUTPUT_PORT_TYPE
sm[0] <= sm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sm[1] <= sm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sm[2] <= sm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sm[3] <= sm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 
 
|Open_JTAG|clock_mux:inst1
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => cclk[0].CLK
clk => cclk[1].CLK
clk => cclk[2].CLK
clk => cclk[3].CLK
clk => cclk[4].CLK
clk => cclk[5].CLK
clk => cclk[6].CLK
clk => wcks~reg0.CLK
clk => wcks~reg0.ADATA
cks[0] => Add0.IN6
cks[0] => Equal0.IN2
cks[1] => Add0.IN5
cks[1] => Equal0.IN1
cks[2] => Add0.IN4
cks[2] => Equal0.IN0
wcks <= wcks~reg0.DB_MAX_OUTPUT_PORT_TYPE
 
 
|Open_JTAG|serializer:inst2
clk => trst~reg0.CLK
clk => state[0].CLK
clk => state[1].CLK
clk => state[2].CLK
clk => state[3].CLK
clk => wr~reg0.CLK
clk => shift[0].CLK
clk => shift[1].CLK
clk => shift[2].CLK
clk => shift[3].CLK
clk => shift[4].CLK
clk => shift[5].CLK
clk => shift[6].CLK
clk => shift[7].CLK
clk => instr.CLK
clk => rtms.CLK
clk => sclk.CLK
clk => dir.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => new_state[0]~reg0.CLK
clk => new_state[1]~reg0.CLK
clk => new_state[2]~reg0.CLK
clk => new_state[3]~reg0.CLK
clk => cks[0]~reg0.CLK
clk => cks[1]~reg0.CLK
clk => cks[2]~reg0.CLK
clk => db[0]~reg0.CLK
clk => db[0]~en.CLK
clk => db[1]~reg0.CLK
clk => db[1]~en.CLK
clk => db[2]~reg0.CLK
clk => db[2]~en.CLK
clk => db[3]~reg0.CLK
clk => db[3]~en.CLK
clk => db[4]~reg0.CLK
clk => db[4]~en.CLK
clk => db[5]~reg0.CLK
clk => db[5]~en.CLK
clk => db[6]~reg0.CLK
clk => db[6]~en.CLK
clk => db[7]~reg0.CLK
clk => db[7]~en.CLK
clk => rbyte[0].CLK
clk => rbyte[1].CLK
clk => rbyte[2].CLK
clk => rbyte[3].CLK
clk => rbyte[4].CLK
clk => rbyte[5].CLK
clk => rbyte[6].CLK
clk => rbyte[7].CLK
clk => ssm[0].CLK
clk => ssm[1].CLK
clk => ssm[2].CLK
clk => ssm[3].CLK
clk => rd~reg0.CLK
clk => tdi~reg0.CLK
clk => tms~reg0.CLK
clk => tck~reg0.CLK
txe => ssm.OUTPUTSELECT
txe => ssm.OUTPUTSELECT
txe => ssm.OUTPUTSELECT
txe => ssm.OUTPUTSELECT
txe => Mux78.IN15
rxf => rd.OUTPUTSELECT
rxf => ssm.OUTPUTSELECT
rxf => ssm.OUTPUTSELECT
rxf => ssm.OUTPUTSELECT
rxf => ssm.OUTPUTSELECT
pwr => ~NO_FANOUT~
rst => ~NO_FANOUT~
wrk => db[7].IN1
wrk => state[0].ENA
wrk => trst~reg0.ENA
wrk => rbyte[0].ENA
wrk => state[1].ENA
wrk => state[2].ENA
wrk => state[3].ENA
wrk => wr~reg0.ENA
wrk => shift[0].ENA
wrk => shift[1].ENA
wrk => shift[2].ENA
wrk => shift[3].ENA
wrk => shift[4].ENA
wrk => shift[5].ENA
wrk => shift[6].ENA
wrk => shift[7].ENA
wrk => instr.ENA
wrk => rtms.ENA
wrk => sclk.ENA
wrk => dir.ENA
wrk => count[0].ENA
wrk => count[1].ENA
wrk => count[2].ENA
wrk => count[3].ENA
wrk => new_state[0]~reg0.ENA
wrk => new_state[1]~reg0.ENA
wrk => new_state[2]~reg0.ENA
wrk => new_state[3]~reg0.ENA
wrk => cks[0]~reg0.ENA
wrk => cks[1]~reg0.ENA
wrk => cks[2]~reg0.ENA
wrk => rbyte[1].ENA
wrk => rbyte[2].ENA
wrk => rbyte[3].ENA
wrk => rbyte[4].ENA
wrk => rbyte[5].ENA
wrk => rbyte[6].ENA
wrk => rbyte[7].ENA
wrk => ssm[0].ENA
wrk => ssm[1].ENA
wrk => ssm[2].ENA
wrk => ssm[3].ENA
wrk => rd~reg0.ENA
wrk => tdi~reg0.ENA
wrk => tms~reg0.ENA
wrk => tck~reg0.ENA
wr <= wr~reg0.DB_MAX_OUTPUT_PORT_TYPE
rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
siwu <= 
db[0] <> db[0]
db[1] <> db[1]
db[2] <> db[2]
db[3] <> db[3]
db[4] <> db[4]
db[5] <> db[5]
db[6] <> db[6]
db[7] <> db[7]
tdo => shift.DATAB
tdo => shift.DATAA
tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE
tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE
tdi <= tdi~reg0.DB_MAX_OUTPUT_PORT_TYPE
trst <= trst~reg0.DB_MAX_OUTPUT_PORT_TYPE
new_state[0] <= new_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
new_state[1] <= new_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
new_state[2] <= new_state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
new_state[3] <= new_state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cks[0] <= cks[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cks[1] <= cks[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cks[2] <= cks[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
 
 

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Subversion Repositories openjtag-project

[/] [openjtag-project/] [trunk/] [OpenJTAG/] [Quartus_II/] [db/] [Open_JTAG.hier_info] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	rmileca	`\|Open_JTAG`
2			`tms <= inst4.DB_MAX_OUTPUT_PORT_TYPE`
3			`clk => clock_mux:inst1.clk`
4			`txe => serializer:inst2.txe`
5			`rxf => serializer:inst2.rxf`
6			`rst => serializer:inst2.rst`
7			`rst => tap_sm:inst.rst`
8			`tdo => serializer:inst2.tdo`
9			`db[0] <> serializer:inst2.db[0]`
10			`db[1] <> serializer:inst2.db[1]`
11			`db[2] <> serializer:inst2.db[2]`
12			`db[3] <> serializer:inst2.db[3]`
13			`db[4] <> serializer:inst2.db[4]`
14			`db[5] <> serializer:inst2.db[5]`
15			`db[6] <> serializer:inst2.db[6]`
16			`db[7] <> serializer:inst2.db[7]`
17			`tck <= inst3.DB_MAX_OUTPUT_PORT_TYPE`
18			`wrk <= tap_sm:inst.wrk`
19			`wr <= serializer:inst2.wr`
20			`rd <= serializer:inst2.rd`
21			`tdi <= serializer:inst2.tdi`
22			`trst <= serializer:inst2.trst`
23			`wcks <= clock_mux:inst1.wcks`
24			`new_state[0] <= serializer:inst2.new_state[0]`
25			`new_state[1] <= serializer:inst2.new_state[1]`
26			`new_state[2] <= serializer:inst2.new_state[2]`
27			`new_state[3] <= serializer:inst2.new_state[3]`
28			`sm[0] <= tap_sm:inst.sm[0]`
29			`sm[1] <= tap_sm:inst.sm[1]`
30			`sm[2] <= tap_sm:inst.sm[2]`
31			`sm[3] <= tap_sm:inst.sm[3]`
32
33
34			`\|Open_JTAG\|tap_sm:inst`
35			`clk => state[0].CLK`
36			`clk => state[1].CLK`
37			`clk => state[2].CLK`
38			`clk => state[3].CLK`
39			`clk => tck~reg0.CLK`
40			`clk => tms~reg0.CLK`
41			`clk => wrk~reg0.CLK`
42			`clk => sm[0]~reg0.CLK`
43			`clk => sm[1]~reg0.CLK`
44			`clk => sm[2]~reg0.CLK`
45			`clk => sm[3]~reg0.CLK`
46			`clk => astate[0].CLK`
47			`clk => astate[1].CLK`
48			`clk => astate[2].CLK`
49			`clk => astate[3].CLK`
50			`clk => rclk.CLK`
51			`rst => ~NO_FANOUT~`
52			`new_state[0] => astate[0].DATAIN`
53			`new_state[1] => astate[1].DATAIN`
54			`new_state[2] => astate[2].DATAIN`
55			`new_state[3] => astate[3].DATAIN`
56			`tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE`
57			`tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE`
58			`wrk <= wrk~reg0.DB_MAX_OUTPUT_PORT_TYPE`
59			`sm[0] <= sm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
60			`sm[1] <= sm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
61			`sm[2] <= sm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
62			`sm[3] <= sm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
63
64
65			`\|Open_JTAG\|clock_mux:inst1`
66			`clk => count[0].CLK`
67			`clk => count[1].CLK`
68			`clk => count[2].CLK`
69			`clk => count[3].CLK`
70			`clk => count[4].CLK`
71			`clk => count[5].CLK`
72			`clk => count[6].CLK`
73			`clk => cclk[0].CLK`
74			`clk => cclk[1].CLK`
75			`clk => cclk[2].CLK`
76			`clk => cclk[3].CLK`
77			`clk => cclk[4].CLK`
78			`clk => cclk[5].CLK`
79			`clk => cclk[6].CLK`
80			`clk => wcks~reg0.CLK`
81			`clk => wcks~reg0.ADATA`
82			`cks[0] => Add0.IN6`
83			`cks[0] => Equal0.IN2`
84			`cks[1] => Add0.IN5`
85			`cks[1] => Equal0.IN1`
86			`cks[2] => Add0.IN4`
87			`cks[2] => Equal0.IN0`
88			`wcks <= wcks~reg0.DB_MAX_OUTPUT_PORT_TYPE`
89
90
91			`\|Open_JTAG\|serializer:inst2`
92			`clk => trst~reg0.CLK`
93			`clk => state[0].CLK`
94			`clk => state[1].CLK`
95			`clk => state[2].CLK`
96			`clk => state[3].CLK`
97			`clk => wr~reg0.CLK`
98			`clk => shift[0].CLK`
99			`clk => shift[1].CLK`
100			`clk => shift[2].CLK`
101			`clk => shift[3].CLK`
102			`clk => shift[4].CLK`
103			`clk => shift[5].CLK`
104			`clk => shift[6].CLK`
105			`clk => shift[7].CLK`
106			`clk => instr.CLK`
107			`clk => rtms.CLK`
108			`clk => sclk.CLK`
109			`clk => dir.CLK`
110			`clk => count[0].CLK`
111			`clk => count[1].CLK`
112			`clk => count[2].CLK`
113			`clk => count[3].CLK`
114			`clk => new_state[0]~reg0.CLK`
115			`clk => new_state[1]~reg0.CLK`
116			`clk => new_state[2]~reg0.CLK`
117			`clk => new_state[3]~reg0.CLK`
118			`clk => cks[0]~reg0.CLK`
119			`clk => cks[1]~reg0.CLK`
120			`clk => cks[2]~reg0.CLK`
121			`clk => db[0]~reg0.CLK`
122			`clk => db[0]~en.CLK`
123			`clk => db[1]~reg0.CLK`
124			`clk => db[1]~en.CLK`
125			`clk => db[2]~reg0.CLK`
126			`clk => db[2]~en.CLK`
127			`clk => db[3]~reg0.CLK`
128			`clk => db[3]~en.CLK`
129			`clk => db[4]~reg0.CLK`
130			`clk => db[4]~en.CLK`
131			`clk => db[5]~reg0.CLK`
132			`clk => db[5]~en.CLK`
133			`clk => db[6]~reg0.CLK`
134			`clk => db[6]~en.CLK`
135			`clk => db[7]~reg0.CLK`
136			`clk => db[7]~en.CLK`
137			`clk => rbyte[0].CLK`
138			`clk => rbyte[1].CLK`
139			`clk => rbyte[2].CLK`
140			`clk => rbyte[3].CLK`
141			`clk => rbyte[4].CLK`
142			`clk => rbyte[5].CLK`
143			`clk => rbyte[6].CLK`
144			`clk => rbyte[7].CLK`
145			`clk => ssm[0].CLK`
146			`clk => ssm[1].CLK`
147			`clk => ssm[2].CLK`
148			`clk => ssm[3].CLK`
149			`clk => rd~reg0.CLK`
150			`clk => tdi~reg0.CLK`
151			`clk => tms~reg0.CLK`
152			`clk => tck~reg0.CLK`
153			`txe => ssm.OUTPUTSELECT`
154			`txe => ssm.OUTPUTSELECT`
155			`txe => ssm.OUTPUTSELECT`
156			`txe => ssm.OUTPUTSELECT`
157			`txe => Mux78.IN15`
158			`rxf => rd.OUTPUTSELECT`
159			`rxf => ssm.OUTPUTSELECT`
160			`rxf => ssm.OUTPUTSELECT`
161			`rxf => ssm.OUTPUTSELECT`
162			`rxf => ssm.OUTPUTSELECT`
163			`pwr => ~NO_FANOUT~`
164			`rst => ~NO_FANOUT~`
165			`wrk => db[7].IN1`
166			`wrk => state[0].ENA`
167			`wrk => trst~reg0.ENA`
168			`wrk => rbyte[0].ENA`
169			`wrk => state[1].ENA`
170			`wrk => state[2].ENA`
171			`wrk => state[3].ENA`
172			`wrk => wr~reg0.ENA`
173			`wrk => shift[0].ENA`
174			`wrk => shift[1].ENA`
175			`wrk => shift[2].ENA`
176			`wrk => shift[3].ENA`
177			`wrk => shift[4].ENA`
178			`wrk => shift[5].ENA`
179			`wrk => shift[6].ENA`
180			`wrk => shift[7].ENA`
181			`wrk => instr.ENA`
182			`wrk => rtms.ENA`
183			`wrk => sclk.ENA`
184			`wrk => dir.ENA`
185			`wrk => count[0].ENA`
186			`wrk => count[1].ENA`
187			`wrk => count[2].ENA`
188			`wrk => count[3].ENA`
189			`wrk => new_state[0]~reg0.ENA`
190			`wrk => new_state[1]~reg0.ENA`
191			`wrk => new_state[2]~reg0.ENA`
192			`wrk => new_state[3]~reg0.ENA`
193			`wrk => cks[0]~reg0.ENA`
194			`wrk => cks[1]~reg0.ENA`
195			`wrk => cks[2]~reg0.ENA`
196			`wrk => rbyte[1].ENA`
197			`wrk => rbyte[2].ENA`
198			`wrk => rbyte[3].ENA`
199			`wrk => rbyte[4].ENA`
200			`wrk => rbyte[5].ENA`
201			`wrk => rbyte[6].ENA`
202			`wrk => rbyte[7].ENA`
203			`wrk => ssm[0].ENA`
204			`wrk => ssm[1].ENA`
205			`wrk => ssm[2].ENA`
206			`wrk => ssm[3].ENA`
207			`wrk => rd~reg0.ENA`
208			`wrk => tdi~reg0.ENA`
209			`wrk => tms~reg0.ENA`
210			`wrk => tck~reg0.ENA`
211			`wr <= wr~reg0.DB_MAX_OUTPUT_PORT_TYPE`
212			`rd <= rd~reg0.DB_MAX_OUTPUT_PORT_TYPE`
213			`siwu <=`
214			`db[0] <> db[0]`
215			`db[1] <> db[1]`
216			`db[2] <> db[2]`
217			`db[3] <> db[3]`
218			`db[4] <> db[4]`
219			`db[5] <> db[5]`
220			`db[6] <> db[6]`
221			`db[7] <> db[7]`
222			`tdo => shift.DATAB`
223			`tdo => shift.DATAA`
224			`tck <= tck~reg0.DB_MAX_OUTPUT_PORT_TYPE`
225			`tms <= tms~reg0.DB_MAX_OUTPUT_PORT_TYPE`
226			`tdi <= tdi~reg0.DB_MAX_OUTPUT_PORT_TYPE`
227			`trst <= trst~reg0.DB_MAX_OUTPUT_PORT_TYPE`
228			`new_state[0] <= new_state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
229			`new_state[1] <= new_state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
230			`new_state[2] <= new_state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
231			`new_state[3] <= new_state[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
232			`cks[0] <= cks[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
233			`cks[1] <= cks[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
234			`cks[2] <= cks[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE`
235
236