Subversion Repositories openjtag-project

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 02 16:01:14 2010 " "Info: Processing started: Wed Jun 02 16:01:14 2010" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Open_JTAG -c Open_JTAG" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_mux:inst1\|wcks " "Info: Detected ripple clock \"clock_mux:inst1\|wcks\" as buffer" {  } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } } { "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/91sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock_mux:inst1\|wcks" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register serializer:inst2\|cks\[0\] register clock_mux:inst1\|wcks 78.31 MHz 12.77 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.31 MHz between source register \"serializer:inst2\|cks\[0\]\" and destination register \"clock_mux:inst1\|wcks\" (period= 12.77 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.481 ns + Longest register register " "Info: + Longest register to register delay is 6.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serializer:inst2\|cks\[0\] 1 REG LC_X7_Y5_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2\|cks\[0\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { serializer:inst2|cks[0] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.558 ns) + CELL(0.740 ns) 3.298 ns clock_mux:inst1\|Mux0~3 2 COMB LC_X9_Y5_N8 1 " "Info: 2: + IC(2.558 ns) + CELL(0.740 ns) = 3.298 ns; Loc. = LC_X9_Y5_N8; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~3'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.298 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.803 ns clock_mux:inst1\|Mux0~4 3 COMB LC_X9_Y5_N9 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.803 ns; Loc. = LC_X9_Y5_N9; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~4'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.200 ns) 4.732 ns clock_mux:inst1\|Mux0~2 4 COMB LC_X9_Y5_N7 1 " "Info: 4: + IC(0.729 ns) + CELL(0.200 ns) = 4.732 ns; Loc. = LC_X9_Y5_N7; Fanout = 1; COMB Node = 'clock_mux:inst1\|Mux0~2'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.929 ns" { clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.591 ns) 6.481 ns clock_mux:inst1\|wcks 5 REG LC_X8_Y5_N5 75 " "Info: 5: + IC(1.158 ns) + CELL(0.591 ns) = 6.481 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.749 ns" { clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.731 ns ( 26.71 % ) " "Info: Total cell delay = 1.731 ns ( 26.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.750 ns ( 73.29 % ) " "Info: Total interconnect delay = 4.750 ns ( 73.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.481 ns" { serializer:inst2|cks[0] {} clock_mux:inst1|Mux0~3 {} clock_mux:inst1|Mux0~4 {} clock_mux:inst1|Mux0~2 {} clock_mux:inst1|wcks {} } { 0.000ns 2.558ns 0.305ns 0.729ns 1.158ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.580 ns - Smallest " "Info: - Smallest clock skew is -5.580 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.261 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|cks\[0\] 3 REG LC_X7_Y5_N5 5 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y5_N5; Fanout = 5; REG Node = 'serializer:inst2\|cks\[0\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.481 ns" { serializer:inst2|cks[0] clock_mux:inst1|Mux0~3 clock_mux:inst1|Mux0~4 clock_mux:inst1|Mux0~2 clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.481 ns" { serializer:inst2|cks[0] {} clock_mux:inst1|Mux0~3 {} clock_mux:inst1|Mux0~4 {} clock_mux:inst1|Mux0~2 {} clock_mux:inst1|wcks {} } { 0.000ns 2.558ns 0.305ns 0.729ns 1.158ns } { 0.000ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|cks[0] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|cks[0] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}

{ "Info" "ITDB_TSU_RESULT" "serializer:inst2\|ssm\[2\] txe clk 1.440 ns register " "Info: tsu for register \"serializer:inst2\|ssm\[2\]\" (data pin = \"txe\", clock pin = \"clk\") is 1.440 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.368 ns + Longest pin register " "Info: + Longest pin to register delay is 10.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns txe 1 PIN PIN_38 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 3; PIN Node = 'txe'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { txe } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 304 48 216 320 "txe" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.540 ns) + CELL(0.200 ns) 5.872 ns serializer:inst2\|ssm\[2\]~0 2 COMB LC_X5_Y7_N9 1 " "Info: 2: + IC(4.540 ns) + CELL(0.200 ns) = 5.872 ns; Loc. = LC_X5_Y7_N9; Fanout = 1; COMB Node = 'serializer:inst2\|ssm\[2\]~0'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.740 ns" { txe serializer:inst2|ssm[2]~0 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.200 ns) 6.783 ns serializer:inst2\|ssm\[2\]~1 3 COMB LC_X5_Y7_N6 1 " "Info: 3: + IC(0.711 ns) + CELL(0.200 ns) = 6.783 ns; Loc. = LC_X5_Y7_N6; Fanout = 1; COMB Node = 'serializer:inst2\|ssm\[2\]~1'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.911 ns" { serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.789 ns) + CELL(0.511 ns) 8.083 ns serializer:inst2\|ssm\[2\]~7 4 COMB LC_X5_Y7_N3 2 " "Info: 4: + IC(0.789 ns) + CELL(0.511 ns) = 8.083 ns; Loc. = LC_X5_Y7_N3; Fanout = 2; COMB Node = 'serializer:inst2\|ssm\[2\]~7'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.200 ns) 9.024 ns serializer:inst2\|ssm\[0\]~9 5 COMB LC_X5_Y7_N8 2 " "Info: 5: + IC(0.741 ns) + CELL(0.200 ns) = 9.024 ns; Loc. = LC_X5_Y7_N8; Fanout = 2; COMB Node = 'serializer:inst2\|ssm\[0\]~9'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.941 ns" { serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.591 ns) 10.368 ns serializer:inst2\|ssm\[2\] 6 REG LC_X5_Y7_N0 20 " "Info: 6: + IC(0.753 ns) + CELL(0.591 ns) = 10.368 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2\|ssm\[2\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.344 ns" { serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.834 ns ( 27.33 % ) " "Info: Total cell delay = 2.834 ns ( 27.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.534 ns ( 72.67 % ) " "Info: Total interconnect delay = 7.534 ns ( 72.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.368 ns" { txe serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "10.368 ns" { txe {} txe~combout {} serializer:inst2|ssm[2]~0 {} serializer:inst2|ssm[2]~1 {} serializer:inst2|ssm[2]~7 {} serializer:inst2|ssm[0]~9 {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 4.540ns 0.711ns 0.789ns 0.741ns 0.753ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.261 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|ssm\[2\] 3 REG LC_X5_Y7_N0 20 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X5_Y7_N0; Fanout = 20; REG Node = 'serializer:inst2\|ssm\[2\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.368 ns" { txe serializer:inst2|ssm[2]~0 serializer:inst2|ssm[2]~1 serializer:inst2|ssm[2]~7 serializer:inst2|ssm[0]~9 serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "10.368 ns" { txe {} txe~combout {} serializer:inst2|ssm[2]~0 {} serializer:inst2|ssm[2]~1 {} serializer:inst2|ssm[2]~7 {} serializer:inst2|ssm[0]~9 {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 4.540ns 0.711ns 0.789ns 0.741ns 0.753ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|ssm[2] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|ssm[2] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}

{ "Info" "ITDB_FULL_TCO_RESULT" "clk tms tap_sm:inst\|tms 15.899 ns register " "Info: tco from clock \"clk\" to destination pin \"tms\" through register \"tap_sm:inst\|tms\" is 15.899 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns tap_sm:inst\|tms 3 REG LC_X9_Y7_N7 5 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst\|tms'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} tap_sm:inst|tms {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.262 ns + Longest register pin " "Info: + Longest register to pin delay is 6.262 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tap_sm:inst\|tms 1 REG LC_X9_Y7_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N7; Fanout = 5; REG Node = 'tap_sm:inst\|tms'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tap_sm:inst|tms } "NODE_NAME" } } { "tap_sm.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/tap_sm.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.966 ns) + CELL(0.511 ns) 1.477 ns inst4 2 COMB LC_X9_Y7_N1 1 " "Info: 2: + IC(0.966 ns) + CELL(0.511 ns) = 1.477 ns; Loc. = LC_X9_Y7_N1; Fanout = 1; COMB Node = 'inst4'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { tap_sm:inst|tms inst4 } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 200 592 656 248 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.463 ns) + CELL(2.322 ns) 6.262 ns tms 3 PIN PIN_87 0 " "Info: 3: + IC(2.463 ns) + CELL(2.322 ns) = 6.262 ns; Loc. = PIN_87; Fanout = 0; PIN Node = 'tms'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.785 ns" { inst4 tms } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 216 680 856 232 "tms" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.833 ns ( 45.24 % ) " "Info: Total cell delay = 2.833 ns ( 45.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.429 ns ( 54.76 % ) " "Info: Total interconnect delay = 3.429 ns ( 54.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.262 ns" { tap_sm:inst|tms inst4 tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.262 ns" { tap_sm:inst|tms {} inst4 {} tms {} } { 0.000ns 0.966ns 2.463ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks tap_sm:inst|tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} tap_sm:inst|tms {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.262 ns" { tap_sm:inst|tms inst4 tms } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "6.262 ns" { tap_sm:inst|tms {} inst4 {} tms {} } { 0.000ns 0.966ns 2.463ns } { 0.000ns 0.511ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}

{ "Info" "ITDB_TH_RESULT" "serializer:inst2\|rbyte\[6\] db\[6\] clk 4.193 ns register " "Info: th for register \"serializer:inst2\|rbyte\[6\]\" (data pin = \"db\[6\]\", clock pin = \"clk\") is 4.193 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.261 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 15 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 560 288 456 576 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns clock_mux:inst1\|wcks 2 REG LC_X8_Y5_N5 75 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X8_Y5_N5; Fanout = 75; REG Node = 'clock_mux:inst1\|wcks'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clk clock_mux:inst1|wcks } "NODE_NAME" } } { "clock_mux.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/clock_mux.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.286 ns) + CELL(0.918 ns) 9.261 ns serializer:inst2\|rbyte\[6\] 3 REG LC_X7_Y7_N3 7 " "Info: 3: + IC(4.286 ns) + CELL(0.918 ns) = 9.261 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2\|rbyte\[6\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.204 ns" { clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 36.44 % ) " "Info: Total cell delay = 3.375 ns ( 36.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.886 ns ( 63.56 % ) " "Info: Total interconnect delay = 5.886 ns ( 63.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.289 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns db\[6\] 1 PIN PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_34; Fanout = 1; PIN Node = 'db\[6\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { db[6] } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns db~1 2 COMB IOC_X6_Y3_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X6_Y3_N2; Fanout = 1; COMB Node = 'db~1'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { db[6] db~1 } "NODE_NAME" } } { "Open_JTAG.bdf" "" { Schematic "C:/AlteraWorks/91/Open JTAG/Open_JTAG.bdf" { { 336 680 856 352 "db\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.877 ns) + CELL(0.280 ns) 5.289 ns serializer:inst2\|rbyte\[6\] 3 REG LC_X7_Y7_N3 7 " "Info: 3: + IC(3.877 ns) + CELL(0.280 ns) = 5.289 ns; Loc. = LC_X7_Y7_N3; Fanout = 7; REG Node = 'serializer:inst2\|rbyte\[6\]'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.157 ns" { db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "serializer.vhd" "" { Text "C:/AlteraWorks/91/Open JTAG/serializer.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 26.70 % ) " "Info: Total cell delay = 1.412 ns ( 26.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.877 ns ( 73.30 % ) " "Info: Total interconnect delay = 3.877 ns ( 73.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.289 ns" { db[6] db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "5.289 ns" { db[6] {} db~1 {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 3.877ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.261 ns" { clk clock_mux:inst1|wcks serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "9.261 ns" { clk {} clk~combout {} clock_mux:inst1|wcks {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 1.600ns 4.286ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.289 ns" { db[6] db~1 serializer:inst2|rbyte[6] } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "5.289 ns" { db[6] {} db~1 {} serializer:inst2|rbyte[6] {} } { 0.000ns 0.000ns 3.877ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}

{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 02 16:01:15 2010 " "Info: Processing ended: Wed Jun 02 16:01:15 2010" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}