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olivier.gi |
//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: msp_debug.v
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//
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// *Module Description:
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// MSP430 core debug utility signals
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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`timescale 1ns / 100ps
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module msp_debug (
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// OUTPUTs
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e_state, // Execution state
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i_state, // Instruction fetch state
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inst_cycle, // Cycle number within current instruction
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inst_full, // Currently executed instruction (full version)
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inst_number, // Instruction number since last system reset
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inst_pc, // Instruction Program counter
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inst_short, // Currently executed instruction (short version)
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// INPUTs
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mclk, // Main system clock
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puc // Main system reset
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);
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// OUTPUTs
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//============
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output [8*32-1:0] e_state; // Execution state
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output [8*32-1:0] i_state; // Instruction fetch state
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output [31:0] inst_cycle; // Cycle number within current instruction
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output [8*32-1:0] inst_full; // Currently executed instruction (full version)
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output [31:0] inst_number; // Instruction number since last system reset
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output [15:0] inst_pc; // Instruction Program counter
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output [8*32-1:0] inst_short; // Currently executed instruction (short version)
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// INPUTs
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//============
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input mclk; // Main system clock
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input puc; // Main system reset
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//=============================================================================
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// 1) ASCII FORMATING FUNCTIONS
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//=============================================================================
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// This function simply concatenates two strings together, ignorning the NULL
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// at the end of string2.
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// The specified number of space will be inserted between string1 and string2
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function [64*8-1:0] myFormat;
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input [32*8-1:0] string1;
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input [32*8-1:0] string2;
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input [3:0] space;
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integer i,j;
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begin
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myFormat = 0;
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j = 0;
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for ( i=0; i < 32; i=i+1) // Copy string2
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begin
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myFormat[8*i +: 8] = string2[8*i +: 8];
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if ((string2[8*i +: 8] == 0) && (j == 0)) j=i;
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end
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for ( i=0; i < space; i=i+1) // Add spaces
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myFormat[8*(j+i) +: 8] = " ";
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j=j+space;
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for ( i=0; i < 32; i=i+1) // Copy string1
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myFormat[8*(j+i) +: 8] = string1[8*i +: 8];
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end
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endfunction
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//=============================================================================
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// 2) CONNECTIONS TO MSP430 CORE INTERNALS
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//=============================================================================
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wire [2:0] i_state_bin = dut.frontend_0.i_state;
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wire [3:0] e_state_bin = dut.frontend_0.e_state;
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wire decode = dut.frontend_0.decode;
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wire [15:0] ir = dut.frontend_0.ir;
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wire irq_detect = dut.frontend_0.irq_detect;
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wire [3:0] irq_num = dut.frontend_0.irq_num;
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wire [15:0] pc = dut.frontend_0.pc;
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//=============================================================================
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// 3) GENERATE DEBUG SIGNALS
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//=============================================================================
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// Instruction fetch state
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//=========================
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reg [8*32-1:0] i_state;
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always @(i_state_bin)
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case(i_state_bin)
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3'h0 : i_state = "IRQ_FETCH";
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3'h1 : i_state = "IRQ_DONE";
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3'h2 : i_state = "DEC";
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3'h3 : i_state = "EXT1";
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3'h4 : i_state = "EXT2";
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3'h5 : i_state = "IDLE";
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default : i_state = "XXXXX";
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endcase
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// Execution state
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//=========================
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reg [8*32-1:0] e_state;
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always @(e_state_bin)
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case(e_state_bin)
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4'h0 : e_state = "IRQ_0";
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4'h1 : e_state = "IRQ_1";
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4'h2 : e_state = "IRQ_2";
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4'h3 : e_state = "IRQ_3";
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4'h4 : e_state = "IRQ_4";
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4'h5 : e_state = "SRC_AD";
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4'h6 : e_state = "SRC_RD";
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4'h7 : e_state = "SRC_WR";
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4'h8 : e_state = "DST_AD";
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4'h9 : e_state = "DST_RD";
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4'hA : e_state = "DST_WR";
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4'hB : e_state = "EXEC";
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4'hC : e_state = "JUMP";
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4'hD : e_state = "IDLE";
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default : e_state = "xxxx";
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endcase
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// Count instruction number & cycles
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//====================================
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reg [31:0] inst_number;
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always @(posedge mclk or posedge puc)
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if (puc) inst_number <= 0;
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else if (decode) inst_number <= inst_number+1;
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reg [31:0] inst_cycle;
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always @(posedge mclk or posedge puc)
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if (puc) inst_cycle <= 0;
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else if (decode) inst_cycle <= 0;
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else inst_cycle <= inst_cycle+1;
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// Decode instruction
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//====================================
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// Buffer opcode
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reg [15:0] opcode;
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always @(posedge mclk or posedge puc)
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if (puc) opcode <= 0;
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else if (decode) opcode <= ir;
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// Interrupts
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reg irq;
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always @(posedge mclk or posedge puc)
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if (puc) irq <= 1'b1;
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else if (decode) irq <= irq_detect;
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// Instruction type
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reg [8*32-1:0] inst_type;
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always @(opcode or irq)
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if (irq)
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inst_type = "IRQ";
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else
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case(opcode[15:13])
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3'b000 : inst_type = "SIG-OP";
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3'b001 : inst_type = "JUMP";
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default : inst_type = "TWO-OP";
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endcase
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// Instructions name
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reg [8*32-1:0] inst_name;
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always @(opcode or inst_type or irq_num)
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if (inst_type=="IRQ")
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case(irq_num[3:0])
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4'b0000 : inst_name = "IRQ 0";
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4'b0001 : inst_name = "IRQ 1";
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4'b0010 : inst_name = "IRQ 2";
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4'b0011 : inst_name = "IRQ 3";
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4'b0100 : inst_name = "IRQ 4";
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4'b0101 : inst_name = "IRQ 5";
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4'b0110 : inst_name = "IRQ 6";
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4'b0111 : inst_name = "IRQ 7";
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4'b1000 : inst_name = "IRQ 8";
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4'b1001 : inst_name = "IRQ 9";
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4'b1010 : inst_name = "IRQ 10";
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4'b1011 : inst_name = "IRQ 11";
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4'b1100 : inst_name = "IRQ 12";
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4'b1101 : inst_name = "IRQ 13";
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4'b1110 : inst_name = "NMI";
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default : inst_name = "RESET";
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endcase
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else if (inst_type=="SIG-OP")
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case(opcode[15:7])
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9'b000100_000 : inst_name = "RRC";
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9'b000100_001 : inst_name = "SWPB";
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9'b000100_010 : inst_name = "RRA";
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9'b000100_011 : inst_name = "SXT";
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9'b000100_100 : inst_name = "PUSH";
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9'b000100_101 : inst_name = "CALL";
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9'b000100_110 : inst_name = "RETI";
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default : inst_name = "xxxx";
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endcase
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else if (inst_type=="JUMP")
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case(opcode[15:10])
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6'b001_000 : inst_name = "JNE";
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6'b001_001 : inst_name = "JEQ";
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6'b001_010 : inst_name = "JNC";
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6'b001_011 : inst_name = "JC";
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6'b001_100 : inst_name = "JN";
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6'b001_101 : inst_name = "JGE";
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6'b001_110 : inst_name = "JL";
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6'b001_111 : inst_name = "JMP";
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default : inst_name = "xxxx";
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endcase
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else if (inst_type=="TWO-OP")
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case(opcode[15:12])
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4'b0100 : inst_name = "MOV";
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4'b0101 : inst_name = "ADD";
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4'b0110 : inst_name = "ADDC";
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4'b0111 : inst_name = "SUBC";
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4'b1000 : inst_name = "SUB";
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4'b1001 : inst_name = "CMP";
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4'b1010 : inst_name = "DADD";
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4'b1011 : inst_name = "BIT";
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4'b1100 : inst_name = "BIC";
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4'b1101 : inst_name = "BIS";
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4'b1110 : inst_name = "XOR";
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4'b1111 : inst_name = "AND";
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default : inst_name = "xxxx";
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endcase
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// Instructions byte/word mode
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reg [8*32-1:0] inst_bw;
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always @(opcode or inst_type)
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if (inst_type=="IRQ")
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inst_bw = "";
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else if (inst_type=="SIG-OP")
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inst_bw = opcode[6] ? ".B" : "";
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else if (inst_type=="JUMP")
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inst_bw = "";
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else if (inst_type=="TWO-OP")
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inst_bw = opcode[6] ? ".B" : "";
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| 277 |
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// Source register
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| 279 |
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reg [8*32-1:0] inst_src;
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wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8];
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| 282 |
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always @(src_reg or inst_type)
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| 283 |
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if (inst_type=="IRQ")
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inst_src = "";
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| 285 |
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else if (inst_type=="JUMP")
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| 286 |
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inst_src = "";
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| 287 |
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else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP"))
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| 288 |
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case(src_reg)
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4'b0000 : inst_src = "r0";
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| 290 |
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4'b0001 : inst_src = "r1";
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| 291 |
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4'b0010 : inst_src = "r2";
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| 292 |
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4'b0011 : inst_src = "r3";
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| 293 |
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4'b0100 : inst_src = "r4";
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| 294 |
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4'b0101 : inst_src = "r5";
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| 295 |
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4'b0110 : inst_src = "r6";
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| 296 |
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4'b0111 : inst_src = "r7";
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| 297 |
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4'b1000 : inst_src = "r8";
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| 298 |
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4'b1001 : inst_src = "r9";
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| 299 |
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4'b1010 : inst_src = "r10";
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| 300 |
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4'b1011 : inst_src = "r11";
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| 301 |
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4'b1100 : inst_src = "r12";
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| 302 |
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4'b1101 : inst_src = "r13";
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4'b1110 : inst_src = "r14";
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default : inst_src = "r15";
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endcase
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| 307 |
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// Destination register
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| 308 |
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reg [8*32-1:0] inst_dst;
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| 309 |
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always @(opcode or inst_type)
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| 310 |
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if (inst_type=="IRQ")
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| 311 |
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inst_dst = "";
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| 312 |
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else if (inst_type=="SIG-OP")
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| 313 |
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inst_dst = "";
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| 314 |
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else if (inst_type=="JUMP")
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| 315 |
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inst_dst = "";
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| 316 |
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else if (inst_type=="TWO-OP")
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case(opcode[3:0])
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4'b0000 : inst_dst = "r0";
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4'b0001 : inst_dst = "r1";
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| 320 |
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4'b0010 : inst_dst = "r2";
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4'b0011 : inst_dst = "r3";
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| 322 |
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4'b0100 : inst_dst = "r4";
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| 323 |
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4'b0101 : inst_dst = "r5";
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| 324 |
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4'b0110 : inst_dst = "r6";
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| 325 |
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4'b0111 : inst_dst = "r7";
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| 326 |
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4'b1000 : inst_dst = "r8";
|
| 327 |
|
|
4'b1001 : inst_dst = "r9";
|
| 328 |
|
|
4'b1010 : inst_dst = "r10";
|
| 329 |
|
|
4'b1011 : inst_dst = "r11";
|
| 330 |
|
|
4'b1100 : inst_dst = "r12";
|
| 331 |
|
|
4'b1101 : inst_dst = "r13";
|
| 332 |
|
|
4'b1110 : inst_dst = "r14";
|
| 333 |
|
|
default : inst_dst = "r15";
|
| 334 |
|
|
endcase
|
| 335 |
|
|
|
| 336 |
|
|
// Source Addressing mode
|
| 337 |
|
|
reg [8*32-1:0] inst_as;
|
| 338 |
|
|
always @(inst_type or src_reg or opcode or inst_src)
|
| 339 |
|
|
begin
|
| 340 |
|
|
if (inst_type=="IRQ")
|
| 341 |
|
|
inst_as = "";
|
| 342 |
|
|
else if (inst_type=="JUMP")
|
| 343 |
|
|
inst_as = "";
|
| 344 |
|
|
else if (src_reg==4'h3) // Addressing mode using R3
|
| 345 |
|
|
case (opcode[5:4])
|
| 346 |
|
|
2'b11 : inst_as = "#-1";
|
| 347 |
|
|
2'b10 : inst_as = "#2";
|
| 348 |
|
|
2'b01 : inst_as = "#1";
|
| 349 |
|
|
default: inst_as = "#0";
|
| 350 |
|
|
endcase
|
| 351 |
|
|
else if (src_reg==4'h2) // Addressing mode using R2
|
| 352 |
|
|
case (opcode[5:4])
|
| 353 |
|
|
2'b11 : inst_as = "#8";
|
| 354 |
|
|
2'b10 : inst_as = "#4";
|
| 355 |
|
|
2'b01 : inst_as = "&EDE";
|
| 356 |
|
|
default: inst_as = inst_src;
|
| 357 |
|
|
endcase
|
| 358 |
|
|
else if (src_reg==4'h0) // Addressing mode using R0
|
| 359 |
|
|
case (opcode[5:4])
|
| 360 |
|
|
2'b11 : inst_as = "#N";
|
| 361 |
|
|
2'b10 : inst_as = myFormat("@", inst_src, 0);
|
| 362 |
|
|
2'b01 : inst_as = "EDE";
|
| 363 |
|
|
default: inst_as = inst_src;
|
| 364 |
|
|
endcase
|
| 365 |
|
|
else // General Addressing mode
|
| 366 |
|
|
case (opcode[5:4])
|
| 367 |
|
|
2'b11 : begin
|
| 368 |
|
|
inst_as = myFormat("@", inst_src, 0);
|
| 369 |
|
|
inst_as = myFormat(inst_as, "+", 0);
|
| 370 |
|
|
end
|
| 371 |
|
|
2'b10 : inst_as = myFormat("@", inst_src, 0);
|
| 372 |
|
|
2'b01 : begin
|
| 373 |
|
|
inst_as = myFormat("x(", inst_src, 0);
|
| 374 |
|
|
inst_as = myFormat(inst_as, ")", 0);
|
| 375 |
|
|
end
|
| 376 |
|
|
default: inst_as = inst_src;
|
| 377 |
|
|
endcase
|
| 378 |
|
|
end
|
| 379 |
|
|
|
| 380 |
|
|
// Destination Addressing mode
|
| 381 |
|
|
reg [8*32-1:0] inst_ad;
|
| 382 |
|
|
always @(opcode or inst_type or inst_dst)
|
| 383 |
|
|
begin
|
| 384 |
|
|
if (inst_type!="TWO-OP")
|
| 385 |
|
|
inst_ad = "";
|
| 386 |
|
|
else if (opcode[3:0]==4'h2) // Addressing mode using R2
|
| 387 |
|
|
case (opcode[7])
|
| 388 |
|
|
1'b1 : inst_ad = "&EDE";
|
| 389 |
|
|
default: inst_ad = inst_dst;
|
| 390 |
|
|
endcase
|
| 391 |
|
|
else if (opcode[3:0]==4'h0) // Addressing mode using R0
|
| 392 |
|
|
case (opcode[7])
|
| 393 |
|
|
2'b1 : inst_ad = "EDE";
|
| 394 |
|
|
default: inst_ad = inst_dst;
|
| 395 |
|
|
endcase
|
| 396 |
|
|
else // General Addressing mode
|
| 397 |
|
|
case (opcode[7])
|
| 398 |
|
|
2'b1 : begin
|
| 399 |
|
|
inst_ad = myFormat("x(", inst_dst, 0);
|
| 400 |
|
|
inst_ad = myFormat(inst_ad, ")", 0);
|
| 401 |
|
|
end
|
| 402 |
|
|
default: inst_ad = inst_dst;
|
| 403 |
|
|
endcase
|
| 404 |
|
|
end
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
// Currently executed instruction
|
| 408 |
|
|
//================================
|
| 409 |
|
|
|
| 410 |
|
|
wire [32*8-1:0] inst_short = inst_name;
|
| 411 |
|
|
|
| 412 |
|
|
reg [32*8-1:0] inst_full;
|
| 413 |
|
|
always @(inst_type or inst_name or inst_bw or inst_as or inst_ad)
|
| 414 |
|
|
begin
|
| 415 |
|
|
inst_full = myFormat(inst_name, inst_bw, 0);
|
| 416 |
|
|
inst_full = myFormat(inst_full, inst_as, 1);
|
| 417 |
|
|
if (inst_type=="TWO-OP")
|
| 418 |
|
|
inst_full = myFormat(inst_full, ",", 0);
|
| 419 |
|
|
inst_full = myFormat(inst_full, inst_ad, 1);
|
| 420 |
|
|
if (opcode==16'h4303)
|
| 421 |
|
|
inst_full = "NOP";
|
| 422 |
|
|
if (opcode==`DBG_SWBRK_OP)
|
| 423 |
|
|
inst_full = "SBREAK";
|
| 424 |
|
|
|
| 425 |
|
|
end
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
// Instruction program counter
|
| 429 |
|
|
//================================
|
| 430 |
|
|
|
| 431 |
|
|
reg [15:0] inst_pc;
|
| 432 |
|
|
always @(posedge mclk or posedge puc)
|
| 433 |
|
|
if (puc) inst_pc <= 16'h0000;
|
| 434 |
|
|
else if (decode) inst_pc <= pc;
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
endmodule // msp_debug
|
| 438 |
|
|
|
