OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_clock_mux.v] - Blame information for rev 202

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi
//----------------------------------------------------------------------------
2
// Copyright (C) 2009 , Olivier Girard
3
//
4
// Redistribution and use in source and binary forms, with or without
5
// modification, are permitted provided that the following conditions
6
// are met:
7
//     * Redistributions of source code must retain the above copyright
8
//       notice, this list of conditions and the following disclaimer.
9
//     * Redistributions in binary form must reproduce the above copyright
10
//       notice, this list of conditions and the following disclaimer in the
11
//       documentation and/or other materials provided with the distribution.
12
//     * Neither the name of the authors nor the names of its contributors
13
//       may be used to endorse or promote products derived from this software
14
//       without specific prior written permission.
15
//
16
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
21
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26
// THE POSSIBILITY OF SUCH DAMAGE
27
//
28
//----------------------------------------------------------------------------
29
//
30
// *File Name: omsp_clock_mux.v
31 202 olivier.gi
//
32 134 olivier.gi
// *Module Description:
33
//                       Standard clock mux for the openMSP430
34
//
35
// *Author(s):
36
//              - Olivier Girard,    olgirard@gmail.com
37
//
38
//----------------------------------------------------------------------------
39
// $Rev: 103 $
40
// $LastChangedBy: olivier.girard $
41
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
42
//----------------------------------------------------------------------------
43
 
44
module  omsp_clock_mux (
45
 
46
// OUTPUTs
47
    clk_out,                   // Clock output
48
 
49
// INPUTs
50
    clk_in0,                   // Clock input 0
51
    clk_in1,                   // Clock input 1
52
    reset,                     // Reset
53
    scan_mode,                 // Scan mode (clk_in0 is selected in scan mode)
54 202 olivier.gi
    select_in                  // Clock selection
55 134 olivier.gi
);
56
 
57
// OUTPUTs
58
//=========
59
output         clk_out;        // Clock output
60
 
61
// INPUTs
62
//=========
63
input          clk_in0;        // Clock input 0
64
input          clk_in1;        // Clock input 1
65
input          reset;          // Reset
66
input          scan_mode;      // Scan mode (clk_in0 is selected in scan mode)
67 202 olivier.gi
input          select_in;      // Clock selection
68 134 olivier.gi
 
69
 
70
//===========================================================================================================================//
71
// 1)  CLOCK MUX                                                                                                             //
72
//===========================================================================================================================//
73
//                                                                                                                           //
74
//    The following (glitch free) clock mux is implemented as following:                                                     //
75
//                                                                                                                           //
76
//                                                                                                                           //
77
//                                                                                                                           //
78
//                                                                                                                           //
79
//                                   +-----.     +--------+   +--------+                                                     //
80 202 olivier.gi
//    select_in >>----+-------------O|      \    |        |   |        |          +-----.                                    //
81 134 olivier.gi
//                    |              |       |---| D    Q |---| D    Q |--+-------|      \                                   //
82
//                    |     +-------O|      /    |        |   |        |  |       |       |O-+                               //
83
//                    |     |        +-----'     |        |   |        |  |   +--O|      /   |                               //
84
//                    |     |                    |   /\   |   |   /\   |  |   |   +-----'    |                               //
85
//                    |     |                    +--+--+--+   +--+--+--+  |   |              |                               //
86
//                    |     |                        O            |       |   |              |                               //
87
//                    |     |                        |            |       |   |              |  +-----.                      //
88
//       clk_in0 >>----------------------------------+------------+-----------+              +--|      \                     //
89
//                    |     |                                             |                     |       |----<< clk_out      //
90
//                    |     |     +---------------------------------------+                  +--|      /                     //
91
//                    |     |     |                                                          |  +-----'                      //
92
//                    |     +---------------------------------------------+                  |                               //
93
//                    |           |                                       |                  |                               //
94
//                    |           |  +-----.     +--------+   +--------+  |                  |                               //
95
//                    |           +-O|      \    |        |   |        |  |       +-----.    |                               //
96
//                    |              |       |---| D    Q |---| D    Q |--+-------|      \   |                               //
97
//                    +--------------|      /    |        |   |        |          |       |O-+                               //
98
//                                   +-----'     |        |   |        |      +--O|      /                                   //
99
//                                               |   /\   |   |   /\   |      |   +-----'                                    //
100
//                                               +--+--+--+   +--+--+--+      |                                              //
101
//                                                   O            |           |                                              //
102
//                                                   |            |           |                                              //
103
//       clk_in1 >>----------------------------------+------------+-----------+                                              //
104
//                                                                                                                           //
105
//                                                                                                                           //
106
//===========================================================================================================================//
107
 
108
//-----------------------------------------------------------------------------
109
// Wire declarations
110
//-----------------------------------------------------------------------------
111 202 olivier.gi
 
112 134 olivier.gi
wire in0_select;
113
reg  in0_select_s;
114
reg  in0_select_ss;
115
wire in0_enable;
116
 
117
wire in1_select;
118
reg  in1_select_s;
119
reg  in1_select_ss;
120
wire in1_enable;
121
 
122
wire clk_in0_inv;
123
wire clk_in1_inv;
124
wire gated_clk_in0;
125
wire gated_clk_in1;
126
 
127
 
128
//-----------------------------------------------------------------------------
129
// CLK_IN0 Selection
130
//-----------------------------------------------------------------------------
131 202 olivier.gi
 
132
assign in0_select = ~select_in & ~in1_select_ss;
133
 
134 134 olivier.gi
always @ (posedge clk_in0_inv or posedge reset)
135
  if (reset) in0_select_s  <=  1'b1;
136
  else       in0_select_s  <=  in0_select;
137
 
138
always @ (posedge clk_in0     or posedge reset)
139
  if (reset) in0_select_ss <=  1'b1;
140
  else       in0_select_ss <=  in0_select_s;
141
 
142
assign in0_enable = in0_select_ss | scan_mode;
143
 
144
 
145
//-----------------------------------------------------------------------------
146
// CLK_IN1 Selection
147
//-----------------------------------------------------------------------------
148 202 olivier.gi
 
149
assign in1_select =  select_in & ~in0_select_ss;
150
 
151 134 olivier.gi
always @ (posedge clk_in1_inv or posedge reset)
152
  if (reset) in1_select_s  <=  1'b0;
153
  else       in1_select_s  <=  in1_select;
154
 
155
always @ (posedge clk_in1     or posedge reset)
156
  if (reset) in1_select_ss <=  1'b0;
157
  else       in1_select_ss <=  in1_select_s;
158
 
159
assign in1_enable = in1_select_ss & ~scan_mode;
160
 
161 202 olivier.gi
 
162 134 olivier.gi
//-----------------------------------------------------------------------------
163
// Clock MUX
164
//-----------------------------------------------------------------------------
165
//
166
// IMPORTANT NOTE:
167
//                  Because the clock network is a critical part of the design,
168
//                 the following combinatorial logic should be replaced with
169
//                 direct instanciation of standard cells from target library.
170
//                  Don't forget the "dont_touch" attribute to make sure
171
//                 synthesis won't mess it up.
172
//
173
 
174
// Replace with standard cell INVERTER
175
assign clk_in0_inv   = ~clk_in0;
176
assign clk_in1_inv   = ~clk_in1;
177
 
178
 
179
// Replace with standard cell NAND2
180
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
181
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
182
 
183 202 olivier.gi
 
184 134 olivier.gi
// Replace with standard cell AND2
185
assign clk_out       =  (gated_clk_in0 & gated_clk_in1);
186
 
187
 
188
 
189
endmodule // omsp_clock_gate

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.