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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                               CLOCK MODULE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the clock module:                                                    */
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/*                        - Check the ACLK and SMCLK clock generation.       */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer mclk_counter;
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always @ (negedge mclk)
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  mclk_counter <=  mclk_counter+1;
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integer aclk_counter;
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always @ (negedge mclk)
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  if (aclk_en) aclk_counter <=  aclk_counter+1;
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integer smclk_counter;
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always @ (negedge mclk)
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  if (smclk_en) smclk_counter <=  smclk_counter+1;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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      // ACLK GENERATION
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      //--------------------------------------------------------
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                                // ------- Divider /1 ----------
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      @(r15 === 16'h0001);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
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      if (aclk_counter !== 24)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) =====");
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                                // ------- Divider /2 ----------
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      @(r15 === 16'h0002);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
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      if (aclk_counter !== 12)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) =====");
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                                // ------- Divider /4 ----------
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      @(r15 === 16'h0003);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
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      if (aclk_counter !== 6)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) =====");
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                                // ------- Divider /8 ----------
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      @(r15 === 16'h0004);
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      @(negedge aclk_en);
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      mclk_counter = 0;
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      aclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
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      if (aclk_counter !== 3)   tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) =====");
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      // SMCLK GENERATION - LFXT_CLK INPUT
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      //--------------------------------------------------------
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                                // ------- Divider /1 ----------
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      @(r15 === 16'h1001);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
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      if (smclk_counter !== 24) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /1) =====");
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                                // ------- Divider /2 ----------
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      @(r15 === 16'h1002);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
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      if (smclk_counter !== 12) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /2) =====");
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                                // ------- Divider /4 ----------
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      @(r15 === 16'h1003);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
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      if (smclk_counter !== 6)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /4) =====");
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                                // ------- Divider /8 ----------
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      @(r15 === 16'h1004);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(735) @(posedge mclk);
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      if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
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      if (smclk_counter !== 3)  tb_error("====== CLOCK GENERATOR: SMCLK - LFXT_CLK INPUT (DIV /8) =====");
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      // SMCLK GENERATION - DCO_CLK INPUT
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      //--------------------------------------------------------
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                                // ------- Divider /1 ----------
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      @(r15 === 16'h2001);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(600) @(posedge mclk);
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      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
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      if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) =====");
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                                // ------- Divider /2 ----------
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      @(r15 === 16'h2002);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(600) @(posedge mclk);
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      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
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      if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) =====");
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                                // ------- Divider /4 ----------
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      @(r15 === 16'h2003);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(600) @(posedge mclk);
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      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
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      if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) =====");
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                                // ------- Divider /8 ----------
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      @(r15 === 16'h2004);
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      @(negedge smclk_en);
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      mclk_counter = 0;
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      smclk_counter = 0;
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      repeat(600) @(posedge mclk);
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      if (mclk_counter !== 600)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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      if (smclk_counter !== 75)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) =====");
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      stimulus_done = 1;
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   end
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