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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.v] - Blame information for rev 202

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                               CLOCK MODULE                                */
/*---------------------------------------------------------------------------*/
/* Test the clock module:                                                    */
/*                        - Check the ACLK and SMCLK clock generation.       */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
 
integer dco_clk_counter;
always @ (negedge dco_clk)
  dco_clk_counter <=  dco_clk_counter+1;
 
integer lfxt_clk_counter;
always @ (negedge lfxt_clk)
  lfxt_clk_counter <=  lfxt_clk_counter+1;
 
integer mclk_counter;
always @ (posedge mclk)
  mclk_counter <=  mclk_counter+1;
 
integer aclk_counter;
always @ (negedge aclk)
  aclk_counter <=  aclk_counter+1;
 
integer smclk_counter;
always @ (negedge smclk)
  smclk_counter <=  smclk_counter+1;
 
integer dbg_clk_counter;
always @ (negedge dbg_clk)
  dbg_clk_counter <=  dbg_clk_counter+1;
 
reg [15:0] reg_val;
reg [15:0] bcsctl1_mask;
reg [15:0] bcsctl2_mask;
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
 
      force tb_openMSP430.dut.wdt_reset = 1'b0;
 
`ifdef ASIC_CLOCKING
 
      // MCLK GENERATION: SELECTING DCO_CLK
      //--------------------------------------------------------
 
                                // ------- Divider /1 ----------
      @(r15 === 16'h0001);
      @(posedge mclk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /1) - TEST 1 =====");
      if (mclk_counter    !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /1) - TEST 2 =====");
 
 
   `ifdef MCLK_DIVIDER
                                // ------- Divider /2 ----------
      @(r15 === 16'h0002);
      @(posedge mclk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /2) - TEST 1 =====");
      if (mclk_counter    !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /2) - TEST 2 =====");
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h0003);
      @(posedge mclk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /4) - TEST 1 =====");
      if (mclk_counter    !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /4) - TEST 2 =====");
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h0004);
      @(posedge mclk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /8) - TEST 1 =====");
      if (mclk_counter    !== 91)  tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /8) - TEST 2 =====");
 
   `else
                                // ------- Divider /2 ----------
      @(r15 === 16'h0002);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /2) - TEST 1 =====");
      if (mclk_counter    !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /2) - TEST 2 =====");
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h0003);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /4) - TEST 1 =====");
      if (mclk_counter    !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /4) - TEST 2 =====");
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h0004);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      mclk_counter    = 0;
      repeat(735) @(posedge dco_clk);
      #1;
      if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /8) - TEST 1 =====");
      if (mclk_counter    !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT  (DIV /8) - TEST 2 =====");
 
 
   `endif
 
      @(r15 === 16'h1000);
 
 
      // MCLK GENERATION: SELECTING LFXT_CLK
      //--------------------------------------------------------
      // VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN
      @(r15 === 16'h2000);
 
 
      // ACLK GENERATION
      //--------------------------------------------------------
 
                                // ------- Divider /1 ----------
      @(r15 === 16'h2001);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      #1;
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");
`endif
 
 
   `ifdef ACLK_DIVIDER
                                // ------- Divider /2 ----------
      @(r15 === 16'h2002);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      #1;
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
      if (aclk_counter     !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      #1;
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
      if (aclk_counter     !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
`endif
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h2003);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
      if (aclk_counter     !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
      if (aclk_counter     !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
`endif
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h2004);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
      if (aclk_counter     !== 7)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
      if (aclk_counter     !== 7)  tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
`endif
 
   `else
                                // ------- Divider /2 ----------
      @(r15 === 16'h2002);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      #1;
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      #1;
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");
`endif
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h2003);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      #1;
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      #1;
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");
`endif
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h2004);
`ifdef LFXT_DOMAIN
      @(posedge lfxt_clk);
`else
      @(posedge dco_clk);
`endif
      #1;
      dco_clk_counter  = 0;
      lfxt_clk_counter = 0;
      aclk_counter     = 0;
`ifdef LFXT_DOMAIN
      repeat(54) @(posedge lfxt_clk);
      #1;
      if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
`else
      repeat(54) @(posedge dco_clk);
      #1;
      if (dco_clk_counter  !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");
      if (aclk_counter     !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");
`endif
 
   `endif
 
      @(r15 === 16'h3000);
 
 
      // SMCLK GENERATION - DCO_CLK INPUT
      //--------------------------------------------------------
 
                                // ------- Divider /1 ----------
      @(r15 === 16'h3001);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
      if (smclk_counter   !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
 
   `ifdef SMCLK_DIVIDER
                                // ------- Divider /2 ----------
      @(r15 === 16'h3002);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
      if (smclk_counter   !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h3003);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
      if (smclk_counter   !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h3004);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
      if (smclk_counter   !== 75)  tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
 
   `else
                                // ------- Divider /2 ----------
      @(r15 === 16'h3002);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
      if (smclk_counter   !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
 
 
                                // ------- Divider /4 ----------
      @(r15 === 16'h3003);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
      if (smclk_counter   !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
 
 
                                // ------- Divider /8 ----------
      @(r15 === 16'h3004);
      @(posedge dco_clk);
      #1;
      dco_clk_counter = 0;
      smclk_counter   = 0;
      repeat(600) @(posedge dco_clk);
      if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
      if (smclk_counter   !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
 
   `endif
 
      @(r15 === 16'h4000);
 
 
      // SMCLK GENERATION - LFXT_CLK INPUT
      //--------------------------------------------------------
      // VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN
      @(r15 === 16'h5000);
 
 
      // CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT
      //--------------------------------------------------------
 
      @(r15 === 16'h5001);
      repeat(50) @(negedge dco_clk);
      if (dbg_freeze    == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
      cpu_en        = 1'b0;
      #(3*763*2);
      reg_val       = r14;            // Read R14 register & initialize mclk/smclk/aclk counters
      mclk_counter  = 0;
      aclk_counter  = 0;
      smclk_counter = 0;
 
      #(50*500); // Make sure that the CPU is stopped
      if (reg_val       !== r14)  tb_error("====== CPU is not stopped (test 3) =====");
      if (mclk_counter  !== 0)    tb_error("====== MCLK is not stopped (test 4) =====");
`ifdef OSCOFF_EN
      if (aclk_counter  !== 0)    tb_error("====== ACLK is not stopped (test 5) =====");
`else
  `ifdef LFXT_DOMAIN
    `ifdef ACLK_DIVIDER
      if (aclk_counter  !== 0)    tb_error("====== ACLK is running     (test 5) =====");
    `else
      if (aclk_counter  !== 17)   tb_error("====== ACLK is not running (test 5) =====");
    `endif
  `else
      if (aclk_counter  !== 0)    tb_error("====== ACLK is running (test 5) =====");
  `endif
`endif
      if (smclk_counter !== 0)    tb_error("====== SMCLK is not stopped (test 6) =====");
      cpu_en = 1'b1;
 
      #(50*500); // Make sure that the CPU runs again
      if (reg_val       == r14)  tb_error("====== CPU is not running (test 7) =====");
      if (mclk_counter  == 0)    tb_error("====== MCLK is not running (test 8) =====");
      if (aclk_counter  == 0)    tb_error("====== ACLK is not running (test 9) =====");
      if (smclk_counter == 0)    tb_error("====== SMCLK is not running (test 10) =====");
 
 
      @(r15 === 16'h5002);
`ifdef DBG_EN
      repeat(50) @(posedge dco_clk);
      if (dbg_freeze     == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");
      if (dbg_rst        == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");
 
      dbg_en = 1'b1;
      repeat(6)  @(posedge mclk);
      reg_val         = r14;          // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
      mclk_counter    = 0;
      aclk_counter    = 0;
      smclk_counter   = 0;
      dbg_clk_counter = 0;
      if (dbg_freeze     == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");
      if (dbg_rst       !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");
 
      repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs
      if (reg_val          == r14)  tb_error("====== CPU is stopped (test 5) =====");
      if (mclk_counter     == 0)    tb_error("====== MCLK is stopped (test 6) =====");
      if (aclk_counter     == 0)    tb_error("====== ACLK is stopped (test 7) =====");
      if (smclk_counter    == 0)    tb_error("====== SMCLK is stopped (test 8) =====");
      if (dbg_clk_counter  == 0)    tb_error("====== DBG_CLK is stopped (test 9) =====");
      if (dbg_freeze       == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 10) =====");
      if (dbg_rst         !== 1'b0) tb_error("====== DBG_RST signal is active (test 11) =====");
 
      dbg_en = 1'b0;
      repeat(6)  @(posedge mclk);
      reg_val         = r14;          // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters
      mclk_counter    = 0;
      aclk_counter    = 0;
      smclk_counter   = 0;
      dbg_clk_counter = 0;
      if (dbg_freeze     == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 12) =====");
      if (dbg_rst        == 1'b0) tb_error("====== DBG_RST signal is not active (test 13) =====");
 
      repeat(500) @(posedge dco_clk); // Make sure that the DBG interface is stopped
      if (reg_val          == r14)  tb_error("====== CPU is not running (test 14) =====");
      if (mclk_counter     == 0)    tb_error("====== MCLK is not running (test 15) =====");
      if (aclk_counter     == 0)    tb_error("====== ACLK is not running (test 16) =====");
      if (smclk_counter    == 0)    tb_error("====== SMCLK is not running (test 17) =====");
      if (dbg_clk_counter !== 0)    tb_error("====== DBG_CLK is not stopped (test 18) =====");
      if (dbg_freeze       == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 19) =====");
      if (dbg_rst          == 1'b0) tb_error("====== DBG_RST signal is not active (test 20) =====");
 
      if (r15 !== 16'h5002) tb_error("====== DBG_EN did generate a PUC reset (test 21) =====");
`endif
 
      @(r15 === 16'h6000);
 
 
      // RD/WR ACCESS TO REGISTERS
      //--------------------------------------------------------
 
      bcsctl1_mask = 16'h0000;
      bcsctl2_mask = 16'h0000;
 
`ifdef ASIC_CLOCKING
  `ifdef ACLK_DIVIDER
      bcsctl1_mask = bcsctl1_mask | 16'h0030;
  `endif
  `ifdef DMA_IF_EN
    `ifdef CPUOFF_EN
      bcsctl1_mask = bcsctl1_mask | 16'h0001;
    `endif
    `ifdef OSCOFF_EN
      bcsctl1_mask = bcsctl1_mask | 16'h0002;
    `endif
    `ifdef SCG0_EN
      bcsctl1_mask = bcsctl1_mask | 16'h0004;
    `endif
    `ifdef SCG1_EN
      bcsctl1_mask = bcsctl1_mask | 16'h0008;
    `endif
  `endif
`else
      bcsctl1_mask = bcsctl1_mask | 16'h0030;
`endif
 
`ifdef MCLK_MUX
      bcsctl2_mask = bcsctl2_mask | 16'h0080;
`endif
`ifdef MCLK_DIVIDER
      bcsctl2_mask = bcsctl2_mask | 16'h0030;
`endif
`ifdef ASIC_CLOCKING
  `ifdef SMCLK_MUX
      bcsctl2_mask = bcsctl2_mask | 16'h0008;
  `endif
  `ifdef SMCLK_DIVIDER
      bcsctl2_mask = bcsctl2_mask | 16'h0006;
  `endif
`else
      bcsctl2_mask = bcsctl2_mask | 16'h0008;
      bcsctl2_mask = bcsctl2_mask | 16'h0006;
`endif
 
       @(r15 === 16'h7000);
       if (r4  !== 16'h0000)     tb_error("====== BCSCTL1 rd/wr access error (test 1) =====");
       if (r5  !== 16'h0000)     tb_error("====== BCSCTL2 rd/wr access error (test 1) =====");
 
       if (r6  !== bcsctl1_mask) tb_error("====== BCSCTL1 rd/wr access error (test 2) =====");
       if (r7  !== 16'h0000)     tb_error("====== BCSCTL2 rd/wr access error (test 2) =====");
 
       if (r8  !== 16'h0000)     tb_error("====== BCSCTL1 rd/wr access error (test 3) =====");
       if (r9  !== 16'h0000)     tb_error("====== BCSCTL2 rd/wr access error (test 3) =====");
 
       if (r10 !== 16'h0000)     tb_error("====== BCSCTL1 rd/wr access error (test 4) =====");
       if (r11 !== bcsctl2_mask) tb_error("====== BCSCTL2 rd/wr access error (test 4) =====");
 
       if (r12 !== 16'h0000)     tb_error("====== BCSCTL1 rd/wr access error (test 5) =====");
       if (r13 !== 16'h0000)     tb_error("====== BCSCTL2 rd/wr access error (test 5) =====");
 
 
`else
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
`endif
 
      stimulus_done = 1;
   end

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* CLOCK MODULE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the clock module: */`
27			`/* - Check the ACLK and SMCLK clock generation. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38			`define LONG_TIMEOUT
39
40
41			`integer dco_clk_counter;`
42			`always @ (negedge dco_clk)`
43			`dco_clk_counter <= dco_clk_counter+1;`
44
45			`integer lfxt_clk_counter;`
46			`always @ (negedge lfxt_clk)`
47			`lfxt_clk_counter <= lfxt_clk_counter+1;`
48
49			`integer mclk_counter;`
50			`always @ (posedge mclk)`
51			`mclk_counter <= mclk_counter+1;`
52
53			`integer aclk_counter;`
54			`always @ (negedge aclk)`
55			`aclk_counter <= aclk_counter+1;`
56
57			`integer smclk_counter;`
58			`always @ (negedge smclk)`
59			`smclk_counter <= smclk_counter+1;`
60
61			`integer dbg_clk_counter;`
62			`always @ (negedge dbg_clk)`
63			`dbg_clk_counter <= dbg_clk_counter+1;`
64
65			`reg [15:0] reg_val;`
66			`reg [15:0] bcsctl1_mask;`
67			`reg [15:0] bcsctl2_mask;`
68	202	olivier.gi
69	134	olivier.gi	`initial`
70			`begin`
71			`$display(" ===============================================");`
72			`$display("\| START SIMULATION \|");`
73			`$display(" ===============================================");`
74			`repeat(5) @(posedge mclk);`
75			`stimulus_done = 0;`
76
77			`force tb_openMSP430.dut.wdt_reset = 1'b0;`
78
79	180	olivier.gi	`ifdef ASIC_CLOCKING
80	134	olivier.gi
81			`// MCLK GENERATION: SELECTING DCO_CLK`
82			`//--------------------------------------------------------`
83
84			`// ------- Divider /1 ----------`
85			`@(r15 === 16'h0001);`
86			`@(posedge mclk);`
87			`#1;`
88			`dco_clk_counter = 0;`
89			`mclk_counter = 0;`
90			`repeat(735) @(posedge dco_clk);`
91			`#1;`
92			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");`
93			`if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");`
94
95	202	olivier.gi
96	134	olivier.gi	`ifdef MCLK_DIVIDER
97			`// ------- Divider /2 ----------`
98			`@(r15 === 16'h0002);`
99			`@(posedge mclk);`
100			`#1;`
101			`dco_clk_counter = 0;`
102			`mclk_counter = 0;`
103			`repeat(735) @(posedge dco_clk);`
104			`#1;`
105			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");`
106			`if (mclk_counter !== 367) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");`
107
108	202	olivier.gi
109	134	olivier.gi	`// ------- Divider /4 ----------`
110			`@(r15 === 16'h0003);`
111			`@(posedge mclk);`
112			`#1;`
113			`dco_clk_counter = 0;`
114			`mclk_counter = 0;`
115			`repeat(735) @(posedge dco_clk);`
116			`#1;`
117			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");`
118			`if (mclk_counter !== 183) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");`
119	202	olivier.gi
120
121	134	olivier.gi	`// ------- Divider /8 ----------`
122			`@(r15 === 16'h0004);`
123			`@(posedge mclk);`
124			`#1;`
125			`dco_clk_counter = 0;`
126			`mclk_counter = 0;`
127			`repeat(735) @(posedge dco_clk);`
128			`#1;`
129			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");`
130			`if (mclk_counter !== 91) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");`
131
132			`else
133			`// ------- Divider /2 ----------`
134			`@(r15 === 16'h0002);`
135			`@(posedge dco_clk);`
136			`#1;`
137			`dco_clk_counter = 0;`
138			`mclk_counter = 0;`
139			`repeat(735) @(posedge dco_clk);`
140			`#1;`
141			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");`
142			`if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");`
143
144	202	olivier.gi
145	134	olivier.gi	`// ------- Divider /4 ----------`
146			`@(r15 === 16'h0003);`
147			`@(posedge dco_clk);`
148			`#1;`
149			`dco_clk_counter = 0;`
150			`mclk_counter = 0;`
151			`repeat(735) @(posedge dco_clk);`
152			`#1;`
153			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");`
154			`if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");`
155	202	olivier.gi
156
157	134	olivier.gi	`// ------- Divider /8 ----------`
158			`@(r15 === 16'h0004);`
159			`@(posedge dco_clk);`
160			`#1;`
161			`dco_clk_counter = 0;`
162			`mclk_counter = 0;`
163			`repeat(735) @(posedge dco_clk);`
164			`#1;`
165			`if (dco_clk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");`
166			`if (mclk_counter !== 735) tb_error("====== CLOCK GENERATOR: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");`
167
168
169			`endif
170
171			`@(r15 === 16'h1000);`
172
173	202	olivier.gi
174	134	olivier.gi	`// MCLK GENERATION: SELECTING LFXT_CLK`
175			`//--------------------------------------------------------`
176			`// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_MCLK" PATTERN`
177			`@(r15 === 16'h2000);`
178
179	202	olivier.gi
180	134	olivier.gi	`// ACLK GENERATION`
181			`//--------------------------------------------------------`
182
183			`// ------- Divider /1 ----------`
184			`@(r15 === 16'h2001);`
185			`ifdef LFXT_DOMAIN
186			`@(posedge lfxt_clk);`
187			`else
188			`@(posedge dco_clk);`
189			`endif
190			`#1;`
191			`dco_clk_counter = 0;`
192			`lfxt_clk_counter = 0;`
193			`aclk_counter = 0;`
194			`ifdef LFXT_DOMAIN
195			`repeat(54) @(posedge lfxt_clk);`
196			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");`
197			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");`
198			`else
199			`repeat(54) @(posedge dco_clk);`
200			`#1;`
201			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 1 =====");`
202			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /1) - TEST 2 =====");`
203			`endif
204
205	202	olivier.gi
206	134	olivier.gi	`ifdef ACLK_DIVIDER
207			`// ------- Divider /2 ----------`
208			`@(r15 === 16'h2002);`
209			`ifdef LFXT_DOMAIN
210			`@(posedge lfxt_clk);`
211			`else
212			`@(posedge dco_clk);`
213			`endif
214			`#1;`
215			`dco_clk_counter = 0;`
216			`lfxt_clk_counter = 0;`
217			`aclk_counter = 0;`
218			`ifdef LFXT_DOMAIN
219			`repeat(54) @(posedge lfxt_clk);`
220			`#1;`
221			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");`
222			`if (aclk_counter !== 28) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");`
223			`else
224			`repeat(54) @(posedge dco_clk);`
225			`#1;`
226			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");`
227			`if (aclk_counter !== 27) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");`
228			`endif
229
230	202	olivier.gi
231	134	olivier.gi	`// ------- Divider /4 ----------`
232			`@(r15 === 16'h2003);`
233			`ifdef LFXT_DOMAIN
234			`@(posedge lfxt_clk);`
235			`else
236			`@(posedge dco_clk);`
237			`endif
238			`#1;`
239			`dco_clk_counter = 0;`
240			`lfxt_clk_counter = 0;`
241			`aclk_counter = 0;`
242			`ifdef LFXT_DOMAIN
243			`repeat(54) @(posedge lfxt_clk);`
244			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");`
245			`if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");`
246			`else
247			`repeat(54) @(posedge dco_clk);`
248			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");`
249			`if (aclk_counter !== 14) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");`
250			`endif
251	202	olivier.gi
252
253	134	olivier.gi	`// ------- Divider /8 ----------`
254			`@(r15 === 16'h2004);`
255			`ifdef LFXT_DOMAIN
256			`@(posedge lfxt_clk);`
257			`else
258			`@(posedge dco_clk);`
259			`endif
260			`#1;`
261			`dco_clk_counter = 0;`
262			`lfxt_clk_counter = 0;`
263			`aclk_counter = 0;`
264			`ifdef LFXT_DOMAIN
265			`repeat(54) @(posedge lfxt_clk);`
266			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");`
267			`if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");`
268			`else
269			`repeat(54) @(posedge dco_clk);`
270			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");`
271			`if (aclk_counter !== 7) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");`
272			`endif
273	202	olivier.gi
274	134	olivier.gi	`else
275			`// ------- Divider /2 ----------`
276			`@(r15 === 16'h2002);`
277			`ifdef LFXT_DOMAIN
278			`@(posedge lfxt_clk);`
279			`else
280			`@(posedge dco_clk);`
281			`endif
282			`#1;`
283			`dco_clk_counter = 0;`
284			`lfxt_clk_counter = 0;`
285			`aclk_counter = 0;`
286			`ifdef LFXT_DOMAIN
287			`repeat(54) @(posedge lfxt_clk);`
288			`#1;`
289			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");`
290			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");`
291			`else
292			`repeat(54) @(posedge dco_clk);`
293			`#1;`
294			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 1 =====");`
295			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /2) - TEST 2 =====");`
296			`endif
297
298	202	olivier.gi
299	134	olivier.gi	`// ------- Divider /4 ----------`
300			`@(r15 === 16'h2003);`
301			`ifdef LFXT_DOMAIN
302			`@(posedge lfxt_clk);`
303			`else
304			`@(posedge dco_clk);`
305			`endif
306			`#1;`
307			`dco_clk_counter = 0;`
308			`lfxt_clk_counter = 0;`
309			`aclk_counter = 0;`
310			`ifdef LFXT_DOMAIN
311			`repeat(54) @(posedge lfxt_clk);`
312			`#1;`
313			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");`
314			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");`
315			`else
316			`repeat(54) @(posedge dco_clk);`
317			`#1;`
318			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 1 =====");`
319			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /4) - TEST 2 =====");`
320			`endif
321	202	olivier.gi
322
323	134	olivier.gi	`// ------- Divider /8 ----------`
324			`@(r15 === 16'h2004);`
325			`ifdef LFXT_DOMAIN
326			`@(posedge lfxt_clk);`
327			`else
328			`@(posedge dco_clk);`
329			`endif
330			`#1;`
331			`dco_clk_counter = 0;`
332			`lfxt_clk_counter = 0;`
333			`aclk_counter = 0;`
334			`ifdef LFXT_DOMAIN
335			`repeat(54) @(posedge lfxt_clk);`
336			`#1;`
337			`if (lfxt_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");`
338			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");`
339			`else
340			`repeat(54) @(posedge dco_clk);`
341			`#1;`
342			`if (dco_clk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 1 =====");`
343			`if (aclk_counter !== 54) tb_error("====== CLOCK GENERATOR: ACLK (DIV /8) - TEST 2 =====");`
344			`endif
345	202	olivier.gi
346	134	olivier.gi	`endif
347
348			`@(r15 === 16'h3000);`
349
350	202	olivier.gi
351	134	olivier.gi	`// SMCLK GENERATION - DCO_CLK INPUT`
352			`//--------------------------------------------------------`
353
354			`// ------- Divider /1 ----------`
355			`@(r15 === 16'h3001);`
356			`@(posedge dco_clk);`
357			`#1;`
358			`dco_clk_counter = 0;`
359			`smclk_counter = 0;`
360			`repeat(600) @(posedge dco_clk);`
361			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");`
362			`if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");`
363
364			`ifdef SMCLK_DIVIDER
365			`// ------- Divider /2 ----------`
366			`@(r15 === 16'h3002);`
367			`@(posedge dco_clk);`
368			`#1;`
369			`dco_clk_counter = 0;`
370			`smclk_counter = 0;`
371			`repeat(600) @(posedge dco_clk);`
372			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");`
373			`if (smclk_counter !== 300) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");`
374
375	202	olivier.gi
376	134	olivier.gi	`// ------- Divider /4 ----------`
377			`@(r15 === 16'h3003);`
378			`@(posedge dco_clk);`
379			`#1;`
380			`dco_clk_counter = 0;`
381			`smclk_counter = 0;`
382			`repeat(600) @(posedge dco_clk);`
383			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");`
384			`if (smclk_counter !== 150) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");`
385	202	olivier.gi
386
387	134	olivier.gi	`// ------- Divider /8 ----------`
388			`@(r15 === 16'h3004);`
389			`@(posedge dco_clk);`
390			`#1;`
391			`dco_clk_counter = 0;`
392			`smclk_counter = 0;`
393			`repeat(600) @(posedge dco_clk);`
394			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");`
395			`if (smclk_counter !== 75) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");`
396
397			`else
398			`// ------- Divider /2 ----------`
399			`@(r15 === 16'h3002);`
400			`@(posedge dco_clk);`
401			`#1;`
402			`dco_clk_counter = 0;`
403			`smclk_counter = 0;`
404			`repeat(600) @(posedge dco_clk);`
405			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");`
406			`if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");`
407
408	202	olivier.gi
409	134	olivier.gi	`// ------- Divider /4 ----------`
410			`@(r15 === 16'h3003);`
411			`@(posedge dco_clk);`
412			`#1;`
413			`dco_clk_counter = 0;`
414			`smclk_counter = 0;`
415			`repeat(600) @(posedge dco_clk);`
416			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");`
417			`if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");`
418	202	olivier.gi
419
420	134	olivier.gi	`// ------- Divider /8 ----------`
421			`@(r15 === 16'h3004);`
422			`@(posedge dco_clk);`
423			`#1;`
424			`dco_clk_counter = 0;`
425			`smclk_counter = 0;`
426			`repeat(600) @(posedge dco_clk);`
427			`if (dco_clk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");`
428			`if (smclk_counter !== 600) tb_error("====== CLOCK GENERATOR: SMCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");`
429
430			`endif
431
432			`@(r15 === 16'h4000);`
433
434
435			`// SMCLK GENERATION - LFXT_CLK INPUT`
436			`//--------------------------------------------------------`
437			`// VERIFICATION DONE IN THE "CLOC_MODULE_ASIC_SMCLK" PATTERN`
438			`@(r15 === 16'h5000);`
439
440
441			`// CPU ENABLE - CPU_EN INPUT / DBG ENABLE - DBG_EN INPUT`
442			`//--------------------------------------------------------`
443
444			`@(r15 === 16'h5001);`
445			`repeat(50) @(negedge dco_clk);`
446			`if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");`
447			`cpu_en = 1'b0;`
448			`#(37632);`
449			`reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk counters`
450			`mclk_counter = 0;`
451			`aclk_counter = 0;`
452			`smclk_counter = 0;`
453
454			`#(50*500); // Make sure that the CPU is stopped`
455			`if (reg_val !== r14) tb_error("====== CPU is not stopped (test 3) =====");`
456			`if (mclk_counter !== 0) tb_error("====== MCLK is not stopped (test 4) =====");`
457			`ifdef OSCOFF_EN
458			`if (aclk_counter !== 0) tb_error("====== ACLK is not stopped (test 5) =====");`
459			`else
460			`ifdef LFXT_DOMAIN
461			`ifdef ACLK_DIVIDER
462			`if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");`
463			`else
464			`if (aclk_counter !== 17) tb_error("====== ACLK is not running (test 5) =====");`
465			`endif
466			`else
467			`if (aclk_counter !== 0) tb_error("====== ACLK is running (test 5) =====");`
468			`endif
469			`endif
470			`if (smclk_counter !== 0) tb_error("====== SMCLK is not stopped (test 6) =====");`
471			`cpu_en = 1'b1;`
472
473			`#(50*500); // Make sure that the CPU runs again`
474			`if (reg_val == r14) tb_error("====== CPU is not running (test 7) =====");`
475			`if (mclk_counter == 0) tb_error("====== MCLK is not running (test 8) =====");`
476			`if (aclk_counter == 0) tb_error("====== ACLK is not running (test 9) =====");`
477			`if (smclk_counter == 0) tb_error("====== SMCLK is not running (test 10) =====");`
478
479	202	olivier.gi
480	134	olivier.gi	`@(r15 === 16'h5002);`
481			`ifdef DBG_EN
482			`repeat(50) @(posedge dco_clk);`
483			`if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is active (test 1) =====");`
484			`if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 2) =====");`
485
486			`dbg_en = 1'b1;`
487			`repeat(6) @(posedge mclk);`
488			`reg_val = r14; // Read R14 register & initialize mclk/smclk/aclk/dbg_clk counters`
489			`mclk_counter = 0;`
490			`aclk_counter = 0;`
491			`smclk_counter = 0;`
492			`dbg_clk_counter = 0;`
493			`if (dbg_freeze == 1'b1) tb_error("====== DBG_FREEZE signal is not active (test 3) =====");`
494			`if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 4) =====");`
495
496			`repeat(500) @(posedge dco_clk); // Make sure that the DBG interface runs`
497			`if (reg_val == r14) tb_error("====== CPU is stopped (test 5) =====");`
498			`if (mclk_counter == 0) tb_error("====== MCLK is stopped (test 6) =====");`
499			`if (aclk_counter == 0) tb_error("====== ACLK is stopped (test 7) =====");`
500			`if (smclk_counter == 0) tb_error("====== SMCLK is stopped (test 8) =====");`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module_asic.v] - Blame information for rev 202