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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_i2c_mem.v] - Blame information for rev 202

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1 154 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the debug interface:                                                 */
27 
/*                        - Check Memory RD/WR features.                     */
28 
/*                                                                           */
29 
/*  Note: The burst features are specific to the selected interface          */
30 
/*    (UART/I2C) and are therefore tested in the dbg_uart/dbg_i2c patterns   */
31 
/*                                                                           */
32 
/* Author(s):                                                                */
33 
/*             - Olivier Girard,    olgirard@gmail.com                       */
34 
/*                                                                           */
35 
/*---------------------------------------------------------------------------*/
36 
/* $Rev: 86 $                                                                */
37 
/* $LastChangedBy: olivier.girard $                                          */
38 
/* $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $          */
39 
/*===========================================================================*/
40 
 
41 
`define LONG_TIMEOUT
42 200 olivier.gi 
 
43 154 olivier.gi 
initial
44 
   begin
45 
      $display(" ===============================================");
46 
      $display("|                 START SIMULATION              |");
47 
      $display(" ===============================================");
48 
`ifdef DBG_EN
49 
`ifdef DBG_I2C
50 
      #1 dbg_en = 1;
51 
      repeat(30) @(posedge mclk);
52 
      stimulus_done = 0;
53 
 
54 
   `ifdef DBG_RST_BRK_EN
55 
      dbg_i2c_wr(CPU_CTL,  16'h0002);  // RUN
56 
   `endif
57 200 olivier.gi 
 
58 154 olivier.gi 
      // RD/WR ACCESS: CPU REGISTERS (16b)
59 
      //--------------------------------------------------------
60 
 
61 
      // READ CPU REGISTERS
62 
      dbg_i2c_wr(MEM_ADDR, 16'h0005);  // select register
63 
      dbg_i2c_wr(MEM_CTL,  16'h0005);  // read register
64 
      dbg_i2c_rd(MEM_DATA);            // read data
65 
      if (dbg_i2c_buf !== 16'haaaa)  tb_error("====== CPU REGISTERS (16b): Read R5 =====");
66 
      dbg_i2c_wr(MEM_ADDR, 16'h0006);  // select register
67 
      dbg_i2c_wr(MEM_CTL,  16'h0005);  // read register
68 
      dbg_i2c_rd(MEM_DATA);            // read data
69 
      if (dbg_i2c_buf !== 16'hbbbb)  tb_error("====== CPU REGISTERS (16b): Read R6 =====");
70 
 
71 
      // WRITE CPU REGISTERS
72 
      dbg_i2c_wr(MEM_ADDR, 16'h0005);  // select register
73 
      dbg_i2c_wr(MEM_DATA, 16'hed32);  // write data
74 
      dbg_i2c_wr(MEM_CTL,  16'h0007);  // write register
75 
      repeat(20) @(posedge mclk);
76 
      if (r5 !== 16'hed32)  tb_error("====== CPU REGISTERS (16b): Write R5 =====");
77 
      dbg_i2c_wr(MEM_ADDR, 16'h0006);  // select register
78 
      dbg_i2c_wr(MEM_DATA, 16'hcb54);  // write data
79 
      dbg_i2c_wr(MEM_CTL,  16'h0007);  // write register
80 
      repeat(20) @(posedge mclk);
81 
      if (r6 !== 16'hcb54)  tb_error("====== CPU REGISTERS (16b): Write R6 =====");
82 
 
83 200 olivier.gi 
 
84 154 olivier.gi 
      // RD/WR ACCESS: RAM (16b)
85 
      //--------------------------------------------------------
86 
 
87 
      // READ RAM
88 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
89 
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
90 
      dbg_i2c_rd(MEM_DATA);            // read data
91 
      if (dbg_i2c_buf !== 16'h1122)  tb_error("====== RAM (16b): Read @0x210 =====");
92 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0012));  // select memory address
93 
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
94 
      dbg_i2c_rd(MEM_DATA);            // read data
95 
      if (dbg_i2c_buf !== 16'h3344)  tb_error("====== RAM (16b): Read @0x212 =====");
96 
 
97 
      // WRITE RAM
98 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
99 
      dbg_i2c_wr(MEM_DATA, 16'ha976);  // write data
100 
      dbg_i2c_wr(MEM_CTL,  16'h0003);  // write memory
101 
      repeat(20) @(posedge mclk);
102 
      if (mem210 !== 16'ha976)  tb_error("====== RAM (16b): Write @0x210 =====");
103 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0012));  // select register
104 
      dbg_i2c_wr(MEM_DATA, 16'h8798);  // write data
105 
      dbg_i2c_wr(MEM_CTL,  16'h0003);  // write register
106 
      repeat(20) @(posedge mclk);
107 
      if (mem212 !== 16'h8798)  tb_error("====== RAM (16b): Write @0x212 =====");
108 
 
109 
 
110 
      // RD/WR ACCESS: RAM (8b)
111 
      //--------------------------------------------------------
112 
 
113 
      // READ RAM
114 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
115 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
116 
      dbg_i2c_rd(MEM_DATA);            // read data
117 
      if (dbg_i2c_buf !== 16'h0076)  tb_error("====== RAM (8b): Read @0x210 =====");
118 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0011));  // select memory address
119 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
120 
      dbg_i2c_rd(MEM_DATA);            // read data
121 
      if (dbg_i2c_buf !== 16'h00a9)  tb_error("====== RAM (8b): Read @0x211 =====");
122 
 
123 
      // WRITE RAM
124 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
125 
      dbg_i2c_wr(MEM_DATA, 16'h14b3);  // write data
126 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write memory
127 
      repeat(20) @(posedge mclk);
128 
      if (mem210 !== 16'ha9b3)  tb_error("====== RAM (8b): Write @0x210 =====");
129 
      dbg_i2c_wr(MEM_ADDR, (`PER_SIZE+16'h0011));  // select register
130 
      dbg_i2c_wr(MEM_DATA, 16'h25c4);  // write data
131 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write register
132 
      repeat(20) @(posedge mclk);
133 
      if (mem210 !== 16'hc4b3)  tb_error("====== RAM (8b): Write @0x211 =====");
134 
 
135 200 olivier.gi 
 
136 154 olivier.gi 
      // RD/WR ACCESS: ROM (16b)
137 
      //--------------------------------------------------------
138 
 
139 
      // READ ROM
140 200 olivier.gi 
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
141 154 olivier.gi 
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
142 
      dbg_i2c_rd(MEM_DATA);            // read data
143 
      if (dbg_i2c_buf !== 16'h5ab7)  tb_error("====== ROM (16b): Read @0xf834 =====");
144 200 olivier.gi 
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h02));  // select memory address
145 154 olivier.gi 
      dbg_i2c_wr(MEM_CTL,  16'h0001);  // read memory
146 
      dbg_i2c_rd(MEM_DATA);            // read data
147 
      if (dbg_i2c_buf !== 16'h6bc8)  tb_error("====== ROM (16b): Read @0xf836 =====");
148 
 
149 
      // WRITE ROM
150 
      dbg_i2c_wr(MEM_ADDR, 16'hffe0);  // select memory address
151 
      dbg_i2c_wr(MEM_DATA, 16'h7cd9);  // write data
152 
      dbg_i2c_wr(MEM_CTL,  16'h0003);  // write memory
153 
      repeat(20) @(posedge mclk);
154 
      if (irq_vect_00 !== 16'h7cd9)  tb_error("====== ROM (16b): Write @0xffe0 =====");
155 
      dbg_i2c_wr(MEM_ADDR, 16'hffe2);  // select register
156 
      dbg_i2c_wr(MEM_DATA, 16'h8dea);  // write data
157 
      dbg_i2c_wr(MEM_CTL,  16'h0003);  // write register
158 
      repeat(20) @(posedge mclk);
159 
      if (irq_vect_01 !== 16'h8dea)  tb_error("====== ROM (16b): Write @0xffe2 =====");
160 
 
161 
 
162 
      // RD/WR ACCESS: ROM (8b)
163 
      //--------------------------------------------------------
164 
 
165 
      // READ ROM
166 200 olivier.gi 
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
167 154 olivier.gi 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
168 
      dbg_i2c_rd(MEM_DATA);            // read data
169 
      if (dbg_i2c_buf !== 16'h00b7)  tb_error("====== ROM (8b): Read @0xf834 =====");
170 200 olivier.gi 
      dbg_i2c_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h01));  // select memory address
171 154 olivier.gi 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
172 
      dbg_i2c_rd(MEM_DATA);            // read data
173 
      if (dbg_i2c_buf !== 16'h005a)  tb_error("====== ROM (8b): Read @0xf835 =====");
174 
 
175 
      // WRITE ROM
176 
      dbg_i2c_wr(MEM_ADDR, 16'hffe0);  // select memory address
177 
      dbg_i2c_wr(MEM_DATA, 16'hb314);  // write data
178 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write memory
179 
      repeat(20) @(posedge mclk);
180 
      if (irq_vect_00 !== 16'h7c14)  tb_error("====== ROM (8b): Write @0xffe0 =====");
181 
      dbg_i2c_wr(MEM_ADDR, 16'hffe1);  // select register
182 
      dbg_i2c_wr(MEM_DATA, 16'hc425);  // write data
183 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write register
184 
      repeat(20) @(posedge mclk);
185 
      if (irq_vect_00 !== 16'h2514)  tb_error("====== ROM (8b): Write @0xffe1 =====");
186 
 
187 200 olivier.gi 
 
188 154 olivier.gi 
      // RD/WR ACCESS: PERIPHERALS (16b)
189 
      //--------------------------------------------------------
190 200 olivier.gi 
 
191 154 olivier.gi 
      // WRITE PERIPHERAL
192 
      dbg_i2c_wr(MEM_ADDR, 16'h0170);                        // select memory address
193 
      dbg_i2c_wr(MEM_DATA, 16'h9dc7);                        // write data
194 
      dbg_i2c_wr(MEM_CTL,  16'h0003);                        // write memory
195 
      repeat(20) @(posedge mclk);
196 
      if (timerA_0.tar !== 16'h9dc7)  tb_error("====== Peripheral (16b): Write @0x0170 =====");
197 
      dbg_i2c_wr(MEM_ADDR, 16'h0172);                        // select register
198 
      dbg_i2c_wr(MEM_DATA, 16'haed8);                        // write data
199 
      dbg_i2c_wr(MEM_CTL,  16'h0003);                        // write register
200 
      repeat(20) @(posedge mclk);
201 
      if (timerA_0.taccr0 !== 16'haed8)  tb_error("====== Peripheral (16b): Write @0x0172 =====");
202 
      dbg_i2c_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002));  // select memory address
203 
      dbg_i2c_wr(MEM_DATA, 16'hdead);                        // write data
204 
      dbg_i2c_wr(MEM_CTL,  16'h0003);                        // write memory
205 
      repeat(20) @(posedge mclk);
206 
      if (template_periph_16b_0.cntrl2 !== 16'hdead)  tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0002) =====");
207 
      dbg_i2c_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006));  // select memory address
208 
      dbg_i2c_wr(MEM_DATA, 16'hbeef);                        // write data
209 
      dbg_i2c_wr(MEM_CTL,  16'h0003);                        // write memory
210 
      repeat(20) @(posedge mclk);
211 
      if (template_periph_16b_0.cntrl4 !== 16'hbeef)  tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0006) =====");
212 
 
213 
      // READ PERIPHERAL
214 
      dbg_i2c_wr(MEM_ADDR, 16'h0170);                        // select memory address
215 
      dbg_i2c_wr(MEM_CTL,  16'h0001);                        // read memory
216 
      dbg_i2c_rd(MEM_DATA);                                  // read data
217 
      if (dbg_i2c_buf !== 16'h9dc7)  tb_error("====== Peripheral (16b): Read @0x0170 =====");
218 
      dbg_i2c_wr(MEM_ADDR, 16'h0172);                        // select memory address
219 
      dbg_i2c_wr(MEM_CTL,  16'h0001);                        // read memory
220 
      dbg_i2c_rd(MEM_DATA);                                  // read data
221 
      if (dbg_i2c_buf !== 16'haed8)  tb_error("====== Peripheral (16b): Read @0x0172 =====");
222 
      dbg_i2c_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002));  // select memory address
223 
      dbg_i2c_wr(MEM_CTL,  16'h0001);                        // read memory
224 
      dbg_i2c_rd(MEM_DATA);                                  // read data
225 
      repeat(20) @(posedge mclk);
226 
      if (dbg_i2c_buf !== 16'hdead)  tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0002) =====");
227 
      dbg_i2c_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006));  // select memory address
228 
      dbg_i2c_wr(MEM_CTL,  16'h0001);                        // read memory
229 
      dbg_i2c_rd(MEM_DATA);                                  // read data
230 
      repeat(20) @(posedge mclk);
231 
      if (dbg_i2c_buf !== 16'hbeef)  tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0006) =====");
232 
 
233 
 
234 
      // RD/WR ACCESS: PERIPHERAL (8b)
235 
      //--------------------------------------------------------
236 
 
237 
      // WRITE PERIPHERAL
238 
      dbg_i2c_wr(MEM_ADDR, 16'h0022);  // select memory address
239 
      dbg_i2c_wr(MEM_DATA, 16'hbfe9);  // write data
240 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write memory
241 
      repeat(20) @(posedge mclk);
242 
      if (gpio_0.p1dir !== 8'he9)  tb_error("====== Peripheral (8b): Write @0x0022 - test 1 =====");
243 
      if (gpio_0.p1ifg !== 8'h00)  tb_error("====== Peripheral (8b): Write @0x0022 - test 2=====");
244 
      dbg_i2c_wr(MEM_ADDR, 16'h0023);  // select register
245 
      dbg_i2c_wr(MEM_DATA, 16'hc0fa);  // write data
246 
      dbg_i2c_wr(MEM_CTL,  16'h000b);  // write register
247 
      repeat(20) @(posedge mclk);
248 
      if (gpio_0.p1dir !== 8'he9)  tb_error("====== Peripheral (8b): Write @0x0023 - test 1 =====");
249 
      if (gpio_0.p1ifg !== 8'hfa)  tb_error("====== Peripheral (8b): Write @0x0023 - test 2=====");
250 
 
251 
      // READ PERIPHERAL
252 
      dbg_i2c_wr(MEM_ADDR, 16'h0022);  // select memory address
253 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
254 
      dbg_i2c_rd(MEM_DATA);            // read data
255 
      if (dbg_i2c_buf !== 16'h00e9)  tb_error("====== Peripheral (8b): Read @0x0022 =====");
256 
      dbg_i2c_wr(MEM_ADDR, 16'h0023);  // select memory address
257 
      dbg_i2c_wr(MEM_CTL,  16'h0009);  // read memory
258 
      dbg_i2c_rd(MEM_DATA);            // read data
259 
      if (dbg_i2c_buf !== 16'h00fa)  tb_error("====== Peripheral (8b): Read @0x0023 =====");
260 
 
261 200 olivier.gi 
 
262 154 olivier.gi 
      stimulus_done = 1;
263 
`else
264 
 
265 202 olivier.gi 
       tb_skip_finish("|   (serial debug interface I2C not included)   |");
266 154 olivier.gi 
`endif
267 
`else
268 202 olivier.gi 
       tb_skip_finish("|      (serial debug interface not included)    |");
269 154 olivier.gi 
`endif
270 
   end

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