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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_mem.v] - Blame information for rev 202

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Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            DEBUG INTERFACE                                */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the debug interface:                                                 */
27 
/*                        - Check Memory RD/WR features.                     */
28 
/*                                                                           */
29 
/*  Note: The burst features are specific to the selected interface          */
30 
/*    (UART/JTAG) and are therefore tested in the dbg_uart/dbg_jtag patterns */
31 18 olivier.gi 
/*                                                                           */
32 
/* Author(s):                                                                */
33 
/*             - Olivier Girard,    olgirard@gmail.com                       */
34 
/*                                                                           */
35 
/*---------------------------------------------------------------------------*/
36 19 olivier.gi 
/* $Rev: 202 $                                                                */
37 
/* $LastChangedBy: olivier.girard $                                          */
38 
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
39 2 olivier.gi 
/*===========================================================================*/
40 
 
41 
`define LONG_TIMEOUT
42 200 olivier.gi 
 
43 2 olivier.gi 
initial
44 
   begin
45 
      $display(" ===============================================");
46 
      $display("|                 START SIMULATION              |");
47 
      $display(" ===============================================");
48 111 olivier.gi 
`ifdef DBG_EN
49 154 olivier.gi 
`ifdef DBG_UART
50 106 olivier.gi 
      #1 dbg_en = 1;
51 2 olivier.gi 
      repeat(30) @(posedge mclk);
52 
      stimulus_done = 0;
53 
 
54 
      // SEND UART SYNCHRONIZATION FRAME
55 
      dbg_uart_tx(DBG_SYNC);
56 
 
57 106 olivier.gi 
   `ifdef DBG_RST_BRK_EN
58 
      dbg_uart_wr(CPU_CTL,  16'h0002);  // RUN
59 
   `endif
60 200 olivier.gi 
 
61 2 olivier.gi 
      // RD/WR ACCESS: CPU REGISTERS (16b)
62 
      //--------------------------------------------------------
63 
 
64 
      // READ CPU REGISTERS
65 
      dbg_uart_wr(MEM_ADDR, 16'h0005);  // select register
66 
      dbg_uart_wr(MEM_CTL,  16'h0005);  // read register
67 
      dbg_uart_rd(MEM_DATA);            // read data
68 
      if (dbg_uart_buf !== 16'haaaa)  tb_error("====== CPU REGISTERS (16b): Read R5 =====");
69 
      dbg_uart_wr(MEM_ADDR, 16'h0006);  // select register
70 
      dbg_uart_wr(MEM_CTL,  16'h0005);  // read register
71 
      dbg_uart_rd(MEM_DATA);            // read data
72 
      if (dbg_uart_buf !== 16'hbbbb)  tb_error("====== CPU REGISTERS (16b): Read R6 =====");
73 
 
74 
      // WRITE CPU REGISTERS
75 
      dbg_uart_wr(MEM_ADDR, 16'h0005);  // select register
76 
      dbg_uart_wr(MEM_DATA, 16'hed32);  // write data
77 
      dbg_uart_wr(MEM_CTL,  16'h0007);  // write register
78 
      repeat(20) @(posedge mclk);
79 
      if (r5 !== 16'hed32)  tb_error("====== CPU REGISTERS (16b): Write R5 =====");
80 
      dbg_uart_wr(MEM_ADDR, 16'h0006);  // select register
81 
      dbg_uart_wr(MEM_DATA, 16'hcb54);  // write data
82 
      dbg_uart_wr(MEM_CTL,  16'h0007);  // write register
83 
      repeat(20) @(posedge mclk);
84 
      if (r6 !== 16'hcb54)  tb_error("====== CPU REGISTERS (16b): Write R6 =====");
85 
 
86 200 olivier.gi 
 
87 2 olivier.gi 
      // RD/WR ACCESS: RAM (16b)
88 
      //--------------------------------------------------------
89 
 
90 
      // READ RAM
91 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
92 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);  // read memory
93 
      dbg_uart_rd(MEM_DATA);            // read data
94 
      if (dbg_uart_buf !== 16'h1122)  tb_error("====== RAM (16b): Read @0x210 =====");
95 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012));  // select memory address
96 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);  // read memory
97 
      dbg_uart_rd(MEM_DATA);            // read data
98 
      if (dbg_uart_buf !== 16'h3344)  tb_error("====== RAM (16b): Read @0x212 =====");
99 
 
100 
      // WRITE RAM
101 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
102 2 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'ha976);  // write data
103 
      dbg_uart_wr(MEM_CTL,  16'h0003);  // write memory
104 
      repeat(20) @(posedge mclk);
105 
      if (mem210 !== 16'ha976)  tb_error("====== RAM (16b): Write @0x210 =====");
106 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0012));  // select register
107 2 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'h8798);  // write data
108 
      dbg_uart_wr(MEM_CTL,  16'h0003);  // write register
109 
      repeat(20) @(posedge mclk);
110 
      if (mem212 !== 16'h8798)  tb_error("====== RAM (16b): Write @0x212 =====");
111 
 
112 
 
113 
      // RD/WR ACCESS: RAM (8b)
114 
      //--------------------------------------------------------
115 
 
116 
      // READ RAM
117 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
118 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
119 
      dbg_uart_rd(MEM_DATA);            // read data
120 
      if (dbg_uart_buf !== 16'h0076)  tb_error("====== RAM (8b): Read @0x210 =====");
121 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011));  // select memory address
122 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
123 
      dbg_uart_rd(MEM_DATA);            // read data
124 
      if (dbg_uart_buf !== 16'h00a9)  tb_error("====== RAM (8b): Read @0x211 =====");
125 
 
126 
      // WRITE RAM
127 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0010));  // select memory address
128 2 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'h14b3);  // write data
129 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write memory
130 
      repeat(20) @(posedge mclk);
131 
      if (mem210 !== 16'ha9b3)  tb_error("====== RAM (8b): Write @0x210 =====");
132 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (`PER_SIZE+16'h0011));  // select register
133 2 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'h25c4);  // write data
134 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write register
135 
      repeat(20) @(posedge mclk);
136 
      if (mem210 !== 16'hc4b3)  tb_error("====== RAM (8b): Write @0x211 =====");
137 
 
138 200 olivier.gi 
 
139 2 olivier.gi 
      // RD/WR ACCESS: ROM (16b)
140 
      //--------------------------------------------------------
141 
 
142 
      // READ ROM
143 200 olivier.gi 
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
144 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);  // read memory
145 
      dbg_uart_rd(MEM_DATA);            // read data
146 
      if (dbg_uart_buf !== 16'h5ab7)  tb_error("====== ROM (16b): Read @0xf82e =====");
147 200 olivier.gi 
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h02));  // select memory address
148 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);  // read memory
149 
      dbg_uart_rd(MEM_DATA);            // read data
150 
      if (dbg_uart_buf !== 16'h6bc8)  tb_error("====== ROM (16b): Read @0xf830 =====");
151 
 
152 
      // WRITE ROM
153 
      dbg_uart_wr(MEM_ADDR, 16'hffe0);  // select memory address
154 
      dbg_uart_wr(MEM_DATA, 16'h7cd9);  // write data
155 
      dbg_uart_wr(MEM_CTL,  16'h0003);  // write memory
156 
      repeat(20) @(posedge mclk);
157 
      if (irq_vect_00 !== 16'h7cd9)  tb_error("====== ROM (16b): Write @0xffe0 =====");
158 
      dbg_uart_wr(MEM_ADDR, 16'hffe2);  // select register
159 
      dbg_uart_wr(MEM_DATA, 16'h8dea);  // write data
160 
      dbg_uart_wr(MEM_CTL,  16'h0003);  // write register
161 
      repeat(20) @(posedge mclk);
162 
      if (irq_vect_01 !== 16'h8dea)  tb_error("====== ROM (16b): Write @0xffe2 =====");
163 
 
164 
 
165 
      // RD/WR ACCESS: ROM (8b)
166 
      //--------------------------------------------------------
167 
 
168 
      // READ ROM
169 200 olivier.gi 
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h00));  // select memory address
170 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
171 
      dbg_uart_rd(MEM_DATA);            // read data
172 
      if (dbg_uart_buf !== 16'h00b7)  tb_error("====== ROM (8b): Read @0xf82e =====");
173 200 olivier.gi 
      dbg_uart_wr(MEM_ADDR, ('h10000-`PMEM_SIZE+'h01));  // select memory address
174 2 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
175 
      dbg_uart_rd(MEM_DATA);            // read data
176 
      if (dbg_uart_buf !== 16'h005a)  tb_error("====== ROM (8b): Read @0xf82f =====");
177 
 
178 
      // WRITE ROM
179 
      dbg_uart_wr(MEM_ADDR, 16'hffe0);  // select memory address
180 
      dbg_uart_wr(MEM_DATA, 16'hb314);  // write data
181 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write memory
182 
      repeat(20) @(posedge mclk);
183 
      if (irq_vect_00 !== 16'h7c14)  tb_error("====== ROM (8b): Write @0xffe0 =====");
184 
      dbg_uart_wr(MEM_ADDR, 16'hffe1);  // select register
185 
      dbg_uart_wr(MEM_DATA, 16'hc425);  // write data
186 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write register
187 
      repeat(20) @(posedge mclk);
188 
      if (irq_vect_00 !== 16'h2514)  tb_error("====== ROM (8b): Write @0xffe1 =====");
189 
 
190 200 olivier.gi 
 
191 2 olivier.gi 
      // RD/WR ACCESS: PERIPHERALS (16b)
192 
      //--------------------------------------------------------
193 200 olivier.gi 
 
194 2 olivier.gi 
      // WRITE PERIPHERAL
195 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, 16'h0170);                        // select memory address
196 
      dbg_uart_wr(MEM_DATA, 16'h9dc7);                        // write data
197 
      dbg_uart_wr(MEM_CTL,  16'h0003);                        // write memory
198 2 olivier.gi 
      repeat(20) @(posedge mclk);
199 
      if (timerA_0.tar !== 16'h9dc7)  tb_error("====== Peripheral (16b): Write @0x0170 =====");
200 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, 16'h0172);                        // select register
201 
      dbg_uart_wr(MEM_DATA, 16'haed8);                        // write data
202 
      dbg_uart_wr(MEM_CTL,  16'h0003);                        // write register
203 2 olivier.gi 
      repeat(20) @(posedge mclk);
204 
      if (timerA_0.taccr0 !== 16'haed8)  tb_error("====== Peripheral (16b): Write @0x0172 =====");
205 151 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002));  // select memory address
206 111 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'hdead);                        // write data
207 
      dbg_uart_wr(MEM_CTL,  16'h0003);                        // write memory
208 
      repeat(20) @(posedge mclk);
209 
      if (template_periph_16b_0.cntrl2 !== 16'hdead)  tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0002) =====");
210 151 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006));  // select memory address
211 111 olivier.gi 
      dbg_uart_wr(MEM_DATA, 16'hbeef);                        // write data
212 
      dbg_uart_wr(MEM_CTL,  16'h0003);                        // write memory
213 
      repeat(20) @(posedge mclk);
214 
      if (template_periph_16b_0.cntrl4 !== 16'hbeef)  tb_error("====== Peripheral (16b): Write @(DMEM_BASE-0x0070+0x0006) =====");
215 2 olivier.gi 
 
216 
      // READ PERIPHERAL
217 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, 16'h0170);                        // select memory address
218 
      dbg_uart_wr(MEM_CTL,  16'h0001);                        // read memory
219 
      dbg_uart_rd(MEM_DATA);                                  // read data
220 2 olivier.gi 
      if (dbg_uart_buf !== 16'h9dc7)  tb_error("====== Peripheral (16b): Read @0x0170 =====");
221 111 olivier.gi 
      dbg_uart_wr(MEM_ADDR, 16'h0172);                        // select memory address
222 
      dbg_uart_wr(MEM_CTL,  16'h0001);                        // read memory
223 
      dbg_uart_rd(MEM_DATA);                                  // read data
224 2 olivier.gi 
      if (dbg_uart_buf !== 16'haed8)  tb_error("====== Peripheral (16b): Read @0x0172 =====");
225 151 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0002));  // select memory address
226 111 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);                        // read memory
227 
      dbg_uart_rd(MEM_DATA);                                  // read data
228 
      repeat(20) @(posedge mclk);
229 
      if (dbg_uart_buf !== 16'hdead)  tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0002) =====");
230 151 olivier.gi 
      dbg_uart_wr(MEM_ADDR, (((`DMEM_BASE-16'h0070)&16'h7ff8)+16'h0006));  // select memory address
231 111 olivier.gi 
      dbg_uart_wr(MEM_CTL,  16'h0001);                        // read memory
232 
      dbg_uart_rd(MEM_DATA);                                  // read data
233 
      repeat(20) @(posedge mclk);
234 
      if (dbg_uart_buf !== 16'hbeef)  tb_error("====== Peripheral (16b): Read @(DMEM_BASE-0x0070+0x0006) =====");
235 2 olivier.gi 
 
236 
 
237 
      // RD/WR ACCESS: PERIPHERAL (8b)
238 
      //--------------------------------------------------------
239 
 
240 
      // WRITE PERIPHERAL
241 
      dbg_uart_wr(MEM_ADDR, 16'h0022);  // select memory address
242 
      dbg_uart_wr(MEM_DATA, 16'hbfe9);  // write data
243 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write memory
244 
      repeat(20) @(posedge mclk);
245 
      if (gpio_0.p1dir !== 8'he9)  tb_error("====== Peripheral (8b): Write @0x0022 - test 1 =====");
246 
      if (gpio_0.p1ifg !== 8'h00)  tb_error("====== Peripheral (8b): Write @0x0022 - test 2=====");
247 
      dbg_uart_wr(MEM_ADDR, 16'h0023);  // select register
248 
      dbg_uart_wr(MEM_DATA, 16'hc0fa);  // write data
249 
      dbg_uart_wr(MEM_CTL,  16'h000b);  // write register
250 
      repeat(20) @(posedge mclk);
251 
      if (gpio_0.p1dir !== 8'he9)  tb_error("====== Peripheral (8b): Write @0x0023 - test 1 =====");
252 
      if (gpio_0.p1ifg !== 8'hfa)  tb_error("====== Peripheral (8b): Write @0x0023 - test 2=====");
253 
 
254 
      // READ PERIPHERAL
255 
      dbg_uart_wr(MEM_ADDR, 16'h0022);  // select memory address
256 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
257 
      dbg_uart_rd(MEM_DATA);            // read data
258 
      if (dbg_uart_buf !== 16'h00e9)  tb_error("====== Peripheral (8b): Read @0x0022 =====");
259 
      dbg_uart_wr(MEM_ADDR, 16'h0023);  // select memory address
260 
      dbg_uart_wr(MEM_CTL,  16'h0009);  // read memory
261 
      dbg_uart_rd(MEM_DATA);            // read data
262 
      if (dbg_uart_buf !== 16'h00fa)  tb_error("====== Peripheral (8b): Read @0x0023 =====");
263 
 
264 200 olivier.gi 
 
265 2 olivier.gi 
      stimulus_done = 1;
266 111 olivier.gi 
`else
267 
 
268 202 olivier.gi 
       tb_skip_finish("|   (serial debug interface UART not included)  |");
269 154 olivier.gi 
`endif
270 
`else
271 202 olivier.gi 
       tb_skip_finish("|      (serial debug interface not included)    |");
272 111 olivier.gi 
`endif
273 2 olivier.gi 
   end

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