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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_onoff_asic.v] - Blame information for rev 202

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1 134 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            DEBUG INTERFACE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the debug interface:                                                 */
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/*                           - CPU Control features.                         */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 95 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
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/*===========================================================================*/
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39
   integer test_nr;
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   integer test_var;
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   integer dco_clk_counter;
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   always @ (negedge dco_clk)
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     dco_clk_counter <=  dco_clk_counter+1;
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   integer dbg_clk_counter;
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   always @ (negedge dbg_clk)
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     dbg_clk_counter <=  dbg_clk_counter+1;
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50 202 olivier.gi
 
51 134 olivier.gi
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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`ifdef DBG_EN
57 154 olivier.gi
`ifdef DBG_UART
58 180 olivier.gi
  `ifdef ASIC_CLOCKING
59 134 olivier.gi
      test_nr = 0;
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      #1 dbg_en = 0;
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      repeat(30) @(posedge dco_clk);
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      stimulus_done = 0;
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64
      // Make sure the CPU always starts executing when the
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      // debug interface is disabled during POR.
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      // Also make sure that the debug interface clock is stopped
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      // and that it is under reset
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      //--------------------------------------------------------
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      dbg_en  = 0;
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      test_nr = 1;
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      @(negedge dco_clk) dbg_clk_counter = 0;
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      repeat(300) @(posedge dco_clk);
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      if (r14 === 16'h0000)         tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
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      if (dbg_clk_counter !== 0)    tb_error("====== DBG_CLK is not stopped (test 1) =====");
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      if (dbg_rst          == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
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      test_var = r14;
79 202 olivier.gi
 
80
 
81 134 olivier.gi
      // Make sure that enabling the debug interface after the POR
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      // don't stop the cpu
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      // Also make sure that the debug interface clock is running
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      // and that its reset is released
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      //--------------------------------------------------------
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      dbg_en  = 1;
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      test_nr = 2;
88 202 olivier.gi
 
89 134 olivier.gi
      @(negedge dco_clk) dbg_clk_counter = 0;
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91
      repeat(300) @(posedge dco_clk);
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      if (r14 === test_var[15:0])   tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
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      if (dbg_clk_counter  == 0)    tb_error("====== DBG_CLK is not running (test 5) =====");
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      if (dbg_rst         !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
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96 202 olivier.gi
 
97 134 olivier.gi
      // Make sure that disabling the CPU with debug enabled
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      // will stop the CPU
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      // Also make sure that the debug interface clock is stopped
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      // and that it is NOT under reset
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      //--------------------------------------------------------
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      cpu_en  = 0;
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      dbg_en  = 1;
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      test_nr = 3;
105 202 olivier.gi
 
106 134 olivier.gi
      #(6*50);
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      test_var = r14;
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      dbg_clk_counter = 0;
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      #(300*50);
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      if (r14 !== test_var[15:0])   tb_error("====== CPU is not stopped (test 7) =====");
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      if (dbg_clk_counter !== 0)    tb_error("====== DBG_CLK is not running (test 8) =====");
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      if (dbg_rst         !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
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      cpu_en  = 1;
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      repeat(6) @(negedge dco_clk);
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118 202 olivier.gi
 
119 134 olivier.gi
      // Create POR with debug enable and observe the
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      // behavior depending on the DBG_RST_BRK_EN define
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      //--------------------------------------------------------
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      dbg_en  = 1;
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      test_nr = 4;
124 202 olivier.gi
 
125 134 olivier.gi
      @(posedge dco_clk); // Generate POR
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      reset_n = 1'b0;
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      @(posedge dco_clk);
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      reset_n = 1'b1;
129 202 olivier.gi
 
130 134 olivier.gi
      repeat(300) @(posedge dco_clk);
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  `ifdef DBG_RST_BRK_EN
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      if (r14 !== 16'h0000)       tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
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  `else
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      if (r14 === 16'h0000)       tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
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  `endif
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      // Send uart synchronization frame
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      dbg_uart_tx(DBG_SYNC);
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      // Check CPU_CTL reset value
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      dbg_uart_rd(CPU_CTL);
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  `ifdef DBG_RST_BRK_EN
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      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
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  `else
145 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 4 =====");
146 134 olivier.gi
  `endif
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      // Make sure that DBG_EN resets the debug interface
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      //--------------------------------------------------------
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      test_nr = 5;
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      // Let the CPU run
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      dbg_uart_wr(CPU_CTL,  16'h0002);
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      repeat(300) @(posedge dco_clk);
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      dbg_uart_wr(CPU_CTL,   16'h0000);
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      dbg_uart_wr(MEM_DATA,  16'haa55);
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      dbg_uart_rd(CPU_CTL);
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      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 5 =====");
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      dbg_uart_rd(MEM_DATA);
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      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 6 =====");
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164 202 olivier.gi
 
165 134 olivier.gi
      test_var = r14;  // Backup the current register value
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167 202 olivier.gi
 
168 134 olivier.gi
      @(posedge dco_clk); // Resets the debug interface
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      dbg_en = 1'b0;
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      repeat(2) @(posedge dco_clk);
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      dbg_en = 1'b1;
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      // Make sure that the register was not reseted
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      if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN -  test 7 =====");
175 202 olivier.gi
      repeat(2) @(posedge dco_clk);
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177 134 olivier.gi
      // Send uart synchronization frame
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      dbg_uart_tx(DBG_SYNC);
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180
      // Check CPU_CTL reset value
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      dbg_uart_rd(CPU_CTL);
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  `ifdef DBG_RST_BRK_EN
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      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
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  `else
185 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
186 134 olivier.gi
  `endif
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      dbg_uart_rd(MEM_DATA);
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      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
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190
 
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      // Make sure that RESET_N resets the debug interface
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      //--------------------------------------------------------
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      test_nr = 6;
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195
      // Let the CPU run
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      dbg_uart_wr(CPU_CTL,  16'h0002);
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198
      repeat(300) @(posedge dco_clk);
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      dbg_uart_wr(CPU_CTL,   16'h0000);
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      dbg_uart_wr(MEM_DATA,  16'haa55);
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      dbg_uart_rd(CPU_CTL);
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      if (dbg_uart_buf !== 16'h0000)  tb_error("====== CPU_CTL write access failed  - test 10 =====");
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      dbg_uart_rd(MEM_DATA);
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      if (dbg_uart_buf !== 16'haa55)  tb_error("====== MEM_DATA write access failed - test 11 =====");
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      test_nr = 7;
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      @(posedge dco_clk); // Generates POR
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      reset_n = 1'b0;
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      repeat(2) @(posedge dco_clk);
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      reset_n = 1'b1;
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      // Make sure that the register was reseted
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      if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N -  test 12 =====");
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      repeat(2) @(posedge dco_clk);
216 202 olivier.gi
 
217 134 olivier.gi
      // Send uart synchronization frame
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      dbg_uart_tx(DBG_SYNC);
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220
      test_nr = 8;
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222
      // Check CPU_CTL reset value
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      dbg_uart_rd(CPU_CTL);
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  `ifdef DBG_RST_BRK_EN
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      if (dbg_uart_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
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  `else
227 202 olivier.gi
      if (dbg_uart_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value -  test 8 =====");
228 134 olivier.gi
  `endif
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      dbg_uart_rd(MEM_DATA);
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      if (dbg_uart_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
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232 202 olivier.gi
 
233 134 olivier.gi
      // Let the CPU run
234
      dbg_uart_wr(CPU_CTL,  16'h0002);
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236
      test_nr = 9;
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      // Generate IRQ to terminate the test pattern
239 200 olivier.gi
      irq[`IRQ_NR-15] = 1'b1;
240 134 olivier.gi
      @(r13);
241 200 olivier.gi
      irq[`IRQ_NR-15] = 1'b0;
242 202 olivier.gi
 
243 134 olivier.gi
      stimulus_done = 1;
244
 
245
  `else
246 202 olivier.gi
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
247 134 olivier.gi
  `endif
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`else
249 202 olivier.gi
      tb_skip_finish("|   (serial debug interface UART not included)  |");
250 154 olivier.gi
`endif
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`else
252 202 olivier.gi
      tb_skip_finish("|      (serial debug interface not included)    |");
253 134 olivier.gi
`endif
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   end

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