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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dma_lpm1_asic.v] - Blame information for rev 202

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1 202 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                  CPU LOW POWER MODES & DMA TRANSFER                       */
25
/*---------------------------------------------------------------------------*/
26
/* Test DMA transfer with the CPU Low Power modes:                           */
27
/*                                                                           */
28
/*                      - LPM0       <=>  CPUOFF                             */
29
/*                      - LPM1       <=>  CPUOFF + SCG0                      */
30
/*                      - LPM2       <=>  CPUOFF +        SCG1               */
31
/*                      - LPM3       <=>  CPUOFF + SCG0 + SCG1               */
32
/*                      - LPM4       <=>  CPUOFF + SCG0 + SCG1 + OSCOFF      */
33
/*                                                                           */
34
/*                                                                           */
35
/* Reminder about config registers:                                          */
36
/*                                                                           */
37
/*                      - CPUOFF     <=>  turns off CPU.                     */
38
/*                      - SCG0       <=>  turns off DCO.                     */
39
/*                      - SCG1       <=>  turns off SMCLK.                   */
40
/*                      - OSCOFF     <=>  turns off LFXT_CLK.                */
41
/*                                                                           */
42
/*                      - DMA_CPUOFF <=>  allow DMA to turn on MCLK          */
43
/*                      - DMA_SCG0   <=>  allow DMA to turn on DCO           */
44
/*                      - DMA_SCG1   <=>  allow DMA to turn on SMCLK         */
45
/*                      - DMA_OSCOFF <=>  allow DMA to turn on LFXT_CLK      */
46
/*                                                                           */
47
/* Author(s):                                                                */
48
/*             - Olivier Girard,    olgirard@gmail.com                       */
49
/*                                                                           */
50
/*---------------------------------------------------------------------------*/
51
/* $Rev: 95 $                                                                */
52
/* $LastChangedBy: olivier.girard $                                          */
53
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $          */
54
/*===========================================================================*/
55
 
56
`define VERY_LONG_TIMEOUT
57
 
58
reg     dma_loop_enable;
59
integer dma_loop_nr;
60
integer cfg_idx;
61
 
62
integer dco_clk_cnt;
63
always @(negedge dco_clk)
64
  dco_clk_cnt <= dco_clk_cnt+1;
65
 
66
integer mclk_dma_cnt;
67
always @(negedge mclk)
68
  mclk_dma_cnt <= mclk_dma_cnt+1;
69
 
70
integer mclk_cpu_cnt;
71
always @(negedge tb_openMSP430.dut.cpu_mclk)
72
  mclk_cpu_cnt <= mclk_cpu_cnt+1;
73
 
74
integer smclk_cnt;
75
always @(negedge smclk)
76
  smclk_cnt <= smclk_cnt+1;
77
 
78
integer aclk_cnt;
79
always @(negedge aclk)
80
  aclk_cnt <= aclk_cnt+1;
81
 
82
integer inst_cnt;
83
always @(inst_number)
84
  inst_cnt <= inst_cnt+1;
85
 
86
// Wakeup synchronizer to generate IRQ
87
reg [1:0] wkup2_sync;
88
always @(posedge mclk or posedge puc_rst)
89
  if (puc_rst) wkup2_sync <= 2'b00;
90
  else         wkup2_sync <= {wkup2_sync[0], wkup[2]};
91
 
92
always @(wkup2_sync)
93
  irq[`IRQ_NR-14] = wkup2_sync[1]; // IRQ-2
94
 
95
// Wakeup synchronizer to generate IRQ
96
reg [1:0] wkup3_sync;
97
always @(posedge mclk or posedge puc_rst)
98
  if (puc_rst) wkup3_sync <= 2'b00;
99
  else         wkup3_sync <= {wkup3_sync[0], wkup[3]};
100
 
101
always @(wkup3_sync)
102
  irq[`IRQ_NR-13] = wkup3_sync[1]; // IRQ-3
103
 
104
initial
105
   begin
106
      $display(" ===============================================");
107
      $display("|                 START SIMULATION              |");
108
      $display(" ===============================================");
109
`ifdef DMA_IF_EN
110
      // Disable automatic DMA verification
111
      #10;
112
      dma_verif_on = 0;
113
      repeat(5) @(posedge mclk);
114
      stimulus_done = 0;
115
 
116
      irq[`IRQ_NR-14]  = 0; // IRQ-2
117
      wkup[2] = 0;
118
 
119
      irq[`IRQ_NR-13]  = 0; // IRQ-3
120
      wkup[3] = 0;
121
 
122
 
123
`ifdef ASIC_CLOCKING
124
`ifdef CPUOFF_EN
125
 
126
      //--------------------------------------------------------
127
      // ACTIVE
128
      //--------------------------------------------------------
129
      @(r15==16'h1001);
130
      $display("");
131
      $display("\nACTIVE                         -  NO DMA");
132
 
133
      //           DCO_CLK, MCLK_CPU, MCLK_DMA, SMCLK, ACLK1, ACLK2, INST, DMA_NR
134
      clock_check(   100  ,   100   ,   100   ,  100 ,   4  ,  100 ,  60 ,   0    );
135
 
136
 
137
      // Check clocks for each possible DMA wakeup configuration
138
      for ( cfg_idx=0; cfg_idx < 16; cfg_idx=cfg_idx+1)
139
        begin
140
           @(r15==(16'h3000 + cfg_idx));
141
           $display("\nLPM1 (CPUOFF+SCG0) -  {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF}={%d, %d, %d, %d}\n", cfg_idx[3], cfg_idx[2], cfg_idx[1], cfg_idx[0]);
142
 
143
           //                                                {SCG1 , SCG0 , OSCOFF }
144
           full_lpm_clock_check ( lpm_clocks_status         ({1'b0 , 1'b1 ,  1'b0  }),                                                       // Get running clocks in low power mode
145
 
146
           //                                                {SCG1 , SCG0 , OSCOFF }  { DMA_SCG1 , DMA_SCG0 , DMA_OSCOFF, DMA_CPUOFF }
147
                                  lmp_clocks_status_dma_wkup({1'b0 , 1'b1 ,  1'b0  }, {cfg_idx[3],cfg_idx[2], cfg_idx[1], cfg_idx[0] }));    // Get running clocks in low power mode with DMA wake-up
148
        end
149
 
150
      $display("");
151
`else
152
      tb_skip_finish("|   (CPUOFF low power mode should be enabled)   |");
153
`endif
154
`else
155
      tb_skip_finish("|   (this test is not supported in FPGA mode)   |");
156
`endif
157
`else
158
      tb_skip_finish("|      (DMA interface support not included)     |");
159
`endif
160
 
161
      stimulus_done = 1;
162
   end
163
 
164
//------------------------------------------------------
165
// Clock check function
166
//------------------------------------------------------
167
task clock_check;
168
 
169
   input integer dco_val;
170
   input integer mclk_cpu_val;
171
   input integer mclk_dma_val;
172
   input integer smclk_val;
173
   input integer aclk_val1;
174
   input integer aclk_val2;
175
   input integer inst_val;
176
   input integer dma_val;
177
 
178
   begin
179
  `ifdef LFXT_DOMAIN
180
      if (aclk_val1 != 0) @(posedge aclk);
181
  `endif
182
      tb_idx = 777;
183
      #(100*50);
184
      dco_clk_cnt  = 0;
185
      mclk_cpu_cnt = 0;
186
      mclk_dma_cnt = 0;
187
      smclk_cnt    = 0;
188
      tb_idx = 888;
189
      aclk_cnt     = 0;
190
      inst_cnt     = 0;
191
      dma_loop_nr  = 0;
192
      #(100*50);
193
      if (dco_clk_cnt  !== dco_val)        tb_error("====== DCO_CLK   CHECK FAILED =====");
194
      if (mclk_cpu_cnt !== mclk_cpu_val)   tb_error("====== MCLK CPU  CHECK FAILED =====");
195
      if (mclk_dma_cnt !== mclk_dma_val)   tb_error("====== MCLK DMA  CHECK FAILED =====");
196
      if (smclk_cnt    !== smclk_val)      tb_error("====== SMCLK     CHECK FAILED =====");
197
  `ifdef LFXT_DOMAIN
198
      if (aclk_cnt     !== aclk_val1)      tb_error("====== ACLK1     CHECK FAILED =====");
199
  `else
200
      if (aclk_cnt     !== aclk_val2)      tb_error("====== ACLK2     CHECK FAILED =====");
201
  `endif
202
      if (inst_cnt     <   inst_val)       tb_error("====== INST_NR   CHECK FAILED =====");
203
      if (dma_loop_nr  !== dma_val)        tb_error("====== DMA_NR    CHECK FAILED =====");
204
      dco_clk_cnt  = 0;
205
      mclk_cpu_cnt = 0;
206
      mclk_dma_cnt = 0;
207
      smclk_cnt    = 0;
208
      aclk_cnt     = 0;
209
      inst_cnt     = 0;
210
      dma_loop_nr  = 0;
211
   end
212
 
213
endtask
214
 
215
//------------------------------------------------------
216
// Check Clocks for the whole LPM sequence
217
//------------------------------------------------------
218
 
219
task full_lpm_clock_check;
220
   input [2:0] lpm_clock_status;           // { SMCLK , DCO_CLK , ACLK }
221
   input [3:0] lpm_clock_status_dma_wkup;  // { SMCLK , DCO_CLK , ACLK , MCLK_DMA }
222
 
223
   integer  lpm_dco       , lpm_mclk_cpu       , lpm_mclk_dma       , lpm_smclk       , lpm_aclk1       , lpm_aclk2       , lpm_inst       , lpm_dma_nr       ;
224
   integer  dma_nowkup_dco, dma_nowkup_mclk_cpu, dma_nowkup_mclk_dma, dma_nowkup_smclk, dma_nowkup_aclk1, dma_nowkup_aclk2, dma_nowkup_inst, dma_nowkup_dma_nr;
225
   integer  dma_wkup_dco  , dma_wkup_mclk_cpu  , dma_wkup_mclk_dma  , dma_wkup_smclk  , dma_wkup_aclk1  , dma_wkup_aclk2  , dma_wkup_inst  , dma_wkup_dma_nr  ;
226
 
227
   begin
228
      // Initialize target values
229
      lpm_dco       =0; lpm_mclk_cpu       =0; lpm_mclk_dma       =0; lpm_smclk       =0; lpm_aclk1       =0; lpm_aclk2       =0; lpm_inst       =0; lpm_dma_nr       =0;
230
      dma_nowkup_dco=0; dma_nowkup_mclk_cpu=0; dma_nowkup_mclk_dma=0; dma_nowkup_smclk=0; dma_nowkup_aclk1=0; dma_nowkup_aclk2=0; dma_nowkup_inst=0; dma_nowkup_dma_nr=0;
231
      dma_wkup_dco  =0; dma_wkup_mclk_cpu  =0; dma_wkup_mclk_dma  =0; dma_wkup_smclk  =0; dma_wkup_aclk1  =0; dma_wkup_aclk2  =0; dma_wkup_inst  =0; dma_wkup_dma_nr  =0;
232
 
233
      // Update depending on running clocks during the low-power mode (no DMA)
234
      if (lpm_clock_status[0])          begin lpm_aclk1           =   4; lpm_aclk2           = 100; end
235
      if (lpm_clock_status[1])          begin lpm_dco             = 100; lpm_mclk_cpu        =   0; end
236
      if (lpm_clock_status[2])          begin lpm_smclk           = 100;                            end
237
 
238
      // Update depending on running clocks during the low-power mode (with DMA, with wakeup)
239
      if (lpm_clock_status_dma_wkup[0]) begin dma_wkup_mclk_dma   = 100;                            end else begin dma_wkup_mclk_dma   = lpm_mclk_dma;                                     end
240
      if (lpm_clock_status_dma_wkup[1]) begin dma_wkup_aclk1      =   4; dma_wkup_aclk2      = 100; end else begin dma_wkup_aclk1      = lpm_aclk1   ; dma_wkup_aclk2      = lpm_aclk2   ; end
241
      if (lpm_clock_status_dma_wkup[2]) begin dma_wkup_dco        = 100; dma_wkup_mclk_cpu   =   0; end else begin dma_wkup_dco        = lpm_dco     ; dma_wkup_mclk_cpu   = lpm_mclk_cpu; end
242
      if (lpm_clock_status_dma_wkup[3]) begin dma_wkup_smclk      = 100;                            end else begin dma_wkup_smclk      = lpm_smclk   ;                                     end
243
      if (dma_wkup_smclk == 100)        begin dma_wkup_dma_nr     = dma_wkup_mclk_dma;              end
244
 
245
      // Update depending on running clocks during the low-power mode (with DMA, no wakeup)
246
      if ((lpm_smclk == 100) &
247
           lpm_clock_status_dma_wkup[0]) begin dma_nowkup_mclk_dma = 100;                                                      end
248
      if  (lpm_smclk == 100)             begin dma_nowkup_dma_nr   = dma_nowkup_mclk_dma;                                      end
249
      if  (lpm_smclk == 100)             begin dma_nowkup_aclk1    = dma_wkup_aclk1;        dma_nowkup_aclk2 = dma_wkup_aclk2; end
250
      else                               begin dma_nowkup_aclk1    = lpm_aclk1;             dma_nowkup_aclk2 = lpm_aclk2;      end
251
 
252
      //---------- NO DMA                             - CHECK CLOCK STATUS  -------------//
253
      $display("                                      - NO DMA");
254
      clock_check(lpm_dco,      lpm_mclk_cpu,      lpm_mclk_dma,      lpm_smclk,      lpm_aclk1,      lpm_aclk2,      lpm_inst,      lpm_dma_nr      );
255
 
256
      //---------- PERFORM DMA TRANSFER NO WAKEUP     - CHECK CLOCK STATUS  -------------//
257
      $display("                                      - WITH DMA, NO WAKE-UP");
258
      dma_wkup        = 0;
259
      dma_loop_enable = 1;
260
      tb_idx = 666;
261
      clock_check(lpm_dco,      lpm_mclk_cpu,      dma_nowkup_mclk_dma,      lpm_smclk,      dma_nowkup_aclk1, dma_nowkup_aclk2, lpm_inst,      dma_nowkup_dma_nr );
262
      tb_idx = 999;
263
      dma_loop_enable = 0;
264
      dma_wkup        = 0;
265
      #100;
266
      dma_tfx_cancel  = 1;
267
      #100;
268
      dma_tfx_cancel  = 0;
269
      #100;
270
 
271
      //---------- NO DMA                             - CHECK CLOCK STATUS  -------------//
272
      $display("                                      - NO DMA");
273
      clock_check(lpm_dco,      lpm_mclk_cpu,      lpm_mclk_dma,      lpm_smclk,      lpm_aclk1,      lpm_aclk2,      lpm_inst,      lpm_dma_nr      );
274
 
275
      //---------- PERFORM DMA TRANSFER WITH WAKEUP   - CHECK CLOCK STATUS  -------------//
276
      $display("                                      - WITH DMA, WITH WAKE-UP");
277
      dma_wkup        = 1;
278
      dma_loop_enable = 1;
279
      clock_check(dma_wkup_dco, dma_wkup_mclk_cpu, dma_wkup_mclk_dma, dma_wkup_smclk, dma_wkup_aclk1, dma_wkup_aclk2, dma_wkup_inst, dma_wkup_dma_nr   );
280
      dma_loop_enable = 0;
281
      dma_wkup        = 0;
282
      #100;
283
      dma_tfx_cancel  = 1;
284
      #100;
285
      dma_tfx_cancel  = 0;
286
      #100;
287
 
288
      //---------- NO DMA                             - CHECK CLOCK STATUS  -------------//
289
      $display("                                      - NO DMA");
290
      clock_check(lpm_dco,      lpm_mclk_cpu,      lpm_mclk_dma,      lpm_smclk,      lpm_aclk1,      lpm_aclk2,      lpm_inst,      lpm_dma_nr      );
291
 
292
      //---------- PORT2 IRQ            - EXITING POWER MODE  -------------//
293
      irq_exit_lp_mode;
294
   end
295
 
296
endtask
297
 
298
//------------------------------------------------------
299
// ENABLE DISABLE DMA TRANSFERS
300
//------------------------------------------------------
301
// Note that we synchronize DMA transfer with SMCLK
302
 
303
reg [15:0] dma_loop_val;
304
reg        dma_loop_enable_old;
305
initial
306
  begin
307
     dma_loop_enable=0;
308
     dma_loop_val=0;
309
     dma_loop_nr=0;
310
     forever
311
       begin
312
          dma_loop_enable_old=dma_loop_enable;
313
          if (~dma_loop_enable) @(posedge dma_loop_enable);
314
          if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
315
          if (~dma_tfx_cancel) dma_write_16b(16'h0000-`PMEM_SIZE, dma_loop_val, 1'b0);
316
          if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
317
          if (~dma_tfx_cancel)
318
            begin
319
               dma_loop_enable_old=dma_loop_enable;
320
               if (~dma_loop_enable) @(posedge dma_loop_enable);
321
               if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
322
               if (~dma_tfx_cancel) dma_read_16b(16'h0000-`PMEM_SIZE,  dma_loop_val, 1'b0);
323
               if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
324
            end
325
          dma_loop_val=dma_loop_val+1;
326
       end
327
  end
328
 
329
//------------------------------------------------------
330
// IRQ to exit Low Power Mode
331
//------------------------------------------------------
332
task irq_exit_lp_mode;
333
 
334
   begin
335
      wkup[3] = 1'b1;
336
      @(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
337
      #(10*50);
338
      @(r13==16'hbbbb);
339
      wkup[3] = 1'b0;
340
   end
341
 
342
endtask
343
 
344
 
345
//----------------------------------------------------------------------------------//
346
//                    DETECT CLOCKS RESTORED WITH DMA WAKEUP                        //
347
//----------------------------------------------------------------------------------//
348
function [3:0] lmp_clocks_status_dma_wkup;
349
 
350
   input [3:0] lpm_config;           // {  SCG1  ,   SCG0  ,   OSCOFF               }
351
   input [3:0] dma_lpm_config;       // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
352
 
353
   reg   [3:0] combined_lpm_config;  // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
354
   reg   [2:0] lpm_rtl_support;      // {  SCG1  ,   SCG0  ,   OSCOFF               }
355
   begin
356
 
357
      // Combine low power configuration with the DMA wakeup one
358
      assign combined_lpm_config  =  dma_lpm_config | {~lpm_config, 1'b0};
359
 
360
      // Get supported RTL configuration
361
      lpm_rtl_support =                   3'h0;
362
     `ifdef OSCOFF_EN
363
      lpm_rtl_support = lpm_rtl_support | 3'h1;
364
     `endif
365
     `ifdef SCG0_EN
366
      lpm_rtl_support = lpm_rtl_support | 3'h2;
367
     `endif
368
     `ifdef SCG1_EN
369
      lpm_rtl_support = lpm_rtl_support | 3'h4;
370
     `endif
371
 
372
      // Depending on RTL configuration, figure out which clocks are running when a DMA wakeup is applied
373
      case(lpm_rtl_support)
374
        //                                               SMCLK            ,      DCO_CLK           ,       ACLK             ,      MCLK_DMA
375
        4'b000 :   lmp_clocks_status_dma_wkup  = {        1'b1            ,       1'b1             ,       1'b1             , combined_lpm_config[0] };
376
 
377
        4'b001 :   lmp_clocks_status_dma_wkup  = {        1'b1            ,       1'b1             , combined_lpm_config[1] , combined_lpm_config[0] };
378
 
379
        4'b010 : begin
380
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[2] , combined_lpm_config[2] ,       1'b1             , combined_lpm_config[0] };
381
                   lmp_clocks_status_dma_wkup  = {        1'b1            ,       1'b1             ,       1'b1             , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
382
                 end
383
        4'b011 : begin
384
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[2] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
385
                   lmp_clocks_status_dma_wkup  = {        1'b1            ,       1'b1             ,       1'b1             , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
386
                 end
387
        4'b100 :   lmp_clocks_status_dma_wkup  = { combined_lpm_config[3] ,       1'b1             ,       1'b1             , combined_lpm_config[0] };
388
 
389
        4'b101 :   lmp_clocks_status_dma_wkup  = { combined_lpm_config[3] ,       1'b1             , combined_lpm_config[1] , combined_lpm_config[0] };
390
 
391
        4'b110 : begin
392
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[3] , combined_lpm_config[2] ,       1'b1             , combined_lpm_config[0] };
393
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[2] ,       1'b1             ,       1'b1             , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
394
                 end
395
        4'b111 : begin
396
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[3] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
397
                   lmp_clocks_status_dma_wkup  = { combined_lpm_config[2] ,       1'b1             ,       1'b1             , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
398
                 end
399
      endcase
400
 
401
    // If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
402
    `ifdef LFXT_DOMAIN
403
    `else
404
      lmp_clocks_status_dma_wkup[1] = lmp_clocks_status_dma_wkup[2];
405
    `endif
406
 
407
   end
408
endfunction
409
 
410
//----------------------------------------------------------------------------------//
411
//                    DETECT CLOCKS RUNNING DURING LOW-POWER-MODE                   //
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//----------------------------------------------------------------------------------//
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function [2:0] lpm_clocks_status;
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415
   input [2:0] lpm_config;           // {  SCG1  ,   SCG0  ,   OSCOFF  }
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417
   reg   [2:0] lpm_rtl_support;      // {  SCG1  ,   SCG0  ,   OSCOFF  }
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   begin
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      // Get supported RTL configuration
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      lpm_rtl_support =                   3'h0;
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     `ifdef OSCOFF_EN
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      lpm_rtl_support = lpm_rtl_support | 3'h1;
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     `endif
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     `ifdef SCG0_EN
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      lpm_rtl_support = lpm_rtl_support | 3'h2;
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     `endif
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     `ifdef SCG1_EN
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      lpm_rtl_support = lpm_rtl_support | 3'h4;
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     `endif
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      // Depending on RTL configuration, figure out which clocks are running with a given Low-Power-Mode
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      case(lpm_rtl_support)
434
        //                                     SMCLK     ,     DCO_CLK    ,      ACLK        
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        4'b000 :   lpm_clocks_status  = {      1'b1      ,      1'b1      ,      1'b1      };
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        4'b001 :   lpm_clocks_status  = {      1'b1      ,      1'b1      , ~lpm_config[0] };
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        4'b010 :   lpm_clocks_status  = { ~lpm_config[1] , ~lpm_config[1] ,      1'b1      };
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441
        4'b011 :   lpm_clocks_status  = { ~lpm_config[1] , ~lpm_config[1] , ~lpm_config[0] };
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443
        4'b100 :   lpm_clocks_status  = { ~lpm_config[2] ,      1'b1      ,      1'b1      };
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445
        4'b101 :   lpm_clocks_status  = { ~lpm_config[2] ,      1'b1      , ~lpm_config[0] };
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        4'b110 : begin
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                   lpm_clocks_status  = { ~lpm_config[2] , ~lpm_config[1] ,      1'b1      };
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                   lpm_clocks_status  = { ~lpm_config[1] ,      1'b1      ,      1'b1      } & lpm_clocks_status;
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                 end
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        4'b111 : begin
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                   lpm_clocks_status  = { ~lpm_config[2] , ~lpm_config[1] , ~lpm_config[0] };
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                   lpm_clocks_status  = { ~lpm_config[1] ,      1'b1      ,      1'b1      } & lpm_clocks_status;
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                 end
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      endcase
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    // If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
458
    `ifdef LFXT_DOMAIN
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    `else
460
      lpm_clocks_status[0] = lpm_clocks_status[1];
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    `endif
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463
   end
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endfunction
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