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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dma_resp.v] - Blame information for rev 202

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1 202 olivier.gi 
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                              DMA INTERFACE                                */
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/*---------------------------------------------------------------------------*/
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/* Test the DMA interface:                                                   */
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/*                        - Check transfer response.                         */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev$                                                                */
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/* $LastChangedBy$                                          */
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/* $LastChangedDate$          */
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/*===========================================================================*/
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`define VERY_LONG_TIMEOUT
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integer jj, kk;
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reg [15:0] data_val;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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`ifdef DMA_IF_EN
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      // Disable automatic DMA verification
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      #10;
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      dma_verif_on = 0;
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      repeat(30) @(posedge mclk);
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      stimulus_done = 0;
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      //-------------------------------------------------------------
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      // LOW/HIGH PRIORITY DMA
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      //-------------------------------------------------------------
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      for ( jj=0; jj<=1; jj=jj+1)
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        begin
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           if (jj==0)
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             begin
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                dma_priority=0;
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                $display("\n\n---------------------------------------");
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                $display("   LOW Priority 16B DMA transfer tests");
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                $display("---------------------------------------\n");
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             end
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           else
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             begin
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                dma_priority=1;
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                $display("\n\n---------------------------------------");
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                $display("   HIGH Priority 16B DMA transfer tests");
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                $display("---------------------------------------\n");
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             end
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           // READ ACCESS (whole 64kB address range)
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           //--------------------------------------------------------
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           $display("READ ACCESS (whole 64kB address range)");
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           for ( kk=0; kk<='hfffe; kk=kk+2)
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             begin
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                if      (kk<(`PER_SIZE+`DMEM_SIZE)) dma_read_val_16b(kk, 1'b0); // OKAY response in Peripheral and Data memory space
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                else if (kk>=('h10000-`PMEM_SIZE))  dma_read_val_16b(kk, 1'b0); // OKAY response in Program memory space
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                else                                dma_read_val_16b(kk, 1'b1); // ERROR response otherwise
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             end
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        end
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      // WRITE ACCESS (whole 64kB address range)
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      // (we just do it in high priority mode as PMEM will be overwriten anyway)
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      //-------------------------------------------------------------------------
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      $display("WRITE ACCESS (whole 64kB address range)");
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      for ( kk=0; kk<='hfffe; kk=kk+2)
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        begin
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           case(kk)
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             'h0056     : data_val  = 16'h0000; // BCSCTL1 (avoid reconfiguration of the MCLK frequency)
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             'h0058     : data_val  = 16'h0000; // BCSCTL1 (avoid reconfiguration of the MCLK frequency)
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             'h0120     : data_val  = 16'h5A80; // WDTCTL (avoid reset when writing to watchdog control register)
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             default    : data_val  =  kk;
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           endcase
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           if      (kk<(`PER_SIZE+`DMEM_SIZE)) dma_write_16b(kk, data_val, 1'b0); // OKAY response in Peripheral and Data memory space
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           else if (kk>=('h10000-`PMEM_SIZE))  dma_write_16b(kk, data_val, 1'b0); // OKAY response in Program memory space
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           else                                dma_write_16b(kk, data_val, 1'b1); // ERROR response otherwise
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        end
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      // End of test
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      //--------------------------------------------------
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      $display("\n");
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      repeat(3000) @(posedge mclk);
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      // Put small program in memory
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      dma_write_16b(16'hfff0, 16'h4303, 1'b0); // nop
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      dma_write_16b(16'hfff2, 16'h4030, 1'b0); // br #0xffff
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      dma_write_16b(16'hfff4, 16'hffff, 1'b0); //
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      dma_write_16b(16'hfffe, 16'hfff0, 1'b0); // Reset vector
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      // Apply reset and wait for end of execution
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      dma_write_16b(16'h0120, 16'h0000, 1'b0); // WDTCTL
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      stimulus_done = 1;
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`else
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       tb_skip_finish("|      (DMA interface support not included)    |");
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`endif
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   end
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