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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_irq.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DIGITAL I/O                                    */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface:                                           */
/*                                   - Interrupts.                           */
/*===========================================================================*/
 
.global main
 
.set   P1IN,  0x0020
.set   P1OUT, 0x0021
.set   P1DIR, 0x0022
.set   P1IFG, 0x0023
.set   P1IES, 0x0024
.set   P1IE,  0x0025
.set   P1SEL, 0x0026
.set   P2IN,  0x0028
.set   P2OUT, 0x0029
.set   P2DIR, 0x002A
.set   P2IFG, 0x002B
.set   P2IES, 0x002C
.set   P2IE,  0x002D
.set   P2SEL, 0x002E
 
main:
        ; Disable interrupts
        dint
        mov.b #0x00, &P1IE
        mov.b #0x00, &P2IE
 
 
        /* -------------- PORT 1: TEST INTERRUPT FLAGS  --------------- */
 
 
        mov.b   #0x00, &P1IES       ;# TEST IF RISING EDGE ENABLED
 
        mov     #0x0200, r15        ;# Make sure rising edge is detected test 1
p1ifg_re_loop1:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        mov.b   #0x00, &P1IFG
        inc      r15
        cmp     #0x0208, r15
        jne     p1ifg_re_loop1
 
        mov     #0x0210, r15        ;# Make sure falling edge is ignored
p1ifg_fe_loop1:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        mov.b   #0x00, &P1IFG
        inc      r15
        cmp     #0x0218, r15
        jne     p1ifg_fe_loop1
 
        mov     #0x0220, r15        ;# Make sure rising edge is detected test 2
p1ifg_re_loop2:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        inc      r15
        cmp     #0x0228, r15
        jne     p1ifg_re_loop2
        mov.b   #0x00, &P1IFG
 
 
 
        mov.b   #0xff, &P1IES       ;# TEST IF FALLING EDGE ENABLED
 
        mov     #0x0230, r15        ;# Make sure falling edge is detected test 1
p1ifg_fe_loop2:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        mov.b   #0x00, &P1IFG
        inc      r15
        cmp     #0x0238, r15
        jne     p1ifg_fe_loop2
 
        mov     #0x0240, r15        ;# Make sure rising edge is ignored
p1ifg_re_loop3:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        mov.b   #0x00, &P1IFG
        inc      r15
        cmp     #0x0248, r15
        jne     p1ifg_re_loop3
 
        mov     #0x0250, r15        ;# Make sure falling edge is detected test 2
p1ifg_fe_loop3:
        nop
        nop
        mov.b &P1IFG,  0(r15)
        inc      r15
        cmp     #0x0258, r15
        jne     p1ifg_fe_loop3
        mov.b   #0x00, &P1IFG
 
 
        /* -------------- PORT 2: TEST INTERRUPT FLAGS  --------------- */
 
 
        mov.b   #0x00, &P2IES       ;# TEST IF RISING EDGE ENABLED
 
        mov     #0x0200, r15        ;# Make sure rising edge is detected test 1
p2ifg_re_loop1:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        mov.b   #0x00, &P2IFG
        inc      r15
        cmp     #0x0208, r15
        jne     p2ifg_re_loop1
 
        mov     #0x0210, r15        ;# Make sure falling edge is ignored
p2ifg_fe_loop1:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        mov.b   #0x00, &P2IFG
        inc      r15
        cmp     #0x0218, r15
        jne     p2ifg_fe_loop1
 
        mov     #0x0220, r15        ;# Make sure rising edge is detected test 2
p2ifg_re_loop2:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        inc      r15
        cmp     #0x0228, r15
        jne     p2ifg_re_loop2
        mov.b   #0x00, &P2IFG
 
 
 
        mov.b   #0xff, &P2IES       ;# TEST IF FALLING EDGE ENABLED
 
        mov     #0x0230, r15        ;# Make sure falling edge is detected test 1
p2ifg_fe_loop2:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        mov.b   #0x00, &P2IFG
        inc      r15
        cmp     #0x0238, r15
        jne     p2ifg_fe_loop2
 
        mov     #0x0240, r15        ;# Make sure rising edge is ignored
p2ifg_re_loop3:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        mov.b   #0x00, &P2IFG
        inc      r15
        cmp     #0x0248, r15
        jne     p2ifg_re_loop3
 
        mov     #0x0250, r15        ;# Make sure falling edge is detected test 2
p2ifg_fe_loop3:
        nop
        nop
        mov.b &P2IFG,  0(r15)
        inc      r15
        cmp     #0x0258, r15
        jne     p2ifg_fe_loop3
        mov.b   #0x00, &P2IFG
 
 
        /* --------------            CLEAR MEMORY        --------------- */
 
        mov     #0x0200, r5
mem_clear_loop:
        mov     #0x00,  0(r5)
        incd      r5
        cmp     #0x0260, r5
        jne     mem_clear_loop
 
 
        /* -------------- PORT 1: TEST INTERRUPT VECTOR  --------------- */
 
        mov     #0x0250, r1     ; Initialize stack
        eint                    ; Enable interrupts
 
        mov.b   #0x0001, r6
        mov.b        r6, &P1IE
        mov     #0x0200, r15;
p1_irq_loop:
        mov.b        r6, &P1IFG ; Generate soft interrupt
        nop
        nop
        nop
        rla          r6
        mov.b        r6, &P1IE
        inc         r15
        cmp     #0x0208, r15
        jne     p1_irq_loop
 
 
        /* -------------- PORT 2: TEST INTERRUPT VECTOR  --------------- */
 
        mov     #0x0250, r1     ; Initialize stack
        eint                    ; Enable interrupts
 
        mov.b   #0x0001, r6
        mov.b        r6, &P2IE
        mov     #0x0210, r15;
p2_irq_loop:
        mov.b        r6, &P2IFG ; Generate soft interrupt
        nop
        nop
        nop
        rla          r6
        mov.b        r6, &P2IE
        inc         r15
        cmp     #0x0218, r15
        jne     p2_irq_loop
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
PORT1_VECTOR:
        mov.b &P1IFG,  0(r15)
        mov.b  #0x00, &P1IFG
        reti
 
PORT2_VECTOR:
        mov.b &P2IFG,  0(r15)
        mov.b  #0x00, &P2IFG
        reti
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word PORT1_VECTOR ; Interrupt  2                      
.word PORT2_VECTOR ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_irq.s43] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DIGITAL I/O */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Digital I/O interface: */`
27			`/* - Interrupts. */`
28			`/===========================================================================/`
29
30			`.global main`
31
32			`.set P1IN, 0x0020`
33			`.set P1OUT, 0x0021`
34			`.set P1DIR, 0x0022`
35			`.set P1IFG, 0x0023`
36			`.set P1IES, 0x0024`
37			`.set P1IE, 0x0025`
38			`.set P1SEL, 0x0026`
39			`.set P2IN, 0x0028`
40			`.set P2OUT, 0x0029`
41			`.set P2DIR, 0x002A`
42			`.set P2IFG, 0x002B`
43			`.set P2IES, 0x002C`
44			`.set P2IE, 0x002D`
45			`.set P2SEL, 0x002E`
46
47			`main:`
48			`; Disable interrupts`
49			`dint`
50			`mov.b #0x00, &P1IE`
51			`mov.b #0x00, &P2IE`
52
53
54			`/* -------------- PORT 1: TEST INTERRUPT FLAGS --------------- */`
55
56
57			`mov.b #0x00, &P1IES ;# TEST IF RISING EDGE ENABLED`
58
59			`mov #0x0200, r15 ;# Make sure rising edge is detected test 1`
60			`p1ifg_re_loop1:`
61			`nop`
62			`nop`
63			`mov.b &P1IFG, 0(r15)`
64			`mov.b #0x00, &P1IFG`
65			`inc r15`
66			`cmp #0x0208, r15`
67			`jne p1ifg_re_loop1`
68
69			`mov #0x0210, r15 ;# Make sure falling edge is ignored`
70			`p1ifg_fe_loop1:`
71			`nop`
72			`nop`
73			`mov.b &P1IFG, 0(r15)`
74			`mov.b #0x00, &P1IFG`
75			`inc r15`
76			`cmp #0x0218, r15`
77			`jne p1ifg_fe_loop1`
78
79			`mov #0x0220, r15 ;# Make sure rising edge is detected test 2`
80			`p1ifg_re_loop2:`
81			`nop`
82			`nop`
83			`mov.b &P1IFG, 0(r15)`
84			`inc r15`
85			`cmp #0x0228, r15`
86			`jne p1ifg_re_loop2`
87			`mov.b #0x00, &P1IFG`
88
89
90
91			`mov.b #0xff, &P1IES ;# TEST IF FALLING EDGE ENABLED`
92
93			`mov #0x0230, r15 ;# Make sure falling edge is detected test 1`
94			`p1ifg_fe_loop2:`
95			`nop`
96			`nop`
97			`mov.b &P1IFG, 0(r15)`
98			`mov.b #0x00, &P1IFG`
99			`inc r15`
100			`cmp #0x0238, r15`
101			`jne p1ifg_fe_loop2`
102
103			`mov #0x0240, r15 ;# Make sure rising edge is ignored`
104			`p1ifg_re_loop3:`
105			`nop`
106			`nop`
107			`mov.b &P1IFG, 0(r15)`
108			`mov.b #0x00, &P1IFG`
109			`inc r15`
110			`cmp #0x0248, r15`
111			`jne p1ifg_re_loop3`
112
113			`mov #0x0250, r15 ;# Make sure falling edge is detected test 2`
114			`p1ifg_fe_loop3:`
115			`nop`
116			`nop`
117			`mov.b &P1IFG, 0(r15)`
118			`inc r15`
119			`cmp #0x0258, r15`
120			`jne p1ifg_fe_loop3`
121			`mov.b #0x00, &P1IFG`
122
123
124			`/* -------------- PORT 2: TEST INTERRUPT FLAGS --------------- */`
125
126
127			`mov.b #0x00, &P2IES ;# TEST IF RISING EDGE ENABLED`
128
129			`mov #0x0200, r15 ;# Make sure rising edge is detected test 1`
130			`p2ifg_re_loop1:`
131			`nop`
132			`nop`
133			`mov.b &P2IFG, 0(r15)`
134			`mov.b #0x00, &P2IFG`
135			`inc r15`
136			`cmp #0x0208, r15`
137			`jne p2ifg_re_loop1`
138
139			`mov #0x0210, r15 ;# Make sure falling edge is ignored`
140			`p2ifg_fe_loop1:`
141			`nop`
142			`nop`
143			`mov.b &P2IFG, 0(r15)`
144			`mov.b #0x00, &P2IFG`
145			`inc r15`
146			`cmp #0x0218, r15`
147			`jne p2ifg_fe_loop1`
148
149			`mov #0x0220, r15 ;# Make sure rising edge is detected test 2`
150			`p2ifg_re_loop2:`
151			`nop`
152			`nop`
153			`mov.b &P2IFG, 0(r15)`
154			`inc r15`
155			`cmp #0x0228, r15`
156			`jne p2ifg_re_loop2`
157			`mov.b #0x00, &P2IFG`
158
159
160
161			`mov.b #0xff, &P2IES ;# TEST IF FALLING EDGE ENABLED`
162
163			`mov #0x0230, r15 ;# Make sure falling edge is detected test 1`
164			`p2ifg_fe_loop2:`
165			`nop`
166			`nop`
167			`mov.b &P2IFG, 0(r15)`
168			`mov.b #0x00, &P2IFG`
169			`inc r15`
170			`cmp #0x0238, r15`
171			`jne p2ifg_fe_loop2`
172
173			`mov #0x0240, r15 ;# Make sure rising edge is ignored`
174			`p2ifg_re_loop3:`
175			`nop`
176			`nop`
177			`mov.b &P2IFG, 0(r15)`
178			`mov.b #0x00, &P2IFG`
179			`inc r15`
180			`cmp #0x0248, r15`
181			`jne p2ifg_re_loop3`
182
183			`mov #0x0250, r15 ;# Make sure falling edge is detected test 2`
184			`p2ifg_fe_loop3:`
185			`nop`
186			`nop`
187			`mov.b &P2IFG, 0(r15)`
188			`inc r15`
189			`cmp #0x0258, r15`
190			`jne p2ifg_fe_loop3`
191			`mov.b #0x00, &P2IFG`
192
193
194			`/* -------------- CLEAR MEMORY --------------- */`
195
196			`mov #0x0200, r5`
197			`mem_clear_loop:`
198			`mov #0x00, 0(r5)`
199			`incd r5`
200			`cmp #0x0260, r5`
201			`jne mem_clear_loop`
202
203
204			`/* -------------- PORT 1: TEST INTERRUPT VECTOR --------------- */`
205
206			`mov #0x0250, r1 ; Initialize stack`
207			`eint ; Enable interrupts`
208
209			`mov.b #0x0001, r6`
210			`mov.b r6, &P1IE`
211			`mov #0x0200, r15;`
212			`p1_irq_loop:`
213			`mov.b r6, &P1IFG ; Generate soft interrupt`
214			`nop`
215			`nop`
216			`nop`
217			`rla r6`
218			`mov.b r6, &P1IE`
219			`inc r15`
220			`cmp #0x0208, r15`
221			`jne p1_irq_loop`
222
223
224			`/* -------------- PORT 2: TEST INTERRUPT VECTOR --------------- */`
225
226			`mov #0x0250, r1 ; Initialize stack`
227			`eint ; Enable interrupts`
228
229			`mov.b #0x0001, r6`
230			`mov.b r6, &P2IE`
231			`mov #0x0210, r15;`
232			`p2_irq_loop:`
233			`mov.b r6, &P2IFG ; Generate soft interrupt`
234			`nop`
235			`nop`
236			`nop`
237			`rla r6`
238			`mov.b r6, &P2IE`
239			`inc r15`
240			`cmp #0x0218, r15`
241			`jne p2_irq_loop`
242
243
244			`/* ---------------------- END OF TEST --------------- */`
245			`end_of_test:`
246			`nop`
247			`br #0xffff`
248
249
250			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
251
252			`PORT1_VECTOR:`
253			`mov.b &P1IFG, 0(r15)`
254			`mov.b #0x00, &P1IFG`
255			`reti`
256
257			`PORT2_VECTOR:`
258			`mov.b &P2IFG, 0(r15)`
259			`mov.b #0x00, &P2IFG`
260			`reti`
261
262
263
264			`/* ---------------------- INTERRUPT VECTORS --------------- */`
265
266			`.section .vectors, "a"`
267			`.word end_of_test ; Interrupt 0 (lowest priority)`
268			`.word end_of_test ; Interrupt 1`
269			`.word PORT1_VECTOR ; Interrupt 2`
270			`.word PORT2_VECTOR ; Interrupt 3`
271			`.word end_of_test ; Interrupt 4`
272			`.word end_of_test ; Interrupt 5`
273			`.word end_of_test ; Interrupt 6`
274			`.word end_of_test ; Interrupt 7`
275			`.word end_of_test ; Interrupt 8`
276			`.word end_of_test ; Interrupt 9`
277			`.word end_of_test ; Interrupt 10 Watchdog timer`
278			`.word end_of_test ; Interrupt 11`
279			`.word end_of_test ; Interrupt 12`
280			`.word end_of_test ; Interrupt 13`
281			`.word end_of_test ; Interrupt 14 NMI`
282			`.word main ; Interrupt 15 (highest priority) RESET`