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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_irq.v] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                 DIGITAL I/O                               */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the Digital I/O interface:                                           */
27 
/*                                   - Interrupts.                           */
28 
/*===========================================================================*/
29 
 
30 
initial
31 
   begin
32 
      $display(" ===============================================");
33 
      $display("|                 START SIMULATION              |");
34 
      $display(" ===============================================");
35 
      repeat(5) @(posedge mclk);
36 
      stimulus_done = 0;
37 
 
38 
 
39 
      // PORT 1: TEST INTERRUPT FLAGS
40 
      //--------------------------------------------------------
41 
 
42 
      @(r15==16'h0200) p1_din = 8'h01;
43 
      @(r15==16'h0201) p1_din = 8'h03;
44 
      @(r15==16'h0202) p1_din = 8'h07;
45 
      @(r15==16'h0203) p1_din = 8'h0f;
46 
      @(r15==16'h0204) p1_din = 8'h1f;
47 
      @(r15==16'h0205) p1_din = 8'h3f;
48 
      @(r15==16'h0206) p1_din = 8'h7f;
49 
      @(r15==16'h0207) p1_din = 8'hff;
50 
      @(r15==16'h0208);
51 
      if (mem200 !== 16'h0201) tb_error("====== RISING EDGE TEST: P1IFG != 0x0201 =====");
52 
      if (mem202 !== 16'h0804) tb_error("====== RISING EDGE TEST: P1IFG != 0x0804 =====");
53 
      if (mem204 !== 16'h2010) tb_error("====== RISING EDGE TEST: P1IFG != 0x2010 =====");
54 
      if (mem206 !== 16'h8040) tb_error("====== RISING EDGE TEST: P1IFG != 0x8040 =====");
55 
 
56 
 
57 
      @(r15==16'h0210) p1_din = 8'h7f;
58 
      @(r15==16'h0211) p1_din = 8'h3f;
59 
      @(r15==16'h0212) p1_din = 8'h1f;
60 
      @(r15==16'h0213) p1_din = 8'h0f;
61 
      @(r15==16'h0214) p1_din = 8'h07;
62 
      @(r15==16'h0215) p1_din = 8'h03;
63 
      @(r15==16'h0216) p1_din = 8'h01;
64 
      @(r15==16'h0217) p1_din = 8'h00;
65 
      @(r15==16'h0218);
66 
      if (mem210 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
67 
      if (mem212 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
68 
      if (mem214 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
69 
      if (mem216 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
70 
 
71 
 
72 
      @(r15==16'h0220) p1_din = 8'h01;
73 
      @(r15==16'h0221) p1_din = 8'h03;
74 
      @(r15==16'h0222) p1_din = 8'h07;
75 
      @(r15==16'h0223) p1_din = 8'h0f;
76 
      @(r15==16'h0224) p1_din = 8'h1f;
77 
      @(r15==16'h0225) p1_din = 8'h3f;
78 
      @(r15==16'h0226) p1_din = 8'h7f;
79 
      @(r15==16'h0227) p1_din = 8'hff;
80 
      @(r15==16'h0228);
81 
      if (mem220 !== 16'h0301) tb_error("====== RISING EDGE TEST: P1IFG != 0x0301 =====");
82 
      if (mem222 !== 16'h0f07) tb_error("====== RISING EDGE TEST: P1IFG != 0x0f07 =====");
83 
      if (mem224 !== 16'h3f1f) tb_error("====== RISING EDGE TEST: P1IFG != 0x3f1f =====");
84 
      if (mem226 !== 16'hff7f) tb_error("====== RISING EDGE TEST: P1IFG != 0xff7f =====");
85 
 
86 
 
87 
      @(r15==16'h0230) p1_din = 8'h7f;
88 
      @(r15==16'h0231) p1_din = 8'h3f;
89 
      @(r15==16'h0232) p1_din = 8'h1f;
90 
      @(r15==16'h0233) p1_din = 8'h0f;
91 
      @(r15==16'h0234) p1_din = 8'h07;
92 
      @(r15==16'h0235) p1_din = 8'h03;
93 
      @(r15==16'h0236) p1_din = 8'h01;
94 
      @(r15==16'h0237) p1_din = 8'h00;
95 
      @(r15==16'h0238);
96 
      if (mem230 !== 16'h4080) tb_error("====== FALLING EDGE TEST: P1IFG != 0x4080 =====");
97 
      if (mem232 !== 16'h1020) tb_error("====== FALLING EDGE TEST: P1IFG != 0x1020 =====");
98 
      if (mem234 !== 16'h0408) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0408 =====");
99 
      if (mem236 !== 16'h0102) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0102 =====");
100 
 
101 
      @(r15==16'h0240) p1_din = 8'h01;
102 
      @(r15==16'h0241) p1_din = 8'h03;
103 
      @(r15==16'h0242) p1_din = 8'h07;
104 
      @(r15==16'h0243) p1_din = 8'h0f;
105 
      @(r15==16'h0244) p1_din = 8'h1f;
106 
      @(r15==16'h0245) p1_din = 8'h3f;
107 
      @(r15==16'h0246) p1_din = 8'h7f;
108 
      @(r15==16'h0247) p1_din = 8'hff;
109 
      @(r15==16'h0248);
110 
      if (mem240 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
111 
      if (mem242 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
112 
      if (mem244 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
113 
      if (mem246 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
114 
 
115 
      @(r15==16'h0250) p1_din = 8'h7f;
116 
      @(r15==16'h0251) p1_din = 8'h3f;
117 
      @(r15==16'h0252) p1_din = 8'h1f;
118 
      @(r15==16'h0253) p1_din = 8'h0f;
119 
      @(r15==16'h0254) p1_din = 8'h07;
120 
      @(r15==16'h0255) p1_din = 8'h03;
121 
      @(r15==16'h0256) p1_din = 8'h01;
122 
      @(r15==16'h0257) p1_din = 8'h00;
123 
      @(r15==16'h0258);
124 
      if (mem250 !== 16'hc080) tb_error("====== FALLING EDGE TEST: P1IFG != 0xc080 =====");
125 
      if (mem252 !== 16'hf0e0) tb_error("====== FALLING EDGE TEST: P1IFG != 0xf0e0 =====");
126 
      if (mem254 !== 16'hfcf8) tb_error("====== FALLING EDGE TEST: P1IFG != 0xfcf8 =====");
127 
      if (mem256 !== 16'hfffe) tb_error("====== FALLING EDGE TEST: P1IFG != 0xfffe =====");
128 
 
129 
 
130 
      // PORT 2: TEST INTERRUPT FLAGS
131 
      //--------------------------------------------------------
132 
 
133 
      @(r15==16'h0200) p2_din = 8'h01;
134 
      @(r15==16'h0201) p2_din = 8'h03;
135 
      @(r15==16'h0202) p2_din = 8'h07;
136 
      @(r15==16'h0203) p2_din = 8'h0f;
137 
      @(r15==16'h0204) p2_din = 8'h1f;
138 
      @(r15==16'h0205) p2_din = 8'h3f;
139 
      @(r15==16'h0206) p2_din = 8'h7f;
140 
      @(r15==16'h0207) p2_din = 8'hff;
141 
      @(r15==16'h0208);
142 
      if (mem200 !== 16'h0201) tb_error("====== RISING EDGE TEST: P2IFG != 0x0201 =====");
143 
      if (mem202 !== 16'h0804) tb_error("====== RISING EDGE TEST: P2IFG != 0x0804 =====");
144 
      if (mem204 !== 16'h2010) tb_error("====== RISING EDGE TEST: P2IFG != 0x2010 =====");
145 
      if (mem206 !== 16'h8040) tb_error("====== RISING EDGE TEST: P2IFG != 0x8040 =====");
146 
 
147 
 
148 
      @(r15==16'h0210) p2_din = 8'h7f;
149 
      @(r15==16'h0211) p2_din = 8'h3f;
150 
      @(r15==16'h0212) p2_din = 8'h1f;
151 
      @(r15==16'h0213) p2_din = 8'h0f;
152 
      @(r15==16'h0214) p2_din = 8'h07;
153 
      @(r15==16'h0215) p2_din = 8'h03;
154 
      @(r15==16'h0216) p2_din = 8'h01;
155 
      @(r15==16'h0217) p2_din = 8'h00;
156 
      @(r15==16'h0218);
157 
      if (mem210 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
158 
      if (mem212 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
159 
      if (mem214 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
160 
      if (mem216 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
161 
 
162 
 
163 
      @(r15==16'h0220) p2_din = 8'h01;
164 
      @(r15==16'h0221) p2_din = 8'h03;
165 
      @(r15==16'h0222) p2_din = 8'h07;
166 
      @(r15==16'h0223) p2_din = 8'h0f;
167 
      @(r15==16'h0224) p2_din = 8'h1f;
168 
      @(r15==16'h0225) p2_din = 8'h3f;
169 
      @(r15==16'h0226) p2_din = 8'h7f;
170 
      @(r15==16'h0227) p2_din = 8'hff;
171 
      @(r15==16'h0228);
172 
      if (mem220 !== 16'h0301) tb_error("====== RISING EDGE TEST: P2IFG != 0x0301 =====");
173 
      if (mem222 !== 16'h0f07) tb_error("====== RISING EDGE TEST: P2IFG != 0x0f07 =====");
174 
      if (mem224 !== 16'h3f1f) tb_error("====== RISING EDGE TEST: P2IFG != 0x3f1f =====");
175 
      if (mem226 !== 16'hff7f) tb_error("====== RISING EDGE TEST: P2IFG != 0xff7f =====");
176 
 
177 
 
178 
      @(r15==16'h0230) p2_din = 8'h7f;
179 
      @(r15==16'h0231) p2_din = 8'h3f;
180 
      @(r15==16'h0232) p2_din = 8'h1f;
181 
      @(r15==16'h0233) p2_din = 8'h0f;
182 
      @(r15==16'h0234) p2_din = 8'h07;
183 
      @(r15==16'h0235) p2_din = 8'h03;
184 
      @(r15==16'h0236) p2_din = 8'h01;
185 
      @(r15==16'h0237) p2_din = 8'h00;
186 
      @(r15==16'h0238);
187 
      if (mem230 !== 16'h4080) tb_error("====== FALLING EDGE TEST: P2IFG != 0x4080 =====");
188 
      if (mem232 !== 16'h1020) tb_error("====== FALLING EDGE TEST: P2IFG != 0x1020 =====");
189 
      if (mem234 !== 16'h0408) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0408 =====");
190 
      if (mem236 !== 16'h0102) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0102 =====");
191 
 
192 
      @(r15==16'h0240) p2_din = 8'h01;
193 
      @(r15==16'h0241) p2_din = 8'h03;
194 
      @(r15==16'h0242) p2_din = 8'h07;
195 
      @(r15==16'h0243) p2_din = 8'h0f;
196 
      @(r15==16'h0244) p2_din = 8'h1f;
197 
      @(r15==16'h0245) p2_din = 8'h3f;
198 
      @(r15==16'h0246) p2_din = 8'h7f;
199 
      @(r15==16'h0247) p2_din = 8'hff;
200 
      @(r15==16'h0248);
201 
      if (mem240 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
202 
      if (mem242 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
203 
      if (mem244 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
204 
      if (mem246 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
205 
 
206 
      @(r15==16'h0250) p2_din = 8'h7f;
207 
      @(r15==16'h0251) p2_din = 8'h3f;
208 
      @(r15==16'h0252) p2_din = 8'h1f;
209 
      @(r15==16'h0253) p2_din = 8'h0f;
210 
      @(r15==16'h0254) p2_din = 8'h07;
211 
      @(r15==16'h0255) p2_din = 8'h03;
212 
      @(r15==16'h0256) p2_din = 8'h01;
213 
      @(r15==16'h0257) p2_din = 8'h00;
214 
      @(r15==16'h0258);
215 
      if (mem250 !== 16'hc080) tb_error("====== FALLING EDGE TEST: P2IFG != 0xc080 =====");
216 
      if (mem252 !== 16'hf0e0) tb_error("====== FALLING EDGE TEST: P2IFG != 0xf0e0 =====");
217 
      if (mem254 !== 16'hfcf8) tb_error("====== FALLING EDGE TEST: P2IFG != 0xfcf8 =====");
218 
      if (mem256 !== 16'hfffe) tb_error("====== FALLING EDGE TEST: P2IFG != 0xfffe =====");
219 
 
220 
 
221 
      // PORT 1: TEST INTERRUPT VECTOR
222 
      //--------------------------------------------------------
223 
 
224 
      @(r15==16'h0208);
225 
      if (mem200 !== 16'h0201) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0201 =====");
226 
      if (mem202 !== 16'h0804) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0804 =====");
227 
      if (mem204 !== 16'h2010) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x2010 =====");
228 
      if (mem206 !== 16'h8040) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x8040 =====");
229 
 
230 
 
231 
      // PORT 2: TEST INTERRUPT VECTOR
232 
      //--------------------------------------------------------
233 
 
234 
      @(r15==16'h0218);
235 
      if (mem210 !== 16'h0201) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0201 =====");
236 
      if (mem212 !== 16'h0804) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0804 =====");
237 
      if (mem214 !== 16'h2010) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x2010 =====");
238 
      if (mem216 !== 16'h8040) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x8040 =====");
239 
 
240 
 
241 
      stimulus_done = 1;
242 
   end
243 
 

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