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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Blame information for rev 2

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DIGITAL I/O                                    */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface:                                           */
/*                                   - Read/Write register access.           */
/*                                   - I/O Functionality.                    */
/*===========================================================================*/
 
.global main
 
.set   P1IN,  0x0020
.set   P1OUT, 0x0021
.set   P1DIR, 0x0022
.set   P1IFG, 0x0023
.set   P1IES, 0x0024
.set   P1IE,  0x0025
.set   P1SEL, 0x0026
.set   P2IN,  0x0028
.set   P2OUT, 0x0029
.set   P2DIR, 0x002A
.set   P2IFG, 0x002B
.set   P2IES, 0x002C
.set   P2IE,  0x002D
.set   P2SEL, 0x002E
.set   P3IN,  0x0018
.set   P3OUT, 0x0019
.set   P3DIR, 0x001A
.set   P3SEL, 0x001B
.set   P4IN,  0x001C
.set   P4OUT, 0x001D
.set   P4DIR, 0x001E
.set   P4SEL, 0x001F
.set   P5IN,  0x0030
.set   P5OUT, 0x0031
.set   P5DIR, 0x0032
.set   P5SEL, 0x0033
.set   P6IN,  0x0034
.set   P6OUT, 0x0035
.set   P6DIR, 0x0036
.set   P6SEL, 0x0037
 
main:
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P1IN          ; P1IN
        mov.b &P1IN,  &0x0200
        mov.b #0x55,  &P1IN
        mov.b &P1IN,  &0x0201
 
        mov.b #0xaa,  &P1OUT         ; P1OUT
        mov.b &P1OUT, &0x0202
        mov.b #0x55,  &P1OUT
        mov.b &P1OUT, &0x0203
 
        mov.b #0x5a,  &P1DIR         ; P1DIR
        mov.b &P1DIR, &0x0204
        mov.b #0xa5,  &P1DIR
        mov.b &P1DIR, &0x0205
 
        mov.b #0x55,  &P1IFG         ; P1IFG
        mov.b &P1IFG, &0x0206
        mov.b #0xaa,  &P1IFG
        mov.b &P1IFG, &0x0207
 
        mov.b #0xa5,  &P1IES         ; P1IES
        mov.b &P1IES, &0x0208
        mov.b #0x5a,  &P1IES
        mov.b &P1IES, &0x0209
 
        mov.b #0xaa,  &P1IE          ; P1IE
        mov.b &P1IE,  &0x020A
        mov.b #0x55,  &P1IE
        mov.b &P1IE,  &0x020B
 
        mov.b #0xcd,  &P1SEL         ; P1SEL
        mov.b &P1SEL, &0x020C
        mov.b #0x32,  &P1SEL
        mov.b &P1SEL, &0x020D
 
 
        mov.b #0x00,  &P1IN          ; Re-Initialize
        mov.b #0x00,  &P1OUT
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1IFG
        mov.b #0x00,  &P1IES
        mov.b #0x00,  &P1IE
        mov.b #0x00,  &P1SEL
 
        mov   #0x0001, r15
 
 
        /* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P2IN          ; P2IN
        mov.b &P2IN,  &0x0210
        mov.b #0x55,  &P2IN
        mov.b &P2IN,  &0x0211
 
        mov.b #0xaa,  &P2OUT         ; P2OUT
        mov.b &P2OUT, &0x0212
        mov.b #0x55,  &P2OUT
        mov.b &P2OUT, &0x0213
 
        mov.b #0x5a,  &P2DIR         ; P2DIR
        mov.b &P2DIR, &0x0214
        mov.b #0xa5,  &P2DIR
        mov.b &P2DIR, &0x0215
 
        mov.b #0x55,  &P2IFG         ; P2IFG
        mov.b &P2IFG, &0x0216
        mov.b #0xaa,  &P2IFG
        mov.b &P2IFG, &0x0217
 
        mov.b #0xa5,  &P2IES         ; P2IES
        mov.b &P2IES, &0x0218
        mov.b #0x5a,  &P2IES
        mov.b &P2IES, &0x0219
 
        mov.b #0xaa,  &P2IE          ; P2IE
        mov.b &P2IE,  &0x021A
        mov.b #0x55,  &P2IE
        mov.b &P2IE,  &0x021B
 
        mov.b #0xcd,  &P2SEL         ; P2SEL
        mov.b &P2SEL, &0x021C
        mov.b #0x32,  &P2SEL
        mov.b &P2SEL, &0x021D
 
        mov.b #0x00,  &P2IN          ; Re-Initialize
        mov.b #0x00,  &P2OUT
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2IFG
        mov.b #0x00,  &P2IES
        mov.b #0x00,  &P2IE
        mov.b #0x00,  &P2SEL
 
        mov   #0x0002, r15
 
 
        /* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P3IN          ; P3IN
        mov.b &P3IN,  &0x0220
        mov.b #0x55,  &P3IN
        mov.b &P3IN,  &0x0221
 
        mov.b #0xaa,  &P3OUT         ; P3OUT
        mov.b &P3OUT, &0x0222
        mov.b #0x55,  &P3OUT
        mov.b &P3OUT, &0x0223
 
        mov.b #0x5a,  &P3DIR         ; P3DIR
        mov.b &P3DIR, &0x0224
        mov.b #0xa5,  &P3DIR
        mov.b &P3DIR, &0x0225
 
        mov.b #0xcd,  &P3SEL         ; P3SEL
        mov.b &P3SEL, &0x0226
        mov.b #0x32,  &P3SEL
        mov.b &P3SEL, &0x0227
 
        mov.b #0x00,  &P3IN          ; Re-Initialize
        mov.b #0x00,  &P3OUT
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL
 
        mov   #0x0003, r15
 
 
        /* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P4IN          ; P4IN
        mov.b &P4IN,  &0x0230
        mov.b #0x55,  &P4IN
        mov.b &P4IN,  &0x0231
 
        mov.b #0xaa,  &P4OUT         ; P4OUT
        mov.b &P4OUT, &0x0232
        mov.b #0x55,  &P4OUT
        mov.b &P4OUT, &0x0233
 
        mov.b #0x5a,  &P4DIR         ; P4DIR
        mov.b &P4DIR, &0x0234
        mov.b #0xa5,  &P4DIR
        mov.b &P4DIR, &0x0235
 
        mov.b #0xcd,  &P4SEL         ; P4SEL
        mov.b &P4SEL, &0x0236
        mov.b #0x32,  &P4SEL
        mov.b &P4SEL, &0x0237
 
        mov.b #0x00,  &P4IN          ; Re-Initialize
        mov.b #0x00,  &P4OUT
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL
 
        mov   #0x0004, r15
 
 
        /* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P5IN          ; P5IN
        mov.b &P5IN,  &0x0240
        mov.b #0x55,  &P5IN
        mov.b &P5IN,  &0x0241
 
        mov.b #0xaa,  &P5OUT         ; P5OUT
        mov.b &P5OUT, &0x0242
        mov.b #0x55,  &P5OUT
        mov.b &P5OUT, &0x0243
 
        mov.b #0x5a,  &P5DIR         ; P5DIR
        mov.b &P5DIR, &0x0244
        mov.b #0xa5,  &P5DIR
        mov.b &P5DIR, &0x0245
 
        mov.b #0xcd,  &P5SEL         ; P5SEL
        mov.b &P5SEL, &0x0246
        mov.b #0x32,  &P5SEL
        mov.b &P5SEL, &0x0247
 
        mov.b #0x00,  &P5IN          ; Re-Initialize
        mov.b #0x00,  &P5OUT
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL
 
        mov   #0x0005, r15
 
 
        /* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P6IN          ; P6IN
        mov.b &P6IN,  &0x0250
        mov.b #0x55,  &P6IN
        mov.b &P6IN,  &0x0251
 
        mov.b #0xaa,  &P6OUT         ; P6OUT
        mov.b &P6OUT, &0x0252
        mov.b #0x55,  &P6OUT
        mov.b &P6OUT, &0x0253
 
        mov.b #0x5a,  &P6DIR         ; P6DIR
        mov.b &P6DIR, &0x0254
        mov.b #0xa5,  &P6DIR
        mov.b &P6DIR, &0x0255
 
        mov.b #0xcd,  &P6SEL         ; P6SEL
        mov.b &P6SEL, &0x0256
        mov.b #0x32,  &P6SEL
        mov.b &P6SEL, &0x0257
 
        mov.b #0x00,  &P6IN          ; Re-Initialize
        mov.b #0x00,  &P6OUT
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL
 
        mov   #0x0006, r15
 
 
        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0200, r15        ;# Test Input path
p1_din_loop:
        mov.b &P1IN,  0(r15)
        inc      r15
        cmp     #0x0208, r15
        jne     p1_din_loop
 
 
        mov.b #0x01,   &P1OUT       ; Test Output path
        mov   #0x1100, r15
p1_dout_loop:
        rla.b &P1OUT
        inc      r15
        cmp     #0x1107, r15
        jne     p1_dout_loop
 
 
        mov.b #0x01,   &P1DIR       ; Test Direction register
        mov   #0x1200, r15
p1_dir_loop:
        rla.b &P1DIR
        inc      r15
        cmp     #0x1207, r15
        jne     p1_dir_loop
 
 
        mov.b #0x01,   &P1SEL       ; Test Function Select register
        mov   #0x1300, r15
p1_sel_loop:
        rla.b &P1SEL
        inc      r15
        cmp     #0x1307, r15
        jne     p1_sel_loop
 
 
        mov.b #0x00,  &P1OUT        ; Re-Initialize
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1SEL
 
 
        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0210, r15        ;# Test Input path
p2_din_loop:
        mov.b &P2IN,  0(r15)
        inc      r15
        cmp     #0x0218, r15
        jne     p2_din_loop
 
 
        mov.b #0x01,   &P2OUT       ; Test Output path
        mov   #0x2100, r15
p2_dout_loop:
        rla.b &P2OUT
        inc      r15
        cmp     #0x2107, r15
        jne     p2_dout_loop
 
 
        mov.b #0x01,   &P2DIR       ; Test Direction register
        mov   #0x2200, r15
p2_dir_loop:
        rla.b &P2DIR
        inc      r15
        cmp     #0x2207, r15
        jne     p2_dir_loop
 
 
        mov.b #0x01,   &P2SEL       ; Test Function Select register
        mov   #0x2300, r15
p2_sel_loop:
        rla.b &P2SEL
        inc      r15
        cmp     #0x2307, r15
        jne     p2_sel_loop
 
 
        mov.b #0x00,  &P2OUT        ; Re-Initialize
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2SEL
 
 
        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0220, r15        ;# Test Input path
p3_din_loop:
        mov.b &P3IN,  0(r15)
        inc      r15
        cmp     #0x0228, r15
        jne     p3_din_loop
 
 
        mov.b #0x01,   &P3OUT       ; Test Output path
        mov   #0x3100, r15
p3_dout_loop:
        rla.b &P3OUT
        inc      r15
        cmp     #0x3107, r15
        jne     p3_dout_loop
 
 
        mov.b #0x01,   &P3DIR       ; Test Direction register
        mov   #0x3200, r15
p3_dir_loop:
        rla.b &P3DIR
        inc      r15
        cmp     #0x3207, r15
        jne     p3_dir_loop
 
 
        mov.b #0x01,   &P3SEL       ; Test Function Select register
        mov   #0x3300, r15
p3_sel_loop:
        rla.b &P3SEL
        inc      r15
        cmp     #0x3307, r15
        jne     p3_sel_loop
 
 
        mov.b #0x00,  &P3OUT        ; Re-Initialize
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL
 
 
        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0230, r15        ;# Test Input path
p4_din_loop:
        mov.b &P4IN,  0(r15)
        inc      r15
        cmp     #0x0238, r15
        jne     p4_din_loop
 
 
        mov.b #0x01,   &P4OUT       ; Test Output path
        mov   #0x4100, r15
p4_dout_loop:
        rla.b &P4OUT
        inc      r15
        cmp     #0x4107, r15
        jne     p4_dout_loop
 
 
        mov.b #0x01,   &P4DIR       ; Test Direction register
        mov   #0x4200, r15
p4_dir_loop:
        rla.b &P4DIR
        inc      r15
        cmp     #0x4207, r15
        jne     p4_dir_loop
 
 
        mov.b #0x01,   &P4SEL       ; Test Function Select register
        mov   #0x4300, r15
p4_sel_loop:
        rla.b &P4SEL
        inc      r15
        cmp     #0x4307, r15
        jne     p4_sel_loop
 
 
        mov.b #0x00,  &P4OUT        ; Re-Initialize
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL
 
 
        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0240, r15        ;# Test Input path
p5_din_loop:
        mov.b &P5IN,  0(r15)
        inc      r15
        cmp     #0x0248, r15
        jne     p5_din_loop
 
 
        mov.b #0x01,   &P5OUT       ; Test Output path
        mov   #0x5100, r15
p5_dout_loop:
        rla.b &P5OUT
        inc      r15
        cmp     #0x5107, r15
        jne     p5_dout_loop
 
 
        mov.b #0x01,   &P5DIR       ; Test Direction register
        mov   #0x5200, r15
p5_dir_loop:
        rla.b &P5DIR
        inc      r15
        cmp     #0x5207, r15
        jne     p5_dir_loop
 
 
        mov.b #0x01,   &P5SEL       ; Test Function Select register
        mov   #0x5300, r15
p5_sel_loop:
        rla.b &P5SEL
        inc      r15
        cmp     #0x5307, r15
        jne     p5_sel_loop
 
 
        mov.b #0x00,  &P5OUT        ; Re-Initialize
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL
 
 
        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0250, r15        ;# Test Input path
p6_din_loop:
        mov.b &P6IN,  0(r15)
        inc      r15
        cmp     #0x0258, r15
        jne     p6_din_loop
 
 
        mov.b #0x01,   &P6OUT       ; Test Output path
        mov   #0x6100, r15
p6_dout_loop:
        rla.b &P6OUT
        inc      r15
        cmp     #0x6107, r15
        jne     p6_dout_loop
 
 
        mov.b #0x01,   &P6DIR       ; Test Direction register
        mov   #0x6200, r15
p6_dir_loop:
        rla.b &P6DIR
        inc      r15
        cmp     #0x6207, r15
        jne     p6_dir_loop
 
 
        mov.b #0x01,   &P6SEL       ; Test Function Select register
        mov   #0x6300, r15
p6_sel_loop:
        rla.b &P6SEL
        inc      r15
        cmp     #0x6307, r15
        jne     p6_sel_loop
 
 
        mov.b #0x00,  &P6OUT        ; Re-Initialize
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DIGITAL I/O */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Digital I/O interface: */`
27			`/* - Read/Write register access. */`
28			`/* - I/O Functionality. */`
29			`/===========================================================================/`
30
31			`.global main`
32
33			`.set P1IN, 0x0020`
34			`.set P1OUT, 0x0021`
35			`.set P1DIR, 0x0022`
36			`.set P1IFG, 0x0023`
37			`.set P1IES, 0x0024`
38			`.set P1IE, 0x0025`
39			`.set P1SEL, 0x0026`
40			`.set P2IN, 0x0028`
41			`.set P2OUT, 0x0029`
42			`.set P2DIR, 0x002A`
43			`.set P2IFG, 0x002B`
44			`.set P2IES, 0x002C`
45			`.set P2IE, 0x002D`
46			`.set P2SEL, 0x002E`
47			`.set P3IN, 0x0018`
48			`.set P3OUT, 0x0019`
49			`.set P3DIR, 0x001A`
50			`.set P3SEL, 0x001B`
51			`.set P4IN, 0x001C`
52			`.set P4OUT, 0x001D`
53			`.set P4DIR, 0x001E`
54			`.set P4SEL, 0x001F`
55			`.set P5IN, 0x0030`
56			`.set P5OUT, 0x0031`
57			`.set P5DIR, 0x0032`
58			`.set P5SEL, 0x0033`
59			`.set P6IN, 0x0034`
60			`.set P6OUT, 0x0035`
61			`.set P6DIR, 0x0036`
62			`.set P6SEL, 0x0037`
63
64			`main:`
65			`/* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */`
66
67			`mov.b #0xaa, &P1IN ; P1IN`
68			`mov.b &P1IN, &0x0200`
69			`mov.b #0x55, &P1IN`
70			`mov.b &P1IN, &0x0201`
71
72			`mov.b #0xaa, &P1OUT ; P1OUT`
73			`mov.b &P1OUT, &0x0202`
74			`mov.b #0x55, &P1OUT`
75			`mov.b &P1OUT, &0x0203`
76
77			`mov.b #0x5a, &P1DIR ; P1DIR`
78			`mov.b &P1DIR, &0x0204`
79			`mov.b #0xa5, &P1DIR`
80			`mov.b &P1DIR, &0x0205`
81
82			`mov.b #0x55, &P1IFG ; P1IFG`
83			`mov.b &P1IFG, &0x0206`
84			`mov.b #0xaa, &P1IFG`
85			`mov.b &P1IFG, &0x0207`
86
87			`mov.b #0xa5, &P1IES ; P1IES`
88			`mov.b &P1IES, &0x0208`
89			`mov.b #0x5a, &P1IES`
90			`mov.b &P1IES, &0x0209`
91
92			`mov.b #0xaa, &P1IE ; P1IE`
93			`mov.b &P1IE, &0x020A`
94			`mov.b #0x55, &P1IE`
95			`mov.b &P1IE, &0x020B`
96
97			`mov.b #0xcd, &P1SEL ; P1SEL`
98			`mov.b &P1SEL, &0x020C`
99			`mov.b #0x32, &P1SEL`
100			`mov.b &P1SEL, &0x020D`
101
102
103			`mov.b #0x00, &P1IN ; Re-Initialize`
104			`mov.b #0x00, &P1OUT`
105			`mov.b #0x00, &P1DIR`
106			`mov.b #0x00, &P1IFG`
107			`mov.b #0x00, &P1IES`
108			`mov.b #0x00, &P1IE`
109			`mov.b #0x00, &P1SEL`
110
111			`mov #0x0001, r15`
112
113
114			`/* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */`
115
116			`mov.b #0xaa, &P2IN ; P2IN`
117			`mov.b &P2IN, &0x0210`
118			`mov.b #0x55, &P2IN`
119			`mov.b &P2IN, &0x0211`
120
121			`mov.b #0xaa, &P2OUT ; P2OUT`
122			`mov.b &P2OUT, &0x0212`
123			`mov.b #0x55, &P2OUT`
124			`mov.b &P2OUT, &0x0213`
125
126			`mov.b #0x5a, &P2DIR ; P2DIR`
127			`mov.b &P2DIR, &0x0214`
128			`mov.b #0xa5, &P2DIR`
129			`mov.b &P2DIR, &0x0215`
130
131			`mov.b #0x55, &P2IFG ; P2IFG`
132			`mov.b &P2IFG, &0x0216`
133			`mov.b #0xaa, &P2IFG`
134			`mov.b &P2IFG, &0x0217`
135
136			`mov.b #0xa5, &P2IES ; P2IES`
137			`mov.b &P2IES, &0x0218`
138			`mov.b #0x5a, &P2IES`
139			`mov.b &P2IES, &0x0219`
140
141			`mov.b #0xaa, &P2IE ; P2IE`
142			`mov.b &P2IE, &0x021A`
143			`mov.b #0x55, &P2IE`
144			`mov.b &P2IE, &0x021B`
145
146			`mov.b #0xcd, &P2SEL ; P2SEL`
147			`mov.b &P2SEL, &0x021C`
148			`mov.b #0x32, &P2SEL`
149			`mov.b &P2SEL, &0x021D`
150
151			`mov.b #0x00, &P2IN ; Re-Initialize`
152			`mov.b #0x00, &P2OUT`
153			`mov.b #0x00, &P2DIR`
154			`mov.b #0x00, &P2IFG`
155			`mov.b #0x00, &P2IES`
156			`mov.b #0x00, &P2IE`
157			`mov.b #0x00, &P2SEL`
158
159			`mov #0x0002, r15`
160
161
162			`/* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */`
163
164			`mov.b #0xaa, &P3IN ; P3IN`
165			`mov.b &P3IN, &0x0220`
166			`mov.b #0x55, &P3IN`
167			`mov.b &P3IN, &0x0221`
168
169			`mov.b #0xaa, &P3OUT ; P3OUT`
170			`mov.b &P3OUT, &0x0222`
171			`mov.b #0x55, &P3OUT`
172			`mov.b &P3OUT, &0x0223`
173
174			`mov.b #0x5a, &P3DIR ; P3DIR`
175			`mov.b &P3DIR, &0x0224`
176			`mov.b #0xa5, &P3DIR`
177			`mov.b &P3DIR, &0x0225`
178
179			`mov.b #0xcd, &P3SEL ; P3SEL`
180			`mov.b &P3SEL, &0x0226`
181			`mov.b #0x32, &P3SEL`
182			`mov.b &P3SEL, &0x0227`
183
184			`mov.b #0x00, &P3IN ; Re-Initialize`
185			`mov.b #0x00, &P3OUT`
186			`mov.b #0x00, &P3DIR`
187			`mov.b #0x00, &P3SEL`
188
189			`mov #0x0003, r15`
190
191
192			`/* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */`
193
194			`mov.b #0xaa, &P4IN ; P4IN`
195			`mov.b &P4IN, &0x0230`
196			`mov.b #0x55, &P4IN`
197			`mov.b &P4IN, &0x0231`
198
199			`mov.b #0xaa, &P4OUT ; P4OUT`
200			`mov.b &P4OUT, &0x0232`
201			`mov.b #0x55, &P4OUT`
202			`mov.b &P4OUT, &0x0233`
203
204			`mov.b #0x5a, &P4DIR ; P4DIR`
205			`mov.b &P4DIR, &0x0234`
206			`mov.b #0xa5, &P4DIR`
207			`mov.b &P4DIR, &0x0235`
208
209			`mov.b #0xcd, &P4SEL ; P4SEL`
210			`mov.b &P4SEL, &0x0236`
211			`mov.b #0x32, &P4SEL`
212			`mov.b &P4SEL, &0x0237`
213
214			`mov.b #0x00, &P4IN ; Re-Initialize`
215			`mov.b #0x00, &P4OUT`
216			`mov.b #0x00, &P4DIR`
217			`mov.b #0x00, &P4SEL`
218
219			`mov #0x0004, r15`
220
221
222			`/* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */`
223
224			`mov.b #0xaa, &P5IN ; P5IN`
225			`mov.b &P5IN, &0x0240`
226			`mov.b #0x55, &P5IN`
227			`mov.b &P5IN, &0x0241`
228
229			`mov.b #0xaa, &P5OUT ; P5OUT`
230			`mov.b &P5OUT, &0x0242`
231			`mov.b #0x55, &P5OUT`
232			`mov.b &P5OUT, &0x0243`
233
234			`mov.b #0x5a, &P5DIR ; P5DIR`
235			`mov.b &P5DIR, &0x0244`
236			`mov.b #0xa5, &P5DIR`
237			`mov.b &P5DIR, &0x0245`
238
239			`mov.b #0xcd, &P5SEL ; P5SEL`
240			`mov.b &P5SEL, &0x0246`
241			`mov.b #0x32, &P5SEL`
242			`mov.b &P5SEL, &0x0247`
243
244			`mov.b #0x00, &P5IN ; Re-Initialize`
245			`mov.b #0x00, &P5OUT`
246			`mov.b #0x00, &P5DIR`
247			`mov.b #0x00, &P5SEL`
248
249			`mov #0x0005, r15`
250
251
252			`/* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */`
253
254			`mov.b #0xaa, &P6IN ; P6IN`
255			`mov.b &P6IN, &0x0250`
256			`mov.b #0x55, &P6IN`
257			`mov.b &P6IN, &0x0251`
258
259			`mov.b #0xaa, &P6OUT ; P6OUT`
260			`mov.b &P6OUT, &0x0252`
261			`mov.b #0x55, &P6OUT`
262			`mov.b &P6OUT, &0x0253`
263
264			`mov.b #0x5a, &P6DIR ; P6DIR`
265			`mov.b &P6DIR, &0x0254`
266			`mov.b #0xa5, &P6DIR`
267			`mov.b &P6DIR, &0x0255`
268
269			`mov.b #0xcd, &P6SEL ; P6SEL`
270			`mov.b &P6SEL, &0x0256`
271			`mov.b #0x32, &P6SEL`
272			`mov.b &P6SEL, &0x0257`
273
274			`mov.b #0x00, &P6IN ; Re-Initialize`
275			`mov.b #0x00, &P6OUT`
276			`mov.b #0x00, &P6DIR`
277			`mov.b #0x00, &P6SEL`
278
279			`mov #0x0006, r15`
280
281
282			`/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */`
283
284			`mov #0x0200, r15 ;# Test Input path`
285			`p1_din_loop:`
286			`mov.b &P1IN, 0(r15)`
287			`inc r15`
288			`cmp #0x0208, r15`
289			`jne p1_din_loop`
290
291
292			`mov.b #0x01, &P1OUT ; Test Output path`
293			`mov #0x1100, r15`
294			`p1_dout_loop:`
295			`rla.b &P1OUT`
296			`inc r15`
297			`cmp #0x1107, r15`
298			`jne p1_dout_loop`
299
300
301			`mov.b #0x01, &P1DIR ; Test Direction register`
302			`mov #0x1200, r15`
303			`p1_dir_loop:`
304			`rla.b &P1DIR`
305			`inc r15`
306			`cmp #0x1207, r15`
307			`jne p1_dir_loop`
308
309
310			`mov.b #0x01, &P1SEL ; Test Function Select register`
311			`mov #0x1300, r15`
312			`p1_sel_loop:`
313			`rla.b &P1SEL`
314			`inc r15`
315			`cmp #0x1307, r15`
316			`jne p1_sel_loop`
317
318
319			`mov.b #0x00, &P1OUT ; Re-Initialize`
320			`mov.b #0x00, &P1DIR`
321			`mov.b #0x00, &P1SEL`
322
323
324			`/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */`
325
326			`mov #0x0210, r15 ;# Test Input path`
327			`p2_din_loop:`
328			`mov.b &P2IN, 0(r15)`
329			`inc r15`
330			`cmp #0x0218, r15`
331			`jne p2_din_loop`
332
333
334			`mov.b #0x01, &P2OUT ; Test Output path`
335			`mov #0x2100, r15`
336			`p2_dout_loop:`
337			`rla.b &P2OUT`
338			`inc r15`
339			`cmp #0x2107, r15`
340			`jne p2_dout_loop`
341
342
343			`mov.b #0x01, &P2DIR ; Test Direction register`
344			`mov #0x2200, r15`
345			`p2_dir_loop:`
346			`rla.b &P2DIR`
347			`inc r15`
348			`cmp #0x2207, r15`
349			`jne p2_dir_loop`
350
351
352			`mov.b #0x01, &P2SEL ; Test Function Select register`
353			`mov #0x2300, r15`
354			`p2_sel_loop:`
355			`rla.b &P2SEL`
356			`inc r15`
357			`cmp #0x2307, r15`
358			`jne p2_sel_loop`
359
360
361			`mov.b #0x00, &P2OUT ; Re-Initialize`
362			`mov.b #0x00, &P2DIR`
363			`mov.b #0x00, &P2SEL`
364
365
366			`/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */`
367
368			`mov #0x0220, r15 ;# Test Input path`
369			`p3_din_loop:`
370			`mov.b &P3IN, 0(r15)`
371			`inc r15`
372			`cmp #0x0228, r15`
373			`jne p3_din_loop`
374
375
376			`mov.b #0x01, &P3OUT ; Test Output path`
377			`mov #0x3100, r15`
378			`p3_dout_loop:`
379			`rla.b &P3OUT`
380			`inc r15`
381			`cmp #0x3107, r15`
382			`jne p3_dout_loop`
383
384
385			`mov.b #0x01, &P3DIR ; Test Direction register`
386			`mov #0x3200, r15`
387			`p3_dir_loop:`
388			`rla.b &P3DIR`
389			`inc r15`
390			`cmp #0x3207, r15`
391			`jne p3_dir_loop`
392
393
394			`mov.b #0x01, &P3SEL ; Test Function Select register`
395			`mov #0x3300, r15`
396			`p3_sel_loop:`
397			`rla.b &P3SEL`
398			`inc r15`
399			`cmp #0x3307, r15`
400			`jne p3_sel_loop`
401
402
403			`mov.b #0x00, &P3OUT ; Re-Initialize`
404			`mov.b #0x00, &P3DIR`
405			`mov.b #0x00, &P3SEL`
406
407
408			`/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */`
409
410			`mov #0x0230, r15 ;# Test Input path`
411			`p4_din_loop:`
412			`mov.b &P4IN, 0(r15)`
413			`inc r15`
414			`cmp #0x0238, r15`
415			`jne p4_din_loop`
416
417
418			`mov.b #0x01, &P4OUT ; Test Output path`
419			`mov #0x4100, r15`
420			`p4_dout_loop:`
421			`rla.b &P4OUT`
422			`inc r15`
423			`cmp #0x4107, r15`
424			`jne p4_dout_loop`
425
426
427			`mov.b #0x01, &P4DIR ; Test Direction register`
428			`mov #0x4200, r15`
429			`p4_dir_loop:`
430			`rla.b &P4DIR`
431			`inc r15`
432			`cmp #0x4207, r15`
433			`jne p4_dir_loop`
434
435
436			`mov.b #0x01, &P4SEL ; Test Function Select register`
437			`mov #0x4300, r15`
438			`p4_sel_loop:`
439			`rla.b &P4SEL`
440			`inc r15`
441			`cmp #0x4307, r15`
442			`jne p4_sel_loop`
443
444
445			`mov.b #0x00, &P4OUT ; Re-Initialize`
446			`mov.b #0x00, &P4DIR`
447			`mov.b #0x00, &P4SEL`
448
449
450			`/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */`
451
452			`mov #0x0240, r15 ;# Test Input path`
453			`p5_din_loop:`
454			`mov.b &P5IN, 0(r15)`
455			`inc r15`
456			`cmp #0x0248, r15`
457			`jne p5_din_loop`
458
459
460			`mov.b #0x01, &P5OUT ; Test Output path`
461			`mov #0x5100, r15`
462			`p5_dout_loop:`
463			`rla.b &P5OUT`
464			`inc r15`
465			`cmp #0x5107, r15`
466			`jne p5_dout_loop`
467
468
469			`mov.b #0x01, &P5DIR ; Test Direction register`
470			`mov #0x5200, r15`
471			`p5_dir_loop:`
472			`rla.b &P5DIR`
473			`inc r15`
474			`cmp #0x5207, r15`
475			`jne p5_dir_loop`
476
477
478			`mov.b #0x01, &P5SEL ; Test Function Select register`
479			`mov #0x5300, r15`
480			`p5_sel_loop:`
481			`rla.b &P5SEL`
482			`inc r15`
483			`cmp #0x5307, r15`
484			`jne p5_sel_loop`
485
486
487			`mov.b #0x00, &P5OUT ; Re-Initialize`
488			`mov.b #0x00, &P5DIR`
489			`mov.b #0x00, &P5SEL`
490
491
492			`/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */`
493
494			`mov #0x0250, r15 ;# Test Input path`
495			`p6_din_loop:`
496			`mov.b &P6IN, 0(r15)`
497			`inc r15`
498			`cmp #0x0258, r15`
499			`jne p6_din_loop`
500
501
502			`mov.b #0x01, &P6OUT ; Test Output path`
503			`mov #0x6100, r15`
504			`p6_dout_loop:`
505			`rla.b &P6OUT`
506			`inc r15`
507			`cmp #0x6107, r15`
508			`jne p6_dout_loop`
509
510
511			`mov.b #0x01, &P6DIR ; Test Direction register`
512			`mov #0x6200, r15`
513			`p6_dir_loop:`
514			`rla.b &P6DIR`
515			`inc r15`
516			`cmp #0x6207, r15`
517			`jne p6_dir_loop`
518
519
520			`mov.b #0x01, &P6SEL ; Test Function Select register`
521			`mov #0x6300, r15`
522			`p6_sel_loop:`
523			`rla.b &P6SEL`
524			`inc r15`
525			`cmp #0x6307, r15`
526			`jne p6_sel_loop`
527
528
529			`mov.b #0x00, &P6OUT ; Re-Initialize`
530			`mov.b #0x00, &P6DIR`
531			`mov.b #0x00, &P6SEL`
532
533
534
535			`/* ---------------------- END OF TEST --------------- */`
536			`end_of_test:`
537			`nop`
538			`br #0xffff`
539
540
541			`/* ---------------------- INTERRUPT VECTORS --------------- */`
542
543			`.section .vectors, "a"`
544			`.word end_of_test ; Interrupt 0 (lowest priority)`
545			`.word end_of_test ; Interrupt 1`
546			`.word end_of_test ; Interrupt 2`
547			`.word end_of_test ; Interrupt 3`
548			`.word end_of_test ; Interrupt 4`
549			`.word end_of_test ; Interrupt 5`
550			`.word end_of_test ; Interrupt 6`
551			`.word end_of_test ; Interrupt 7`
552			`.word end_of_test ; Interrupt 8`
553			`.word end_of_test ; Interrupt 9`
554			`.word end_of_test ; Interrupt 10 Watchdog timer`
555			`.word end_of_test ; Interrupt 11`
556			`.word end_of_test ; Interrupt 12`
557			`.word end_of_test ; Interrupt 13`
558			`.word end_of_test ; Interrupt 14 NMI`
559			`.word main ; Interrupt 15 (highest priority) RESET`