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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.v] - Blame information for rev 2

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                 DIGITAL I/O                               */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the Digital I/O interface:                                           */
27 
/*                                   - Read/Write register access.           */
28 
/*                                   - I/O Functionality.                    */
29 
/*===========================================================================*/
30 
 
31 
initial
32 
   begin
33 
      $display(" ===============================================");
34 
      $display("|                 START SIMULATION              |");
35 
      $display(" ===============================================");
36 
      repeat(5) @(posedge mclk);
37 
      stimulus_done = 0;
38 
 
39 
      // PORT 1: TEST RD/WR REGISTER ACCESS
40 
      //--------------------------------------------------------
41 
      @(r15==16'h0001);
42 
 
43 
      if (mem200 !== 16'h0000) tb_error("====== P1IN  != 0x0000 =====");
44 
      if (mem202 !== 16'h55aa) tb_error("====== P1OUT != 0x55aa =====");
45 
      if (mem204 !== 16'ha55a) tb_error("====== P1DIR != 0xa55a =====");
46 
      if (mem206 !== 16'haa55) tb_error("====== P1IFG != 0xaa55 =====");
47 
      if (mem208 !== 16'h5aa5) tb_error("====== P1IES != 0x5aa5 =====");
48 
      if (mem20A !== 16'h55aa) tb_error("====== P1IE  != 0x55aa =====");
49 
      if (mem20C !== 16'h32cd) tb_error("====== P1SEL != 0x32cd =====");
50 
 
51 
 
52 
      // PORT 2: TEST RD/WR REGISTER ACCESS
53 
      //--------------------------------------------------------
54 
      @(r15==16'h0002);
55 
 
56 
      if (mem210 !== 16'h0000) tb_error("====== P2IN  != 0x0000 =====");
57 
      if (mem212 !== 16'h55aa) tb_error("====== P2OUT != 0x55aa =====");
58 
      if (mem214 !== 16'ha55a) tb_error("====== P2DIR != 0xa55a =====");
59 
      if (mem216 !== 16'haa55) tb_error("====== P2IFG != 0xaa55 =====");
60 
      if (mem218 !== 16'h5aa5) tb_error("====== P2IES != 0x5aa5 =====");
61 
      if (mem21A !== 16'h55aa) tb_error("====== P2IE  != 0x55aa =====");
62 
      if (mem21C !== 16'h32cd) tb_error("====== P2SEL != 0x32cd =====");
63 
 
64 
 
65 
      // PORT 3: TEST RD/WR REGISTER ACCESS
66 
      //--------------------------------------------------------
67 
      @(r15==16'h0003);
68 
 
69 
      if (mem220 !== 16'h0000) tb_error("====== P3IN  != 0x0000 =====");
70 
      if (mem222 !== 16'h55aa) tb_error("====== P3OUT != 0x55aa =====");
71 
      if (mem224 !== 16'ha55a) tb_error("====== P3DIR != 0xa55a =====");
72 
      if (mem226 !== 16'h32cd) tb_error("====== P3SEL != 0x32cd =====");
73 
 
74 
 
75 
      // PORT 4: TEST RD/WR REGISTER ACCESS
76 
      //--------------------------------------------------------
77 
      @(r15==16'h0004);
78 
 
79 
      if (mem230 !== 16'h0000) tb_error("====== P4IN  != 0x0000 =====");
80 
      if (mem232 !== 16'h55aa) tb_error("====== P4OUT != 0x55aa =====");
81 
      if (mem234 !== 16'ha55a) tb_error("====== P4DIR != 0xa55a =====");
82 
      if (mem236 !== 16'h32cd) tb_error("====== P4SEL != 0x32cd =====");
83 
 
84 
 
85 
      // PORT 5: TEST RD/WR REGISTER ACCESS
86 
      //--------------------------------------------------------
87 
      @(r15==16'h0005);
88 
 
89 
      if (mem240 !== 16'h0000) tb_error("====== P5IN  != 0x0000 =====");
90 
      if (mem242 !== 16'h55aa) tb_error("====== P5OUT != 0x55aa =====");
91 
      if (mem244 !== 16'ha55a) tb_error("====== P5DIR != 0xa55a =====");
92 
      if (mem246 !== 16'h32cd) tb_error("====== P5SEL != 0x32cd =====");
93 
 
94 
 
95 
      // PORT 6: TEST RD/WR REGISTER ACCESS
96 
      //--------------------------------------------------------
97 
      @(r15==16'h0006);
98 
 
99 
      if (mem250 !== 16'h0000) tb_error("====== P6IN  != 0x0000 =====");
100 
      if (mem252 !== 16'h55aa) tb_error("====== P6OUT != 0x55aa =====");
101 
      if (mem254 !== 16'ha55a) tb_error("====== P6DIR != 0xa55a =====");
102 
      if (mem256 !== 16'h32cd) tb_error("====== P6SEL != 0x32cd =====");
103 
 
104 
 
105 
      // PORT 1: TEST I/O FUNCTIONALITY
106 
      //--------------------------------------------------------
107 
 
108 
      @(r15==16'h0200) p1_din = 8'h01;
109 
      @(r15==16'h0201) p1_din = 8'h02;
110 
      @(r15==16'h0202) p1_din = 8'h04;
111 
      @(r15==16'h0203) p1_din = 8'h08;
112 
      @(r15==16'h0204) p1_din = 8'h10;
113 
      @(r15==16'h0205) p1_din = 8'h20;
114 
      @(r15==16'h0206) p1_din = 8'h40;
115 
      @(r15==16'h0207) p1_din = 8'h80;
116 
      @(r15==16'h0208);
117 
      if (mem200 !== 16'h0201) tb_error("====== P1IN  != 0x0201 =====");
118 
      if (mem202 !== 16'h0804) tb_error("====== P1IN  != 0x0804 =====");
119 
      if (mem204 !== 16'h2010) tb_error("====== P1IN  != 0x2010 =====");
120 
      if (mem206 !== 16'h8040) tb_error("====== P1IN  != 0x8040 =====");
121 
 
122 
      @(r15==16'h1100);
123 
      if (p1_dout !== 8'h01) tb_error("====== P1DOUT  != 0x01 =====");
124 
      @(r15==16'h1101);
125 
      if (p1_dout !== 8'h02) tb_error("====== P1DOUT  != 0x02 =====");
126 
      @(r15==16'h1102);
127 
      if (p1_dout !== 8'h04) tb_error("====== P1DOUT  != 0x04 =====");
128 
      @(r15==16'h1103);
129 
      if (p1_dout !== 8'h08) tb_error("====== P1DOUT  != 0x08 =====");
130 
      @(r15==16'h1104);
131 
      if (p1_dout !== 8'h10) tb_error("====== P1DOUT  != 0x10 =====");
132 
      @(r15==16'h1105);
133 
      if (p1_dout !== 8'h20) tb_error("====== P1DOUT  != 0x20 =====");
134 
      @(r15==16'h1106);
135 
      if (p1_dout !== 8'h40) tb_error("====== P1DOUT  != 0x40 =====");
136 
      @(r15==16'h1107);
137 
      if (p1_dout !== 8'h80) tb_error("====== P1DOUT  != 0x80 =====");
138 
 
139 
      @(r15==16'h1200);
140 
      if (p1_dout_en !== 8'h01) tb_error("====== P1DIR  != 0x01 =====");
141 
      @(r15==16'h1201);
142 
      if (p1_dout_en !== 8'h02) tb_error("====== P1DIR  != 0x02 =====");
143 
      @(r15==16'h1202);
144 
      if (p1_dout_en !== 8'h04) tb_error("====== P1DIR  != 0x04 =====");
145 
      @(r15==16'h1203);
146 
      if (p1_dout_en !== 8'h08) tb_error("====== P1DIR  != 0x08 =====");
147 
      @(r15==16'h1204);
148 
      if (p1_dout_en !== 8'h10) tb_error("====== P1DIR  != 0x10 =====");
149 
      @(r15==16'h1205);
150 
      if (p1_dout_en !== 8'h20) tb_error("====== P1DIR  != 0x20 =====");
151 
      @(r15==16'h1206);
152 
      if (p1_dout_en !== 8'h40) tb_error("====== P1DIR  != 0x40 =====");
153 
      @(r15==16'h1207);
154 
      if (p1_dout_en !== 8'h80) tb_error("====== P1DIR  != 0x80 =====");
155 
 
156 
      @(r15==16'h1300);
157 
      if (p1_sel !== 8'h01) tb_error("====== P1SEL  != 0x01 =====");
158 
      @(r15==16'h1301);
159 
      if (p1_sel !== 8'h02) tb_error("====== P1SEL  != 0x02 =====");
160 
      @(r15==16'h1302);
161 
      if (p1_sel !== 8'h04) tb_error("====== P1SEL  != 0x04 =====");
162 
      @(r15==16'h1303);
163 
      if (p1_sel !== 8'h08) tb_error("====== P1SEL  != 0x08 =====");
164 
      @(r15==16'h1304);
165 
      if (p1_sel !== 8'h10) tb_error("====== P1SEL  != 0x10 =====");
166 
      @(r15==16'h1305);
167 
      if (p1_sel !== 8'h20) tb_error("====== P1SEL  != 0x20 =====");
168 
      @(r15==16'h1306);
169 
      if (p1_sel !== 8'h40) tb_error("====== P1SEL  != 0x40 =====");
170 
      @(r15==16'h1307);
171 
      if (p1_sel !== 8'h80) tb_error("====== P1SEL  != 0x80 =====");
172 
 
173 
 
174 
      // PORT 2: TEST I/O FUNCTIONALITY
175 
      //--------------------------------------------------------
176 
 
177 
      @(r15==16'h0210) p2_din = 8'h01;
178 
      @(r15==16'h0211) p2_din = 8'h02;
179 
      @(r15==16'h0212) p2_din = 8'h04;
180 
      @(r15==16'h0213) p2_din = 8'h08;
181 
      @(r15==16'h0214) p2_din = 8'h10;
182 
      @(r15==16'h0215) p2_din = 8'h20;
183 
      @(r15==16'h0216) p2_din = 8'h40;
184 
      @(r15==16'h0217) p2_din = 8'h80;
185 
      @(r15==16'h0218);
186 
      if (mem210 !== 16'h0201) tb_error("====== P2IN  != 0x0201 =====");
187 
      if (mem212 !== 16'h0804) tb_error("====== P2IN  != 0x0804 =====");
188 
      if (mem214 !== 16'h2010) tb_error("====== P2IN  != 0x2010 =====");
189 
      if (mem216 !== 16'h8040) tb_error("====== P2IN  != 0x8040 =====");
190 
 
191 
      @(r15==16'h2100);
192 
      if (p2_dout !== 8'h01) tb_error("====== P2DOUT  != 0x01 =====");
193 
      @(r15==16'h2101);
194 
      if (p2_dout !== 8'h02) tb_error("====== P2DOUT  != 0x02 =====");
195 
      @(r15==16'h2102);
196 
      if (p2_dout !== 8'h04) tb_error("====== P2DOUT  != 0x04 =====");
197 
      @(r15==16'h2103);
198 
      if (p2_dout !== 8'h08) tb_error("====== P2DOUT  != 0x08 =====");
199 
      @(r15==16'h2104);
200 
      if (p2_dout !== 8'h10) tb_error("====== P2DOUT  != 0x10 =====");
201 
      @(r15==16'h2105);
202 
      if (p2_dout !== 8'h20) tb_error("====== P2DOUT  != 0x20 =====");
203 
      @(r15==16'h2106);
204 
      if (p2_dout !== 8'h40) tb_error("====== P2DOUT  != 0x40 =====");
205 
      @(r15==16'h2107);
206 
      if (p2_dout !== 8'h80) tb_error("====== P2DOUT  != 0x80 =====");
207 
 
208 
      @(r15==16'h2200);
209 
      if (p2_dout_en !== 8'h01) tb_error("====== P2DIR  != 0x01 =====");
210 
      @(r15==16'h2201);
211 
      if (p2_dout_en !== 8'h02) tb_error("====== P2DIR  != 0x02 =====");
212 
      @(r15==16'h2202);
213 
      if (p2_dout_en !== 8'h04) tb_error("====== P2DIR  != 0x04 =====");
214 
      @(r15==16'h2203);
215 
      if (p2_dout_en !== 8'h08) tb_error("====== P2DIR  != 0x08 =====");
216 
      @(r15==16'h2204);
217 
      if (p2_dout_en !== 8'h10) tb_error("====== P2DIR  != 0x10 =====");
218 
      @(r15==16'h2205);
219 
      if (p2_dout_en !== 8'h20) tb_error("====== P2DIR  != 0x20 =====");
220 
      @(r15==16'h2206);
221 
      if (p2_dout_en !== 8'h40) tb_error("====== P2DIR  != 0x40 =====");
222 
      @(r15==16'h2207);
223 
      if (p2_dout_en !== 8'h80) tb_error("====== P2DIR  != 0x80 =====");
224 
 
225 
      @(r15==16'h2300);
226 
      if (p2_sel !== 8'h01) tb_error("====== P2SEL  != 0x01 =====");
227 
      @(r15==16'h2301);
228 
      if (p2_sel !== 8'h02) tb_error("====== P2SEL  != 0x02 =====");
229 
      @(r15==16'h2302);
230 
      if (p2_sel !== 8'h04) tb_error("====== P2SEL  != 0x04 =====");
231 
      @(r15==16'h2303);
232 
      if (p2_sel !== 8'h08) tb_error("====== P2SEL  != 0x08 =====");
233 
      @(r15==16'h2304);
234 
      if (p2_sel !== 8'h10) tb_error("====== P2SEL  != 0x10 =====");
235 
      @(r15==16'h2305);
236 
      if (p2_sel !== 8'h20) tb_error("====== P2SEL  != 0x20 =====");
237 
      @(r15==16'h2306);
238 
      if (p2_sel !== 8'h40) tb_error("====== P2SEL  != 0x40 =====");
239 
      @(r15==16'h2307);
240 
      if (p2_sel !== 8'h80) tb_error("====== P2SEL  != 0x80 =====");
241 
 
242 
 
243 
      // PORT 3: TEST I/O FUNCTIONALITY
244 
      //--------------------------------------------------------
245 
 
246 
      @(r15==16'h0220) p3_din = 8'h01;
247 
      @(r15==16'h0221) p3_din = 8'h02;
248 
      @(r15==16'h0222) p3_din = 8'h04;
249 
      @(r15==16'h0223) p3_din = 8'h08;
250 
      @(r15==16'h0224) p3_din = 8'h10;
251 
      @(r15==16'h0225) p3_din = 8'h20;
252 
      @(r15==16'h0226) p3_din = 8'h40;
253 
      @(r15==16'h0227) p3_din = 8'h80;
254 
      @(r15==16'h0228);
255 
      if (mem220 !== 16'h0201) tb_error("====== P3IN  != 0x0201 =====");
256 
      if (mem222 !== 16'h0804) tb_error("====== P3IN  != 0x0804 =====");
257 
      if (mem224 !== 16'h2010) tb_error("====== P3IN  != 0x2010 =====");
258 
      if (mem226 !== 16'h8040) tb_error("====== P3IN  != 0x8040 =====");
259 
 
260 
      @(r15==16'h3100);
261 
      if (p3_dout !== 8'h01) tb_error("====== P3DOUT  != 0x01 =====");
262 
      @(r15==16'h3101);
263 
      if (p3_dout !== 8'h02) tb_error("====== P3DOUT  != 0x02 =====");
264 
      @(r15==16'h3102);
265 
      if (p3_dout !== 8'h04) tb_error("====== P3DOUT  != 0x04 =====");
266 
      @(r15==16'h3103);
267 
      if (p3_dout !== 8'h08) tb_error("====== P3DOUT  != 0x08 =====");
268 
      @(r15==16'h3104);
269 
      if (p3_dout !== 8'h10) tb_error("====== P3DOUT  != 0x10 =====");
270 
      @(r15==16'h3105);
271 
      if (p3_dout !== 8'h20) tb_error("====== P3DOUT  != 0x20 =====");
272 
      @(r15==16'h3106);
273 
      if (p3_dout !== 8'h40) tb_error("====== P3DOUT  != 0x40 =====");
274 
      @(r15==16'h3107);
275 
      if (p3_dout !== 8'h80) tb_error("====== P3DOUT  != 0x80 =====");
276 
 
277 
      @(r15==16'h3200);
278 
      if (p3_dout_en !== 8'h01) tb_error("====== P3DIR  != 0x01 =====");
279 
      @(r15==16'h3201);
280 
      if (p3_dout_en !== 8'h02) tb_error("====== P3DIR  != 0x02 =====");
281 
      @(r15==16'h3202);
282 
      if (p3_dout_en !== 8'h04) tb_error("====== P3DIR  != 0x04 =====");
283 
      @(r15==16'h3203);
284 
      if (p3_dout_en !== 8'h08) tb_error("====== P3DIR  != 0x08 =====");
285 
      @(r15==16'h3204);
286 
      if (p3_dout_en !== 8'h10) tb_error("====== P3DIR  != 0x10 =====");
287 
      @(r15==16'h3205);
288 
      if (p3_dout_en !== 8'h20) tb_error("====== P3DIR  != 0x20 =====");
289 
      @(r15==16'h3206);
290 
      if (p3_dout_en !== 8'h40) tb_error("====== P3DIR  != 0x40 =====");
291 
      @(r15==16'h3207);
292 
      if (p3_dout_en !== 8'h80) tb_error("====== P3DIR  != 0x80 =====");
293 
 
294 
      @(r15==16'h3300);
295 
      if (p3_sel !== 8'h01) tb_error("====== P3SEL  != 0x01 =====");
296 
      @(r15==16'h3301);
297 
      if (p3_sel !== 8'h02) tb_error("====== P3SEL  != 0x02 =====");
298 
      @(r15==16'h3302);
299 
      if (p3_sel !== 8'h04) tb_error("====== P3SEL  != 0x04 =====");
300 
      @(r15==16'h3303);
301 
      if (p3_sel !== 8'h08) tb_error("====== P3SEL  != 0x08 =====");
302 
      @(r15==16'h3304);
303 
      if (p3_sel !== 8'h10) tb_error("====== P3SEL  != 0x10 =====");
304 
      @(r15==16'h3305);
305 
      if (p3_sel !== 8'h20) tb_error("====== P3SEL  != 0x20 =====");
306 
      @(r15==16'h3306);
307 
      if (p3_sel !== 8'h40) tb_error("====== P3SEL  != 0x40 =====");
308 
      @(r15==16'h3307);
309 
      if (p3_sel !== 8'h80) tb_error("====== P3SEL  != 0x80 =====");
310 
 
311 
 
312 
      // PORT 4: TEST I/O FUNCTIONALITY
313 
      //--------------------------------------------------------
314 
 
315 
      @(r15==16'h0230) p4_din = 8'h01;
316 
      @(r15==16'h0231) p4_din = 8'h02;
317 
      @(r15==16'h0232) p4_din = 8'h04;
318 
      @(r15==16'h0233) p4_din = 8'h08;
319 
      @(r15==16'h0234) p4_din = 8'h10;
320 
      @(r15==16'h0235) p4_din = 8'h20;
321 
      @(r15==16'h0236) p4_din = 8'h40;
322 
      @(r15==16'h0237) p4_din = 8'h80;
323 
      @(r15==16'h0238);
324 
      if (mem230 !== 16'h0201) tb_error("====== P4IN  != 0x0201 =====");
325 
      if (mem232 !== 16'h0804) tb_error("====== P4IN  != 0x0804 =====");
326 
      if (mem234 !== 16'h2010) tb_error("====== P4IN  != 0x2010 =====");
327 
      if (mem236 !== 16'h8040) tb_error("====== P4IN  != 0x8040 =====");
328 
 
329 
      @(r15==16'h4100);
330 
      if (p4_dout !== 8'h01) tb_error("====== P4DOUT  != 0x01 =====");
331 
      @(r15==16'h4101);
332 
      if (p4_dout !== 8'h02) tb_error("====== P4DOUT  != 0x02 =====");
333 
      @(r15==16'h4102);
334 
      if (p4_dout !== 8'h04) tb_error("====== P4DOUT  != 0x04 =====");
335 
      @(r15==16'h4103);
336 
      if (p4_dout !== 8'h08) tb_error("====== P4DOUT  != 0x08 =====");
337 
      @(r15==16'h4104);
338 
      if (p4_dout !== 8'h10) tb_error("====== P4DOUT  != 0x10 =====");
339 
      @(r15==16'h4105);
340 
      if (p4_dout !== 8'h20) tb_error("====== P4DOUT  != 0x20 =====");
341 
      @(r15==16'h4106);
342 
      if (p4_dout !== 8'h40) tb_error("====== P4DOUT  != 0x40 =====");
343 
      @(r15==16'h4107);
344 
      if (p4_dout !== 8'h80) tb_error("====== P4DOUT  != 0x80 =====");
345 
 
346 
      @(r15==16'h4200);
347 
      if (p4_dout_en !== 8'h01) tb_error("====== P4DIR  != 0x01 =====");
348 
      @(r15==16'h4201);
349 
      if (p4_dout_en !== 8'h02) tb_error("====== P4DIR  != 0x02 =====");
350 
      @(r15==16'h4202);
351 
      if (p4_dout_en !== 8'h04) tb_error("====== P4DIR  != 0x04 =====");
352 
      @(r15==16'h4203);
353 
      if (p4_dout_en !== 8'h08) tb_error("====== P4DIR  != 0x08 =====");
354 
      @(r15==16'h4204);
355 
      if (p4_dout_en !== 8'h10) tb_error("====== P4DIR  != 0x10 =====");
356 
      @(r15==16'h4205);
357 
      if (p4_dout_en !== 8'h20) tb_error("====== P4DIR  != 0x20 =====");
358 
      @(r15==16'h4206);
359 
      if (p4_dout_en !== 8'h40) tb_error("====== P4DIR  != 0x40 =====");
360 
      @(r15==16'h4207);
361 
      if (p4_dout_en !== 8'h80) tb_error("====== P4DIR  != 0x80 =====");
362 
 
363 
      @(r15==16'h4300);
364 
      if (p4_sel !== 8'h01) tb_error("====== P4SEL  != 0x01 =====");
365 
      @(r15==16'h4301);
366 
      if (p4_sel !== 8'h02) tb_error("====== P4SEL  != 0x02 =====");
367 
      @(r15==16'h4302);
368 
      if (p4_sel !== 8'h04) tb_error("====== P4SEL  != 0x04 =====");
369 
      @(r15==16'h4303);
370 
      if (p4_sel !== 8'h08) tb_error("====== P4SEL  != 0x08 =====");
371 
      @(r15==16'h4304);
372 
      if (p4_sel !== 8'h10) tb_error("====== P4SEL  != 0x10 =====");
373 
      @(r15==16'h4305);
374 
      if (p4_sel !== 8'h20) tb_error("====== P4SEL  != 0x20 =====");
375 
      @(r15==16'h4306);
376 
      if (p4_sel !== 8'h40) tb_error("====== P4SEL  != 0x40 =====");
377 
      @(r15==16'h4307);
378 
      if (p4_sel !== 8'h80) tb_error("====== P4SEL  != 0x80 =====");
379 
 
380 
 
381 
      // PORT 5: TEST I/O FUNCTIONALITY
382 
      //--------------------------------------------------------
383 
 
384 
      @(r15==16'h0240) p5_din = 8'h01;
385 
      @(r15==16'h0241) p5_din = 8'h02;
386 
      @(r15==16'h0242) p5_din = 8'h04;
387 
      @(r15==16'h0243) p5_din = 8'h08;
388 
      @(r15==16'h0244) p5_din = 8'h10;
389 
      @(r15==16'h0245) p5_din = 8'h20;
390 
      @(r15==16'h0246) p5_din = 8'h40;
391 
      @(r15==16'h0247) p5_din = 8'h80;
392 
      @(r15==16'h0248);
393 
      if (mem240 !== 16'h0201) tb_error("====== P5IN  != 0x0201 =====");
394 
      if (mem242 !== 16'h0804) tb_error("====== P5IN  != 0x0804 =====");
395 
      if (mem244 !== 16'h2010) tb_error("====== P5IN  != 0x2010 =====");
396 
      if (mem246 !== 16'h8040) tb_error("====== P5IN  != 0x8040 =====");
397 
 
398 
      @(r15==16'h5100);
399 
      if (p5_dout !== 8'h01) tb_error("====== P5DOUT  != 0x01 =====");
400 
      @(r15==16'h5101);
401 
      if (p5_dout !== 8'h02) tb_error("====== P5DOUT  != 0x02 =====");
402 
      @(r15==16'h5102);
403 
      if (p5_dout !== 8'h04) tb_error("====== P5DOUT  != 0x04 =====");
404 
      @(r15==16'h5103);
405 
      if (p5_dout !== 8'h08) tb_error("====== P5DOUT  != 0x08 =====");
406 
      @(r15==16'h5104);
407 
      if (p5_dout !== 8'h10) tb_error("====== P5DOUT  != 0x10 =====");
408 
      @(r15==16'h5105);
409 
      if (p5_dout !== 8'h20) tb_error("====== P5DOUT  != 0x20 =====");
410 
      @(r15==16'h5106);
411 
      if (p5_dout !== 8'h40) tb_error("====== P5DOUT  != 0x40 =====");
412 
      @(r15==16'h5107);
413 
      if (p5_dout !== 8'h80) tb_error("====== P5DOUT  != 0x80 =====");
414 
 
415 
      @(r15==16'h5200);
416 
      if (p5_dout_en !== 8'h01) tb_error("====== P5DIR  != 0x01 =====");
417 
      @(r15==16'h5201);
418 
      if (p5_dout_en !== 8'h02) tb_error("====== P5DIR  != 0x02 =====");
419 
      @(r15==16'h5202);
420 
      if (p5_dout_en !== 8'h04) tb_error("====== P5DIR  != 0x04 =====");
421 
      @(r15==16'h5203);
422 
      if (p5_dout_en !== 8'h08) tb_error("====== P5DIR  != 0x08 =====");
423 
      @(r15==16'h5204);
424 
      if (p5_dout_en !== 8'h10) tb_error("====== P5DIR  != 0x10 =====");
425 
      @(r15==16'h5205);
426 
      if (p5_dout_en !== 8'h20) tb_error("====== P5DIR  != 0x20 =====");
427 
      @(r15==16'h5206);
428 
      if (p5_dout_en !== 8'h40) tb_error("====== P5DIR  != 0x40 =====");
429 
      @(r15==16'h5207);
430 
      if (p5_dout_en !== 8'h80) tb_error("====== P5DIR  != 0x80 =====");
431 
 
432 
      @(r15==16'h5300);
433 
      if (p5_sel !== 8'h01) tb_error("====== P5SEL  != 0x01 =====");
434 
      @(r15==16'h5301);
435 
      if (p5_sel !== 8'h02) tb_error("====== P5SEL  != 0x02 =====");
436 
      @(r15==16'h5302);
437 
      if (p5_sel !== 8'h04) tb_error("====== P5SEL  != 0x04 =====");
438 
      @(r15==16'h5303);
439 
      if (p5_sel !== 8'h08) tb_error("====== P5SEL  != 0x08 =====");
440 
      @(r15==16'h5304);
441 
      if (p5_sel !== 8'h10) tb_error("====== P5SEL  != 0x10 =====");
442 
      @(r15==16'h5305);
443 
      if (p5_sel !== 8'h20) tb_error("====== P5SEL  != 0x20 =====");
444 
      @(r15==16'h5306);
445 
      if (p5_sel !== 8'h40) tb_error("====== P5SEL  != 0x40 =====");
446 
      @(r15==16'h5307);
447 
      if (p5_sel !== 8'h80) tb_error("====== P5SEL  != 0x80 =====");
448 
 
449 
 
450 
      // PORT 6: TEST I/O FUNCTIONALITY
451 
      //--------------------------------------------------------
452 
 
453 
      @(r15==16'h0250) p6_din = 8'h01;
454 
      @(r15==16'h0251) p6_din = 8'h02;
455 
      @(r15==16'h0252) p6_din = 8'h04;
456 
      @(r15==16'h0253) p6_din = 8'h08;
457 
      @(r15==16'h0254) p6_din = 8'h10;
458 
      @(r15==16'h0255) p6_din = 8'h20;
459 
      @(r15==16'h0256) p6_din = 8'h40;
460 
      @(r15==16'h0257) p6_din = 8'h80;
461 
      @(r15==16'h0258);
462 
      if (mem250 !== 16'h0201) tb_error("====== P6IN  != 0x0201 =====");
463 
      if (mem252 !== 16'h0804) tb_error("====== P6IN  != 0x0804 =====");
464 
      if (mem254 !== 16'h2010) tb_error("====== P6IN  != 0x2010 =====");
465 
      if (mem256 !== 16'h8040) tb_error("====== P6IN  != 0x8040 =====");
466 
 
467 
      @(r15==16'h6100);
468 
      if (p6_dout !== 8'h01) tb_error("====== P6DOUT  != 0x01 =====");
469 
      @(r15==16'h6101);
470 
      if (p6_dout !== 8'h02) tb_error("====== P6DOUT  != 0x02 =====");
471 
      @(r15==16'h6102);
472 
      if (p6_dout !== 8'h04) tb_error("====== P6DOUT  != 0x04 =====");
473 
      @(r15==16'h6103);
474 
      if (p6_dout !== 8'h08) tb_error("====== P6DOUT  != 0x08 =====");
475 
      @(r15==16'h6104);
476 
      if (p6_dout !== 8'h10) tb_error("====== P6DOUT  != 0x10 =====");
477 
      @(r15==16'h6105);
478 
      if (p6_dout !== 8'h20) tb_error("====== P6DOUT  != 0x20 =====");
479 
      @(r15==16'h6106);
480 
      if (p6_dout !== 8'h40) tb_error("====== P6DOUT  != 0x40 =====");
481 
      @(r15==16'h6107);
482 
      if (p6_dout !== 8'h80) tb_error("====== P6DOUT  != 0x80 =====");
483 
 
484 
      @(r15==16'h6200);
485 
      if (p6_dout_en !== 8'h01) tb_error("====== P6DIR  != 0x01 =====");
486 
      @(r15==16'h6201);
487 
      if (p6_dout_en !== 8'h02) tb_error("====== P6DIR  != 0x02 =====");
488 
      @(r15==16'h6202);
489 
      if (p6_dout_en !== 8'h04) tb_error("====== P6DIR  != 0x04 =====");
490 
      @(r15==16'h6203);
491 
      if (p6_dout_en !== 8'h08) tb_error("====== P6DIR  != 0x08 =====");
492 
      @(r15==16'h6204);
493 
      if (p6_dout_en !== 8'h10) tb_error("====== P6DIR  != 0x10 =====");
494 
      @(r15==16'h6205);
495 
      if (p6_dout_en !== 8'h20) tb_error("====== P6DIR  != 0x20 =====");
496 
      @(r15==16'h6206);
497 
      if (p6_dout_en !== 8'h40) tb_error("====== P6DIR  != 0x40 =====");
498 
      @(r15==16'h6207);
499 
      if (p6_dout_en !== 8'h80) tb_error("====== P6DIR  != 0x80 =====");
500 
 
501 
      @(r15==16'h6300);
502 
      if (p6_sel !== 8'h01) tb_error("====== P6SEL  != 0x01 =====");
503 
      @(r15==16'h6301);
504 
      if (p6_sel !== 8'h02) tb_error("====== P6SEL  != 0x02 =====");
505 
      @(r15==16'h6302);
506 
      if (p6_sel !== 8'h04) tb_error("====== P6SEL  != 0x04 =====");
507 
      @(r15==16'h6303);
508 
      if (p6_sel !== 8'h08) tb_error("====== P6SEL  != 0x08 =====");
509 
      @(r15==16'h6304);
510 
      if (p6_sel !== 8'h10) tb_error("====== P6SEL  != 0x10 =====");
511 
      @(r15==16'h6305);
512 
      if (p6_sel !== 8'h20) tb_error("====== P6SEL  != 0x20 =====");
513 
      @(r15==16'h6306);
514 
      if (p6_sel !== 8'h40) tb_error("====== P6SEL  != 0x40 =====");
515 
      @(r15==16'h6307);
516 
      if (p6_sel !== 8'h80) tb_error("====== P6SEL  != 0x80 =====");
517 
 
518 
 
519 
      stimulus_done = 1;
520 
   end
521 
 

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